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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 11 occurrences of 11 keywords
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Results
Found 5 publication records. Showing 5 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
46 | Alberto Delmas Lascorz, Mostafa Mahmoud, Ali Hadi Zadeh, Milos Nikolic 0002, Kareem Ibrahim, Christina Giannoula, Ameer Abdelhadi, Andreas Moshovos |
Atalanta: A Bit is Worth a "Thousand" Tensor Values. |
ASPLOS (2) |
2024 |
DBLP DOI BibTeX RDF |
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33 | Mohamed Shalan, Vincent John Mooney III |
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management. |
CODES |
2002 |
DBLP DOI BibTeX RDF |
Atalanta, SoCDMMU, real-time operating systems., two-level memory management, real-time systems, embedded systems, System-on-a-Chip, dynamic memory management |
33 | Albrecht P. Stroele, Frank Mayer |
Methods to reduce test application time for accumulator-based self-test. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
accumulator-based self-test, test length minimization, simulation-based reseeding method, random pattern testable circuits, reverse order simulation, hard fault detection, optimal input value, test length reductions, data path blocks, BIST scheme, ATALANTA fault simulation, combinatorial circuit testing, built-in self test, fault coverage, embedded processor, test pattern generators, circuit optimization, test application time reduction, forward simulation |
30 | Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay |
Flip-flop chaining architecture for power-efficient scan during test application. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
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30 | Santanu Chattopadhyay, Naveen Choudhary |
Genetic Algorithm based Approach for Low Power Combinational Circuit Testing. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
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