Search results for "RLC-circuit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
53	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Figures of merit to characterize the importance of on-chip inductance.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
53	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Figures of Merit to Characterize the Importance of On-Chip Inductance.	DAC	1998	DBLP DOI BibTeX RDF
47	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Equivalent Elmore delay for RLC trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
42	Selim G. Akl, Weiguang Yao	A Parallel Approach Eliminates Measurement Perturbations in RLC Circuits.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	RLC-circuit, parallel computation, measurement, dynamical system, oscillation, perturbation, damping
41	Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter	Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses.	DATE	2002	DBLP DOI BibTeX RDF
36	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Signal waveform characterization in RLC trees.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
30	Ning Mi, Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan, Hao Yu 0001	General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
25	Liang Yin, Lei He 0001	An efficient analytical model of coupled on-chip RLC interconnects.	ASP-DAC	2001	DBLP DOI BibTeX RDF
25	Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi	Practical considerations for passive reduction of RLC circuits.	ICCAD	1999	DBLP DOI BibTeX RDF
25	Lawrence T. Pillage, Ronald A. Rohrer	Asymptotic waveform evaluation for timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
25	Zi-Ming Wang 0001, Xudong Zhao 0001, Xiaodi Li, Xianfu Zhang, Rui Mu	Energy-Based Control for Switched Uncertain Port-Controlled Hamiltonian Systems With Its Application to RLC Circuit Systems.	IEEE Trans. Syst. Man Cybern. Syst.	2024	DBLP DOI BibTeX RDF
25	Matap Shankar, Swaroop Nandan Bora	Generalized Ulam-Hyers-Rassias Stability of Solution for the Caputo Fractional Non-instantaneous Impulsive Integro-differential Equation and Its Application to Fractional RLC Circuit.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
25	Yao Huang, Yao-Lin Jiang, Kang-Li Xu	Model Order Reduction of RLC Circuit System Modeled by Port-Hamiltonian Structure.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
25	Issam El Hamdi, Alessandro N. Vargas, Hassane Bouzahir, Ricardo C. L. F. Oliveira, Leonardo Acho	Robust stability of stochastic systems with varying delays: Application to RLC circuit with intermittent closed-loop.	Appl. Math. Comput.	2021	DBLP DOI BibTeX RDF
25	Kristian Haska, Dusan Zorica, Stevan M. Cveticanin	Fractional RLC circuit in transient and steady state regimes.	Commun. Nonlinear Sci. Numer. Simul.	2021	DBLP DOI BibTeX RDF
25	Krzysztof Oprzedkiewicz	A Discrete, Fractional Order, Memory-Effective State Space Model of a RLC Circuit.	AUTOMATION	2021	DBLP DOI BibTeX RDF
25	Ling Zhou, Zhi-zhong Tan, Qing-hua Zhang	A fractional-order multifunctional n-step honeycomb RLC circuit network.	Frontiers Inf. Technol. Electron. Eng.	2017	DBLP DOI BibTeX RDF
25	José Francisco Gómez-Aguilar, Victor Fabian Morales-Delgado, Marco Antonio Taneco-Hernández, Dumitru Baleanu, Ricardo Fabricio Escobar-Jiménez, Maysaa Mohamed Al Qurashi	Analytical Solutions of the Electrical RLC Circuit via Liouville-Caputo Operators with Local and Non-Local Kernels.	Entropy	2016	DBLP DOI BibTeX RDF
25	Rui Zhou 0011, Diyi Chen, Herbert H. C. Iu	Fractional-Order 2 × n RLC Circuit Network.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
25	Dukgwon Lee, Seunghyun Beak, Youngmin Lee, Eunser Lee, Jungkook Kim, Gyung-Leen Park, Taikyeong Jeong	Minimize the delay of parasitic capacitance and modeling in RLC circuit.	ICHIT	2009	DBLP DOI BibTeX RDF	Elmore, parasitic capacitance, delay, interconnection, oscillator
25	Tadashi Kawai, Yasuaki Nakashima, Yoshihiro Kokubo, Isao Ohta	Dual-Band Wilkinson Power Dividers Using a Series RLC Circuit.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
25	Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai	Large scale RLC circuit analysis using RLCG-MNA formulation.	DATE	2006	DBLP DOI BibTeX RDF
25	Aziz S. Inan, Peter M. Osterberg	Special singularity integrals encountered in electric circuits [RLC circuit examples].	ISCAS (2)	2005	DBLP DOI BibTeX RDF
24	Roland W. Freund, Peter Feldmann	Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation.	DATE	1998	DBLP DOI BibTeX RDF	linear passive multi-terminal circuit, matrix-Pade approximants, Lanczos-type process, interconnect analysis, simulation, synthesis, transfer function
22	Nahi H. Abdul Ghani, Farid N. Najm	Handling inductance in early power grid verification.	ICCAD	2006	DBLP DOI BibTeX RDF
19	Taeyong Je, Yungseon Eo	Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching.	ISQED	2006	DBLP DOI BibTeX RDF
19	Saed G. Younis, Thomas F. Knight Jr.	Non-dissipative rail drivers for adiabatic circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	driver circuits, distributed parameter networks, lumped parameter networks, passive networks, nondissipative rail drivers, adiabatic circuits, CMOS charge recovery logic, energy dissipation per operation, SCRL circuits, rail waveform generation, rail driver circuit, multiple harmonics, harmonic rail driver, passive reactive components, trimmed transmission line segments, CMOS logic circuits, CMOS circuits, harmonics
16	Tak K. Tang, Michel S. Nakhla	Analysis of high-speed VLSI interconnects using the asymptotic waveform evaluation technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
14	Federico Fontana, Federico Avanzini	Computation of Delay-Free Nonlinear Digital Filter Networks: Application to Chaotic Circuits and Intracellular Signal Transduction.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
14	Hideo Nakano, Hirohiko Honda, Hideaki Okazaki	Canards in a slow-fast continuous piecewise linear vector field.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
14	Kevin M. Lepak, Min Xu, Jun Chen 0008, Lei He 0001	Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	VLSI physical design automation and on-chip inductance, net ordering, noise minimization, signal integrity, shielding
14	Guoan Zhong, Cheng-Kok Koh, Kaushik Roy 0001	On-chip interconnect modeling by wire duplication.	ICCAD	2002	DBLP DOI BibTeX RDF