Search results for "Substrate"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Contact merging algorithm for efficient substrate noise analysis in large scale circuits.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	noise coupling, substrate modeling, signal integrity, mixed-signal circuits, substrate noise, noise analysis
102	Rashid Farivar, Simon Kristiansson, Fredrik Ingvarson, Kjell O. Jeppson	Evaluation of using active circuitry for substrate noise suppression.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	active noise decoupling, substrate modeling, substrate coupling
76	Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson	Noise Interaction Between Power Distribution Grids and Substrate.	ISQED	2008	DBLP DOI BibTeX RDF	power supply, Substrate noise
72	Qing Su, Jamil Kawa, Charles C. Chiang, Yehia Massoud	Accurate modeling of substrate resistive coupling for floating substrates.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Analog and mixed signal, floating substrate, substrate modeling, system-on-chip, substrate coupling
71	Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata	Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
69	João M. S. Silva, L. Miguel Silveira	Issues in parallelizing multigrid-based substrate model extraction and analysis.	SBCCI	2004	DBLP DOI BibTeX RDF	grid computing, multigrid, substrate coupling
69	Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man	High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects.	DAC	2004	DBLP DOI BibTeX RDF	modeling, model order reduction, substrate noise
69	Anne E. Gattiker, Wojciech Maly	Smart Substrate MCMs.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	smart substrate, testing, cost model, MCM
69	Ranjit Gharpurey, Srinath Hosur	Transform domain techniques for efficient extraction of substrate parasitics.	ICCAD	1997	DBLP DOI BibTeX RDF	Green Function, orthonormal transforms, parasitics, substrate coupling
67	Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man	SWAN: high-level simulation methodology for digital substrate noise generation.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
67	Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens	High-level simulation of substrate noise generation including power supply noise coupling.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
64	Rajendran Panda, Savithri Sundareswaran, David T. Blaauw	On the interaction of power distribution network with substrate.	ISLPED	2001	DBLP DOI BibTeX RDF	power grid analysis, substrate analysis, substrate coupled noise, substrate noise
62	Song Guo, Hoi Lee	A low-power active substrate-noise decoupling circuit with feedforward compensation for mixed-signal SoCs.	ISLPED	2006	DBLP DOI BibTeX RDF	active substrate noise decoupling, feedforward frequency compensation, substrate noise suppression, system-on-a-chip
62	Bruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan	Low-cost diagnosis of defects in MCM substrate interconnections.	VTS	1996	DBLP DOI BibTeX RDF	low-cost diagnosis, MCM substrate interconnections, substrate interconnect defects, defect location, defect size, fault diagnosis, integrated circuit testing, fault location, multichip modules, integrated circuit interconnections, fault-dictionary, substrates
61	Payam Heydari	Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulators.	DAC	2003	DBLP DOI BibTeX RDF	DS modulators, mixed-signal integrated circuits, jitter, phase-locked loop, phase noise, substrate noise
61	Ming-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo	ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process.	ISQED	2002	DBLP DOI BibTeX RDF	ESD, ESD protection circuit, substrate-triggered technique
61	Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen	Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.	DAC	2002	DBLP DOI BibTeX RDF	di/dt noise, low-noise digital design, supply current shaping, optimization, substrate noise, clock distribution networks
61	Eelco Schrik, N. P. van der Meijs	Combined BEM/FEM substrate resistance modeling.	DAC	2002	DBLP DOI BibTeX RDF	modeling, finite element method, boundary element method, substrate noise
59	Minlan Yu, Yung Yi, Jennifer Rexford, Mung Chiang	Rethinking virtual network embedding: substrate support for path splitting and migration.	Comput. Commun. Rev.	2008	DBLP DOI BibTeX RDF	path migration, path splitting, virtual network embedding, optimization, network virtualization
59	Minsik Cho, Hongjoong Shin, David Z. Pan	Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
59	Weize Xu, Eby G. Friedman	A substrate noise circuit for accurately testing mixed-signal ICs.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
59	J. Briaire, K. S. Krisch	Principles of substrate crosstalk generation in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
59	Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel	PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits.	PATMOS	2000	DBLP DOI BibTeX RDF
55	Adil Koukab, Catherine Dehollain, Michel J. Declercq	HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC.	DAC	2002	DBLP DOI BibTeX RDF	mixed-signal noise, supply noise, noise, numerical analysis, boundary-element-method, substrate noise, switching circuits, substrate coupling
53	Xiren Wang, Wenjian Yu, Zeyi Wang, Xianlong Hong	An improved direct boundary element method for substrate coupling resistance extraction.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	condensing and sparsifying matrix, direct boundary element method, substrate resistance extraction
53	Nasser Masoumi, Mohamed I. Elmasry, Safieddin Safavi-Naeini, Haydar Hadi	A Novel Analytical Model for Evaluation of Substrate Crosstalk in VLSI Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	Substrate coupling modeling, image method, Green's function
53	João Paulo Costa, Mike Chou, L. Miguel Silveira	Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's.	DATE	1998	DBLP DOI BibTeX RDF	Eigenfunction, Eigenpair, Fast Fourier Transform, Discrete Cosine Transform, Eigenvalue, Mixed-Signal, Substrate Coupling
53	Edoardo Charbon, Ranjit Gharpurey, Alberto L. Sangiovanni-Vincentelli, Robert G. Meyer	Semi-analytical techniques for substrate characterization in the design of mixed-signal ICs.	ICCAD	1996	DBLP DOI BibTeX RDF	Green Function, placement, trend analysis, substrate
53	Kevin J. Kerns, Ivan L. Wemple, Andrew T. Yang	Stable and efficient reduction of substrate model networks using congruence transforms.	ICCAD	1995	DBLP DOI BibTeX RDF	mixed-signal integrated circuits, rc network reduction, congruence transform, pade approximation, lanczos process, stability, voronoi tesselation, substrate noise
51	Minsik Cho, David Z. Pan	Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
51	Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Input port reduction for efficient substrate extraction in large scale IC's.	ISCAS	2008	DBLP DOI BibTeX RDF
51	Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay	Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance.	DATE	2005	DBLP DOI BibTeX RDF
51	Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi	CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects.	ASP-DAC	2004	DBLP DOI BibTeX RDF
51	Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen	SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation.	ICCAD	2003	DBLP DOI BibTeX RDF
51	Hongmei Li, Jorge Carballido, Harry H. Yu, Vladimir I. Okhmatovski, Elyse Rosenbaum, Andreas C. Cangellaris	Comprehensive frequency-dependent substrate noise analysis using boundary element methods.	ICCAD	2002	DBLP DOI BibTeX RDF
51	Ming-Dou Ker, Kuo-Chun Hsu	On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
51	Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata	Measurements and analyses of substrate noise waveform inmixed-signal IC environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
51	Rajesh Pendurkar, Craig A. Tovey, Abhijit Chatterjee	Single-probe traversal optimization for testing of MCM substrate interconnections.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
51	Jae J. Chang, Myunghee Lee, Sungyong Jung, Martin A. Brooke, Nan M. Jokerst, D. Scott Wills	Fully differential current-input CMOS amplifier front-end suppressing mixed signal substrate noise for optoelectronic applications.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
51	Kazushige Horio, Yasuji Fuseya, Hiroyuki Kusuki, Hisayoshi Yanai	Simplified simulations of GaAs MESFET's with semi-insulating substrate compensated by deep levels.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
47	Neda Nazemifard, Jacob Masliyah, Subir Bhattacharjee	Role of Patterned Surface Charge Heterogeneity on Particle Deposition.	ICMENS	2005	DBLP DOI BibTeX RDF
47	R. K. Jarwal, Durga Misra	Degradation Of Nmosfets During High-Field Injection With Reverse Biased Voltage At Source And Drain Junctions.	VLSI Design	2001	DBLP DOI BibTeX RDF
47	Ranjit Gharpurey, Edoardo Charbon	Substrate Coupling: Modeling, Simulation and Design Perspectives.	ISQED	2004	DBLP DOI BibTeX RDF	digital noise, impact ionization, constraint-driven optimization, fast fourier transform, discrete cosine transform, finite element method, boundary element method, power supply noise, substrate noise, substrate coupling
45	Sebastian Risi, Joel Lehman, Kenneth O. Stanley	Evolving the placement and density of neurons in the hyperneat substrate.	GECCO	2010	DBLP DOI BibTeX RDF	substrate evolution, neuroevolution, neat, hyperneat
45	Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He 0001, Robi Dutta, Xianlong Hong	Diffusion-driven congestion reduction for substrate topological routing.	ISPD	2009	DBLP DOI BibTeX RDF	congestion reduction, ic package, substrate routing, diffusion, routability
45	Parastoo Nikaeen, Boris Murmann, Robert W. Dutton	Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs.	ISQED	2008	DBLP DOI BibTeX RDF	flash ADC, comparator, SNR, substrate noise
45	Meng-Fan Chang, Kuei-Ann Wen	Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	supply noise, SRAM, substrate noise, ROM
45	Scott Schneider 0001, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos	Factory: An Object-Oriented Parallel Programming Substrate for Deep Multiprocessors.	HPCC	2005	DBLP DOI BibTeX RDF	Multithreading substrate, Object-oriented parallel programming, Deep parallel architectures, Multiparadigm parallelism, Portability, Programmability
45	T. Smedes, N. P. van der Meijs, Arjan J. van Genderen	Extraction of circuit models for substrate cross-talk.	ICCAD	1995	DBLP DOI BibTeX RDF	Substrate Cross-talk, Layout Verification, Boundary Element Method, Green's Function
43	Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske	Optimization of active circuits for substrate noise suppression.	ISCAS	2008	DBLP DOI BibTeX RDF
43	Jeff Rose, Cyrus P. Hall, Antonio Carzaniga	Spinneret: A Log Random Substrate for P2P Networks.	IPDPS	2007	DBLP DOI BibTeX RDF
43	Vincent Binet, Yvon Savaria, Michel Meunier, Yves Gagnon	Modeling the Substrate Noise Injected by a DC-DC Converter.	ISCAS	2007	DBLP DOI BibTeX RDF
43	Jeong-Yeol Kim, Ho-Soon Shin, Jong-Bae Lee, Moon-Hyun Yoo, Jeong-Taek Kong	SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory Design.	ISQED	2007	DBLP DOI BibTeX RDF
43	Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram	Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
43	Hongyan Jian, Zhangwen Tang, Jie He 0003, Jinglan He, Min Hao	Standard CMOS technology on-chip inductors with pn junctions substrate isolation.	ASP-DAC	2005	DBLP DOI BibTeX RDF
43	Xiren Wang, Wenjian Yu, Zeyi Wang	Substrate resistance extraction with direct boundary element method.	ASP-DAC	2005	DBLP DOI BibTeX RDF
43	Hiroyuki Kotani, Masaya Takasaki, Takeshi Mizuno, Takaaki Nara	A SAW Tactile Display Using a Glass Substrate.	WHC	2005	DBLP DOI BibTeX RDF
43	Enrique Barajas, Luis Elvira, Miguel A. Méndez, Ferran Martorell, Diego Mateo, José Luis González 0001	Discrete and continuous substrate noise spectrum dependence on digital circuit characteristics.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
43	Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske	Modeling of substrate noise block properties for early prediction.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
43	Yulei Weng, Alex Doboli	Digital cell macro-model with regular substrate template and EKV based MOSFET model.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF
43	Frank Ghenassia, Narayanan Vijaykrishnan, Mary Jane Irwin	Analyzing software influences on substrate noise: an ADC perspective.	ICCAD	2004	DBLP DOI BibTeX RDF
43	Gong-Xin Yu, Byung-Hoon Park, Praveen Chandramohan, Al Geist, Nagiza F. Samatova	In-Silico Prediction of Surface Residue Clusters for Enzyme-Substrate Specificity.	CSB	2004	DBLP DOI BibTeX RDF
43	Ferran Martorell, Diego Mateo, Xavier Aragonès	Modeling and Evaluation of Substrate Noise Induced by Interconnects.	DATE	2003	DBLP DOI BibTeX RDF
43	Eelco Schrik, Patrick M. Dewilde, N. P. van der Meijs	Theoretical and practical validation of combined BEM/FEM substrate resistance modeling.	ICCAD	2002	DBLP DOI BibTeX RDF
43	Dicle Ozis, Kartikeya Mayaram, Terri S. Fiez	An efficient modeling approach for substrate noise coupling analysis.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
43	Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata	Test circuits for substrate noise evaluation in CMOS digital ICs.	ASP-DAC	2001	DBLP DOI BibTeX RDF
43	Tatsuo Nakajima	Towards Universal Software Substrate for Distributed Embedded Systems.	WORDS	2001	DBLP DOI BibTeX RDF
43	Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata	Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation.	ISQED	2001	DBLP DOI BibTeX RDF
43	Edoardo Charbon, Ranjit Gharpurey, Robert G. Meyer, Alberto L. Sangiovanni-Vincentelli	Substrate optimization based on semi-analytical techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
43	So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu	A multi-probe approach for MCM substrate testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
40	Paul C. F. Tong, Ping-Ping Xu, Wensong Chen, John Hui, Patty Z. Q. Liu	A novel substrate-triggered ESD protection structure for a bus switch IC with on-chip substrate-pump.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
37	Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates.	ISQED	2008	DBLP DOI BibTeX RDF	signal integrity, mixed-signal circuits, Substrate coupling
37	Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He 0001, Tianpei Zhang, Robi Dutta, Xianlong Hong	Topological routing to maximize routability for package substrate.	DAC	2008	DBLP DOI BibTeX RDF	IC package, substrate routing, system in package
37	Xiaojun Ma, Fabrizio Lombardi	Multi-Site and Multi-Probe Substrate Testing on an ATE.	DFT	2006	DBLP DOI BibTeX RDF	substrate testing, multi-probe, ATE, MCM, manufacturing test, multi-site
37	Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram	A green function-based parasitic extraction method for inhomogeneous substrate layers.	DAC	2005	DBLP DOI BibTeX RDF	green function, substrate noise, parasitic extraction
36	Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He 0001, Tianpei Zhang, Robi Dutta, Xianlong Hong	Substrate Topological Routing for High-Density Packages.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
36	Wai Leng Cheong, Brian E. Owens, Hui En Pham, Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram	Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes.	ISQED	2009	DBLP DOI BibTeX RDF
36	Masaya Takasaki, Hiroyuki Kotani, Takeshi Mizuno	A Glass Substrate Transducer for Surface Acoustic Wave Tactile Display.	RO-MAN	2007	DBLP DOI BibTeX RDF
36	Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada	Design of Active Substrate Noise Canceller using Power Supply di/dt Detector.	ASP-DAC	2007	DBLP DOI BibTeX RDF
36	William H. Kao, Xiaopeng Dong	Digital Block Modeling and Substrate Noise Aware Floorplanning for Mixed Signal SOCs.	ISCAS	2007	DBLP DOI BibTeX RDF
36	Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Substrate Noise Reduction Based On Noise Aware Cell Design.	ISCAS	2007	DBLP DOI BibTeX RDF
36	Sankar P. Debnath, Ganesh P. Kumar 0002, Sukumar Jairam	Calibration Based Methods for Substrate Modeling and Noise Analysis for Mixed-Signal SoCsc.	VLSI Design	2007	DBLP DOI BibTeX RDF
36	Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man	Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
36	Sheng-Chih Lin, Kaustav Banerjee	An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management.	ICCAD	2006	DBLP DOI BibTeX RDF
36	Dongsheng Ma	Automatic substrate switching circuit for on-chip adaptive power supply system.	ISCAS	2006	DBLP DOI BibTeX RDF
36	Subodh M. Reddy, Rajeev Murgai	Accurate Substrate Noise Analysis Based on Library Module Characterization.	VLSI Design	2006	DBLP DOI BibTeX RDF
36	Amir H. Ajami, Kaustav Banerjee, Massoud Pedram	Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
36	Sankar P. Debnath, Sukumar Jairam, H. Udayakumar	A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses.	VLSI Design	2005	DBLP DOI BibTeX RDF
36	Adil Koukab, Kaustav Banerjee, Michel J. Declercq	Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
36	Meng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai	Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs.	ISQED	2004	DBLP DOI BibTeX RDF
36	Henry H. Y. Chan, Zeljko Zilic	Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach.	ISQED	2004	DBLP DOI BibTeX RDF
36	Hai Lan, Zhiping Yu, Robert W. Dutton	A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design.	ISQED	2003	DBLP DOI BibTeX RDF
36	Thomas Brandtner, Robert Weigel	Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network.	DATE	2002	DBLP DOI BibTeX RDF
36	Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Win	ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
36	Ali M. Niknejad, Ranjit Gharpurey, Robert G. Meyer	Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
36	Tadahiro Kuroda, Takayasu Sakurai	Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
36	Ivan L. Wemple, Andrew T. Yang	Integrated circuit substrate coupling models based on Voronoi tessellation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
35	C. Patrick Yue, S. Simon Wong	Design Strategy of On-Chip Inductors for Highly Integrated RF Systems.	DAC	1999	DBLP DOI BibTeX RDF	patterned ground shield, spiral inductor, substrate loss, interconnects, quality factor, substrate coupling, skin effect
33	Yujian Cheng, Wei Hong 0002, Ke Wu	Design of a multimode beamforming network based on the scattering matrix analysis.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	beamforming network (BFN), multibeam antenna, substrate integrated waveguide (SIW), multimode
33	Rajesh Pendurkar, Abhijit Chatterjee, Craig A. Tovey	Optimal single probe traversal algorithm for testing of MCM substrat.	ICCD	1996	DBLP DOI BibTeX RDF	optimal single probe traversal algorithm, MCM substrate testing, single probe, MCM interconnects, total distance, terminal pad, interconnection net, tour construction, arbitrary insertion, shuffling techniques, total traversal cost, probe traversal time, electronics industry, semiconductor chips, traveling salesman problem, multichip modules, multichip modules