Search results for "Test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
80	Nancy S. Eickelmann, Debra J. Richardson	An Evaluation of Software Test Environment Architectures.	ICSE	1996	DBLP BibTeX RDF	CITE, CONVEX Integrated Test Environment, PROLOG Test Environment, Version II, PROTest II, Software Architectural Analysis Method, TAOS, Testing with Analysis and Oracle Support, architecturally imposed constraints, environment functions allocation, implementation structures, processing algorithms, software test environment architectures, test development, test failure analysis, test measurement, test process automation, performance, software architecture, programming environments, program testing, software reusability, extensibility, reusability, software performance evaluation, portability, functionality, computer aided software engineering, software portability, testing tools, data representation, reference architecture, modifiability, test management, modifications, test planning, test execution, SAAM
79	Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara	A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	test plan grouping, test controllers, partly compacted test plan tables, RTL data paths, test length
79	Makoto Sugihara, Hiroto Yasuura	Optimization of Test Accesses with a Combined BIST and External Test Scheme.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	external test, CBET, test access, external pins, BIST, test scheduling, test time, test bus
70	Naina Mittal, Ira Acharya	An Open Framework for Managed Regression Testing.	TestCom	2003	DBLP DOI BibTeX RDF	managed testing, networking equipment, test bench, hierarchical test case management, test plan tree, framework deployment, test-cycle reduction, testing tool collaboration, regression testing, black-box testing, Test automation, test framework, test planning, test execution, test scripts
67	M. Miegler, Werner Wolz	Development of test programs in a virtual test environment.	VTS	1996	DBLP DOI BibTeX RDF	test programs development, virtual test environment, quality-assured mixed-signal test programs, standard test description language, VTML, Virtual Test Modelling Language, standardized description models, test system resources, equivalent simulation models, VLSI, integrated circuit testing, design for testability, integrated circuit design, circuit CAD, automatic test software
66	Jacob Savir	Generator choices for delay test.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test
65	Albrecht P. Stroele, Frank Mayer	Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	loop folding, test configuration, test register, built-in self-test, test schedule, test application time, Accumulator
64	Wu-Tung Cheng	Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
64	Debaditya Mukherjee, Melvin A. Breuer	An IEEE 1149.1 Compliant Test Control Architecture.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	test control, local test control, distributed test control, dynamic test control, built-in self-test, design-for-test, boundary scan, test bus
60	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
60	Valentin Muresan, Xiaojun Wang 0001, Valentina Muresan, Mircea Vladutiu	Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	distribution-graph based approach, extended tree growing technique, power-constrained block-test scheduling, unequal-length block-test scheduling, power dissipation constraints, test concurrency, assigned power dissipation limits, balanced test power dissipation, least mean square error function, global priority function, system-level test scheduling algorithm, scheduling, VLSI, fault diagnosis, logic testing, high level synthesis, integrated circuit testing, automatic test pattern generation, trees (mathematics), least mean squares methods
60	Hiroshi Date, Michinobu Nakao, Kazumi Hatayama	A parallel sequential test generation system DESCARTES based on real-valued logic simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	parallel sequential test generation system, DESCARTES, real-valued logic simulation, redundant fault identification program, algorithmic test generation program, ISCAS '89 benchmark sequential circuits, distributed processing environment oriented system, concurrent accelerative test generation, parallel algorithms, computational complexity, VLSI, fault diagnosis, logic testing, redundancy, design for testability, sequential circuits, logic CAD, VLSI design, stuck-at faults, automatic test generation, synchronous sequential circuits, automatic test software, test quality
59	Erik Jan Marinissen	The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	system chips, test protocol, test protocol scheduling, test generation, expansion, embedded cores
59	Erik Larsson, Zebo Peng	An Integrated Framework for the Design and Optimization of SOC Test Solutions.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	test access mechanism design, test resource placement, test conflicts, power consumption, test scheduling, SOC test, test resource partitioning
59	Sukumar Nandi, Parimal Pal Chaudhuri	Theory and applications of cellular automata for synthesis of easily testable combinational logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuck-at faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph
58	Carsten Wegener, Michael Peter Kennedy	Test Development Through Defect and Test Escape Level Estimation for Data Converters.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	mixed-signal and analog test, economics of test, test and post-test data analysis
58	Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa	Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	test-per-clock testing, test pattern compression, zero aliasing error, built-in self test, test response compaction
58	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
57	Huaikou Miao, Ling Liu	A Test Class Framework for Generating Test Cases from Z Specifications.	ICECCS	2000	DBLP DOI BibTeX RDF	test class framework, object-oriented concept, test case generation system, formal specification, oracles, test data, Z specifications, test framework, TCGS
57	Albrecht P. Stroele, Frank Mayer	Methods to reduce test application time for accumulator-based self-test.	VTS	1997	DBLP DOI BibTeX RDF	accumulator-based self-test, test length minimization, simulation-based reseeding method, random pattern testable circuits, reverse order simulation, hard fault detection, optimal input value, test length reductions, data path blocks, BIST scheme, ATALANTA fault simulation, combinatorial circuit testing, built-in self test, fault coverage, embedded processor, test pattern generators, circuit optimization, test application time reduction, forward simulation
56	Jung-Cheun Lien, Melvin A. Breuer	Test program synthesis for modules and chips having boundary scan.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	Board and system test, test controllers, test program synthesis, built-in self-test, design-for-test, boundary scan
55	Abhijit Jas, Kartik Mohanram, Nur A. Touba	An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Test Vector Compression, External Testing, Weighted Pseudo-Random Testing, Built-In Self-Test, Embedded Processor, System-on-a-Chip, Automatic Test Equipment, At-Speed Testing, Scan Chains, Deterministic Testing
55	Susana Stoica	A lifecycle approach to design validation is it necessary? Is it feasible?	ITC	1998	DBLP DOI BibTeX RDF	Lifecycle test, system approach to design and test, Robust Test Methodology (RTM), Design Validation (DV), software /hardware test methods, requirements specifications test, QA-type testing, Test Plan (TP) boilerplate, test optimization considering full lifecycle DV, black box testing, white box testing
55	Kuen-Jong Lee, Cheng-I Huang	A hierarchical test control architecture for core based design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	hierarchical test control architecture, SOC design, IEEE P1500 Working Group, test standard, IEEE 1149.1 cores, parallel testing capabilities, hierarchical test control mechanism, deeply embedded cores, hierarchical test access, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, IEEE standards, test architecture, core based design
54	Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis	An efficient comparative concurrent Built-In Self-Test technique.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	off-line test generation, comparative concurrent BIST, test latency, windowed-CBIST, VLSI, logic testing, built-in self test, integrated circuit testing, concurrent engineering, VLSI circuits, test sequence, hardware overhead
54	Michel Renovell, Joan Figueras, Yervant Zorian	Test of RAM-based FPGA: methodology and application to the interconnect.	VTS	1997	DBLP DOI BibTeX RDF	RAM-based FPGA, manufacturing test procedure, user test procedure, orthogonal test configuration, diagonal-1 test configuration, diagonal-2 test configuration, field programmable gate arrays, interconnect
54	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
54	Chih-Pin Su, Cheng-Wen Wu	A Graph-Based Approach to Power-Constrained SOC Test Scheduling.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	test integration, test scheduling, test access mechanism (TAM), SOC testing, test power, system-on-chip (SOC)
54	T. Haulin	Built-in parametric test for controlled impedance I/Os.	VTS	1997	DBLP DOI BibTeX RDF	controlled impedance I/Os, built-in parametric test, full DC parametrics, full speed AC tests, lower cost ATE, differential signal I/Os, single-ended signal I/Os, short circuit proof drivers, B9 test method, bidirectional I/O, differential receivers, differential transmitters, diagnostic tests, narrow pulse test, contact test, high speed test logic, built-in self test, functional test, boundary scan, static tests
54	Qing Xie 0003, Atif M. Memon	Designing and comparing automated test oracles for GUI-based software applications.	ACM Trans. Softw. Eng. Methodol.	2007	DBLP DOI BibTeX RDF	GUI state, user interfaces, graphical user interfaces, widgets, Test oracles, GUI testing
53	Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita	Test sequence compaction for sequential circuits with reset states.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
53	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
53	Diogo José Costa Alves, Edna Barros	A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns.	SBCCI	2009	DBLP DOI BibTeX RDF	LBIST, compressed test patterns, test, SoC, self-test
53	Fidel Muradali, Janusz Rajski	A self-driven test structure for pseudorandom testing of non-scan sequential circuits.	VTS	1996	DBLP DOI BibTeX RDF	self-driven test structure, primary inputs, nonscan sequential circuits, test point structure, parallel pseudorandom test patterns, test mode flag, stuck-at fault coverage, ISCAS-89 benchmarks, logic testing, built-in self test, integrated circuit testing, design for testability, sequential circuits, BIST, automatic testing, circuit under test
53	Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	TOF: a tool for test pattern generation optimization of an FPGA application oriented test.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG
53	Ozgur Sinanoglu	Low Cost Scan Test by Test Correlation Utilization.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	test correlation, scan architecture design, test data compression, scan-based testing
53	Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch	An optimized BIST test pattern generator for delay testing.	VTS	1997	DBLP DOI BibTeX RDF	BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
53	Kalpesh Zinjuwadia, Perry Alexander	DVTG and Test Harnessing using Rosetta Specifications.	ECBS	2004	DBLP DOI BibTeX RDF	Rosetta, DVTG, Test Initialization, Test Harnessing, XML, Test Vectors, Test Requirements, Test Scenarios
52	Ozgur Sinanoglu, Alex Orailoglu	Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
52	Andrew Flint	MCM Test Strategy Synthesis from Chip Test and Board Test Approaches.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	board test, chip test, case studies, automatic test equipment
52	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators.	VTS	2000	DBLP DOI BibTeX RDF	Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model
51	Achintya Halder, Soumendu Bhattacharya, Ganesh Srinivasan, Abhijit Chatterjee	A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback Mode.	VLSI Design	2005	DBLP DOI BibTeX RDF	System-level test, Loop-back test, wireless transceiver test, Analog and mixed-signal test, RF test, Specification test
51	Zhiyuan He 0002, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi	Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Thermal-aware testing, Test scheduling, SoC testing
51	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
51	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
51	Thomas J. Ostrand, Aaron Anodide, Herbert Foster, Tarak Goradia	A Visual Test Development Environment for GUI Systems.	ISSTA	1998	DBLP DOI BibTeX RDF	GUI-based system, capture/reply, test maintenance, visual editor, testing, test generation, test coverage, test designer, test scenario
50	Abhijit Chatterjee, Jacob A. Abraham	Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	Built-in self-test, test generation, design-for-testability, iterative logic array, pseudo-exhaustive test
50	Hideyuki Ichihara, Tomoo Inoue	Generating Small Test Sets for Test Compression/Decompression Scheme Using Statistical Coding.	DELTA	2002	DBLP DOI BibTeX RDF	statistical code, test generation, ATE, test compression, test compaction
50	Erik Larsson, Stina Edbom	Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
50	Guangyu Huang, Cher Ming Tan	Reverse Breakdown Voltage Measurement for Power P+NN+ Rectifier.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Forced voltage test, Forced current test, PIV test, Minimum required test time, Destruction during test
49	Paul Chang, Brion L. Keller, Sarala Paliwal	Effective parallel processing techniques for the generation of test data for a logic built-in self test system.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data
49	Irith Pomeranz, Sudhakar M. Reddy	Forming N-detection test sets without test generation.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	test generation, stuck-at faults, Bridging faults, n-detection test sets
49	Irith Pomeranz, Sudhakar M. Reddy	On the Compaction of Test Sets Produced by Genetic Optimization.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test generation, test compaction, genetic optimization, n-detection test sets
49	Roberto Bevacqua, Luca Guerrazzi, Franco Fummi	SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation.	EUROMICRO	1996	DBLP DOI BibTeX RDF	test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences
48	Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee	Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	wafer probe test, test yield, loopback test, DFT, RF test, low-cost test
48	Hong-Sik Kim, Sungho Kang 0001, Michael S. Hsiao	A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Keyword System on a chip, Test compression, Low power testing, Scan testing
48	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	A class of sequential circuits with combinational test generation complexity under single-fault assumption.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
48	Yiorgos Makris, Jamison Collins, Alex Orailoglu	Fast hierarchical test path construction for DFT-free controller-datapath circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fast hierarchical test path construction, DFT-free controller-datapath circuits, transparency based scheme, locally generated vectors, global design test, influence tables, valid control state sequences, module testing, fault coverage levels, vector counts, logic testing, test generation, automatic test pattern generation, ATPG, computational cost reduction
48	Franco Fummi, Donatella Sciuto	Implicit test pattern generation constrained to cellular automata embedding.	VTS	1997	DBLP DOI BibTeX RDF	implicit test pattern generation, cellular automata embedding, test sequence identification, autonomous finite state machine, off-line self-testable circuit, BIST strategy, deterministic test sequences, MCNC benchmarks, controller, built-in self test, stuck-at faults, ASIC design, circuit under test
48	J. M. Gilbert, Ian M. Bell	The Effectiveness of Test in Controlling Quality Costs: A Conformability Analysis Based Approach.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	test escapes, test capability, electronics design, quality, test coverage, design for test, process capability
47	Markus Seuring	Combining Scan Test and Built-in Self Test.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	MBIST, BIST, scan test, production test, stress test
47	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Test sequence compaction by reduced scan shift and retiming.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	reduced scan shift, full scan designed circuits, computational complexity, logic testing, timing, transformation, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
47	Soumitra Bose, Vishwani D. Agrawal	Sequential logic path delay test generation by symbolic analysis.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions
47	S. Cremoux, Christophe Fagot, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	A new test pattern generation method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
47	Subhrajit Bhattacharya, Sujit Dey	H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.	VTS	1996	DBLP DOI BibTeX RDF	H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology
47	M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor	Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume.	ITC	2002	DBLP DOI BibTeX RDF	compact test sets, ATPG, fault coverage, stuck-at faults, test length, Test point insertion, gate-delay faults
47	Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara	Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors.	ETS	2007	DBLP DOI BibTeX RDF	Dynamically reconfigurable processors, optimal contexts, test frames, self-test, test application time
46	Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal	Finite state machine synthesis with fault tolerant test function.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	Design for combinational test generation, finite state machine synthesis, test function embedding, synthesis for testability, fault-tolerant design
46	Jochen Rivoir	Low-Cost Analog Signal Generation Using a Pulse-Density Modulated Digital ATE Channel.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	low-cost ATE, multi-site test, mixed-signal test, concurrent test, low-cost test, test resource partitioning
46	James A. Jones, Mary Jean Harrold	Test-Suite Reduction and Prioritization for Modified Condition/Decision Coverage.	ICSM	2001	DBLP DOI BibTeX RDF	test-suite prioritization, software testing, regression testing, test-suite reduction, test-suite minimization
46	Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting	Syndrome Simulation And Syndrome Test For Unscanned Interconnects.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	unscanned interconnects, syndrome test methodology, event driven syndrome simulation, boundary scan environment, faulty syndromes, fault-free syndromes, tolerable error rate, partially scanned PCB, board level testing, test pattern generation, boundary scan testing, test length, MCM, set covering problem, simulation algorithm, weighted random patterns, test cost reduction
46	Qizhang Yin, William R. Eisenstadt, Tian Xia	Wireless System for Microwave Test Signal Generation.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	wireless test, RF IC, RF BIST, LNA test, microwave test, embedded test
46	Erik Larsson, Zebo Peng	Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	test set selection, TAM design, power consumption, hot-spots, Test scheduling, design exploration
45	Toshiyuki Maeda, Kozo Kinoshita	Memory reduction of IDDQ test compaction for internal and external bridging faults.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
45	Arno Kunzmann, Frank Böhland	Self-test of sequential circuits with deterministic test pattern sequences.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Deterministic Test Pattern Sequences, Field-Programmable Gate-Arrays (FPGAs), Design-for-Testability, Sequential Circuits, Automatic Test Pattern Generation (ATPG), Self-Test
45	Irith Pomeranz, Sudhakar M. Reddy	On improving genetic optimization based test generation.	ED&TC	1997	DBLP DOI BibTeX RDF	propagation Citation: I. Pomeranz, S.M. Reddy, On improving genetic optimization based test generation, edtc, pp.506, 1997 European Design and Test Conference (ED&TC '97), 1997 Peer Review Notice, Give Us Feedback Usage of this product signifies your acceptance of the Terms of Use. var addtoMethod=1, var AddURL = escape(http://doi.ieeecomputersociety.org/), var AddTitle = escape(On improving genetic optimization based test generation), Open Download Liferay.Portlet.onLoad({ canEditTitle: false, columnPos: 1, isStatic: 'end', namespacedId: 'p_p_id_digitallibraryabstract_WAR_plugins_INSTANCE_DjbO_', portletId: 'digitallibraryabstract_WAR_plugins_INSTANCE_DjbO' }), genetic algorithms, test generation, fault coverage, activation, benchmark circuit, crossover operator, genetic optimization
45	Li Chen, Srivaths Ravi 0001, Anand Raghunathan, Sujit Dey	A scalable software-based self-test methodology for programmable processors.	DAC	2003	DBLP DOI BibTeX RDF	scalability, microprocessor, at-speed test, software-based self-test, test program, manufacturing test
45	Nilanjan Mukherjee, Ramesh Karri	Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	data-path architectures, response compactor, concurrency, built-in self test, high-level synthesis, on-line test, pattern generator, test function
45	Sheng Zhang 0008, Sharad C. Seth, Bhargab B. Bhattacharya	Efficient Test Compaction for Pseudo-Random Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	built-in testing, test-data compression, Test compaction, pseudo-random testing
45	Zahra Sadat Ebadi, André Ivanov	Design of an Optimal Test Access Architecture Using a Genetic Algorithm.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	Optimal testing time, test data width, Genetic Algorithm, Test Access Mechanism (TAM), SOC testing, Embedded core testing
45	Marcel Jacomet, Roger Wälti, Lukas Winzenried, Jaime Perez, Martin Gysel	ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test bench, test machine, CAT-tool, ProTest, FPGA, VHDL, rapid prototyping, Verilog-HDL
44	Biranchinath Sahu, Abhijit Chatterjee	Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	test transfer function model, AC testing, optimization, fault simulation
44	Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, Luís Rolíndez	Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Analogue fault simulation, Catastrophic and parametric faults, Process deviations, Analogue test, Statistical modeling
44	Hans A. R. Manhaeve, Johan Verfaillie, B. Straka, J. P. Cornil	Application of Supply Current Testing to Analogue Circuits, Towards a Structural Analogue Test Methodology.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	supply current test, I DD, I DDX monitor, analog test, structural test, mixed-signal test, current monitor
44	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
44	Jacob Savir	Delay Test Generation: A Hardware Perspective.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	transition test, skewed-load delay test, shift dependency, cellular automata, linear feedback shift register, delay test, pseudo-random test
44	Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo	An Efficient PRPG Strategy By Utilizing Essential Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	PRPG, essential fault, multiple polynomial, Gauss elimination, pseudorandom test pattern, multivariable linear equation, deterministic test set, random pattern resistant circuit, don't care value, intelligent heuristic, ISCAS-85 benchmark, ISCAS-89 benchmark, built-in self test, BIST, fault coverage, LFSR, test length, hardware overhead, multiple seed
44	Oliver F. Haberl, Thomas Kropf	HIST: A hierarchical self test methodology for chips, boards, and systems.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	Boundary-scan architecture, hierarchical self test, self test synthesis, built-in self test (BIST), system test
44	Jiajing Zhuo, Chen Meng, Minghu Zou	A Task Scheduling Algorithm of Single Processor Parallel Test System.	SNPD (1)	2007	DBLP DOI BibTeX RDF	Auto test system(ATS), Multi-threading technique, Task scheduling algorithm, Algorithm time complexity, Parallel test
44	Stina Edbom, Erik Larsson	An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
44	Dong Hyun Baik, Kewal K. Saluja	State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
44	Kohei Miyase, Seiji Kajihara	Optimal Scan Tree Construction with Test Vector Modification for Test Compression.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
44	Anshuman Chandra, Krishnendu Chakrabarty	Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	decompression architecture, precomputed test sets, system-on-a-chip testing, test set encoding, variable-to-variable-length codes, automatic test equipment (ATE), testing time, embedded core testing
44	Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara	A DFT Selection Method for Reducing Test Application Time of System-on-Chips.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	wrapper, design for test, test scheduling, test access mechanism
44	Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li 0001, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin	A built-in self-test and self-diagnosis scheme for embedded SRAM.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	self-diagnosis scheme, fault diagnosis, fault diagnosis, built-in self test, built-in self-test, system-on-chip, memory test, SRAM chips, embedded SRAM
44	S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault	Test configurations to enhance the testability of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector
44	Anshuman Chandra, Krishnendu Chakrabarty	Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	decompression architecture, precomputed test sets, test set encoding, system-on-a-chip test, variable-to-variable-length codes, Automatic test equipment (ATE), embedded core testing
44	Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham	A novel test generation approach for parametric faults in linear analog circuits .	VTS	1996	DBLP DOI BibTeX RDF	digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits
44	M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor	Compact test sets for industrial circuits.	VTS	1995	DBLP DOI BibTeX RDF	compact test sets, industrial circuits, binary logic elements, three-state elements, compaction oriented decision making, heuristics, logic testing, integrated circuit testing, automatic test pattern generation, combinational circuits, automatic testing, multivalued logic circuits, test patterns, bidirectionals, xor gates, or gates, test set size
44	Scott Davidson 0001, Nur A. Touba	Guest Editors' Introduction: Progress in Test Compression.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	tester memory, don't-care bits, X values, test compression, test vectors, test data volume