Search results for "mask-programmable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
83	Narendra V. Shenoy, Jamil Kawa, Raul Camposano	Design automation for mask programmable fabrics.	DAC	2004	DBLP DOI BibTeX RDF	mask programmable fabrics, integrated circuits
62	Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini	A comparison between mask- and field-programmable routing structures on industrial FPGA architectures.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	mask-programmable, FPGA, routing, interconnect architectures
43	Fabio Campi, Luca Ciccarelli, Claudio Mucci	Sustainable (re-) configurable solutions for the high volume SoC market.	IPDPS	2008	DBLP DOI BibTeX RDF
31	Jay B. Brockman, Sheng Li 0007, Peter M. Kogge, Amit Kashyap, Mohammad M. Mojarradi	Design of a mask-programmable memory/multiplier array using G4-FET technology.	DAC	2008	DBLP DOI BibTeX RDF	G4-FET, gate array
31	Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone	Design and design automation of rectification logic for engineering change.	ASP-DAC	2005	DBLP DOI BibTeX RDF
28	Jonathan Rose	Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract).	DAC	1991	DBLP BibTeX RDF
21	David Marple	An MPGA-Like FPGA.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
19	Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, Chotei Zukeran	Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits.	ISMVL	2001	DBLP DOI BibTeX RDF
19	Fernanda Gusmão de Lima, Eduardo D'Avila, Mauricio Moraes, Marcelo Lubaszewski, Ricardo Reis 0001	A Self-Testing Mask Programmable Matrix Using Built-in Current Sensing.	LATW	2000	DBLP BibTeX RDF
19	Saburo Muroga	Mask-Programmable Gate Arrays.	The VLSI Handbook	1999	DBLP DOI BibTeX RDF
19	Fernanda Lima 0001, Marcelo O. Johann, José Luís Almada Güntzel, Eduardo D'Avila, Luigi Carro, Ricardo Augusto da Luz Reis	Designing a Mask Programmable Matrix for Sequential Circuits.	VLSI	1999	DBLP BibTeX RDF
16	Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer	Regular Routing Architecture for a LUT-based MPGA.	ISVLSI	2006	DBLP DOI BibTeX RDF
16	Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer	Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
16	Pierre G. Paulin	DATE Panel: Chips of the Future: Soft, Crunchy or Hard?	DATE	2004	DBLP DOI BibTeX RDF
12	Deepak D. Sherlekar	Design considerations for regular fabrics.	ISPD	2004	DBLP DOI BibTeX RDF	structured ASIC, regular fabric
12	Vijay Lakamraju, Russell Tessier	Tolerating operational faults in cluster-based FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
12	Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González	Circuit Design using Resonant Tunneling Diodes.	VLSI Design	1998	DBLP DOI BibTeX RDF	Quantum device, Pipelining, Multiple-Valued Logic, Nanoelectronics, Resonant Tunneling Diode
12	Massoud Pedram, Bahman S. Nobandegani, Bryan Preas	Design and analysis of segmented routing channels for row-based FPGA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF