Search results for "time-interleaved"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
61	David Camarero, Jean-François Naviner, Patrick Loumeau	Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters.	SBCCI	2004	DBLP DOI BibTeX RDF	digital calibration, parallel ADC, sample-time errors, time-interleaved, adaptive filters, clock skew
53	Qingqi Dou, Jacob A. Abraham	Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems.	VTS	2008	DBLP DOI BibTeX RDF	Time-Interleaved ADC, Timing Mismatch, Mixed-signal testing, Low-cost test, High speed testing
42	Jonas Elbornsson, Fredrik Gustafsson, Jan-Erik Eklund	Blind equalization of time errors in a time-interleaved ADC system.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
39	Afshin Haftbaradaran, Kenneth W. Martin	Mismatch compensation techniques using random data for time-interleaved A/D converters.	ISCAS	2006	DBLP DOI BibTeX RDF
38	Kamal El-Sankary, Ali Assi 0001, Mohamad Sawan	New sampling method to improve the SFDR of time-interleaved ADCs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
38	Naoki Kurosawa, Haruo Kobayashi 0001, Kensuke Kobayashi	Channel linearity mismatch effects in time-interleaved ADC systems.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
30	Christian Vogel 0001, Håkan Johansson	Time-interleaved analog-to-digital converters: status and future directions.	ISCAS	2006	DBLP DOI BibTeX RDF
30	Guillaume Ferré, Maher Jridi, Lilian Bossuet, Bertrand Le Gal, Dominique Dallet	A new orthogonal online digital calibration for time-interleaved analog-to-digital converters.	ISCAS	2008	DBLP DOI BibTeX RDF
30	Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst	Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter.	ISCAS	2007	DBLP DOI BibTeX RDF
30	Franco Maloberti, Yunyoung Choi	86 dB DR Cross-Coupled Time-Interleaved xx ADC for Audio Signal Band with 322 µA Current Consumption.	ISCAS	2007	DBLP DOI BibTeX RDF
30	D. Morin, Frédéric Normandin, Marie-Eve Grandmaison, H. Dang, Yvon Savaria, Mohamad Sawan	An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters.	IWSOC	2004	DBLP DOI BibTeX RDF
24	Jonas Elbornsson, Kalle Folkesson, Jan-Erik Eklund	Measurement verification of estimation method for time errors in a time-interleaved A/D converter system.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
23	Daeik D. Kim, Martin A. Brooke	Time-interleaved switched-capacitor filter for reconfigurable triple-band delta-sigma converter.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
23	Alessandro Cabrini, Franco Maloberti, Riccardo Rovatti, Gianluca Setti	On-line calibration of offset and gain mismatch in time-interleaved ADC using a sampled-data chaotic bit-stream.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Munkyo Seo, Mark J. W. Rodwell	Generalized Blind Mismatch Correction for a Two-Channel Time-Interleaved ADC: Analytic Approach.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Vijay Divi, Gregory W. Wornell	Scalable blind calibration of timing skew in high-resolution time-interleaved ADCs.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Koushik De, Santiram Kal	A Low Power 6-Bit A/D Converter Achieving 10-Bit Resolution for MEMS Sensor Interface Using Time-Interleaved Delta Modulation.	VLSI Design	2006	DBLP DOI BibTeX RDF
22	Minho Kwon, Jungyoon Lee, Gunhee Han	A time-interleaved switched-capacitor band-pass delta-sigma modulator.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
22	Won Namgoong	Finite-length synthesis filters for non-uniformly time-interleaved analog-to-digital converter.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
22	Pierluigi Nuzzo, Claudio Nani, Sergio Saponara, Luca Fanucci, Geert Van der Plas	Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications.	DATE	2008	DBLP DOI BibTeX RDF
22	Manar El-Chammas, Boris Murmann	General analysis on the impact of phase-skew in time-interleaved ADCs.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Stefan Mendel, Christian Vogel 0001	On the Compensation of Magnitude Response Mismatches in M-channel Time-interleaved ADCs.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Minho Kwon, Gunhee Han	An I/Q Channel Time-Interleaved Band-Pass Sigma-Delta Modulator for a Low-IF Receiver.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Pieter Harpe, Athon Zanikopoulos, Hans Hegt, Arthur H. M. van Roermund	Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Van Tam Nguyen 0001, Patrick Loumeau, Jean-François Naviner	A CMOS implementation of time-interleaved high-pass Delta Sigma modulator.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Munkyo Seo, Mark J. W. Rodwell, Upamanyu Madhow	Blind correction of gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter: experimental verification.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Pieter Harpe, Athon Zanikopoulos, Arthur H. M. van Roermund	Digital self-correction of time-interleaved ADCs.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
22	Francisco Colodro Ruiz, Antonio Jesús Torralba Silgado, Marta Laguna Garcia	Time-interleaved multirate sigma-delta modulators.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
22	Christian Vogel 0001, Dieter Draxelmayr, Gernot Kubin	Spectral shaping of timing mismatches in time-interleaved analog-to-digital converters.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
22	Echere Iroaga, Boris Murmann, L. Y. Nathawad	A background correction technique for timing errors in time-interleaved analog-to-digital converters.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
22	Christian Vogel 0001, Gernot Kubin	Analysis and compensation of nonlinearity mismatches in time-interleaved ADC arrays.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
22	Kye-Shin Lee, Yunyoung Choi, Franco Maloberti	Domino free 4-path time-interleaved second order sigma-delta modulator.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
22	Väinö Hakkarainen, Lauri Sumanen, Mikko Aho, Mikko Waltari, Kari Halonen	A self-calibration technique for time-interleaved pipeline ADCs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
22	Seng-Pan U., Rui Paulo Martins, José E. Franca	Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
22	Baiying Yu, William C. Black Jr.	Error analysis for time-interleaved analog channels.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
22	Huawen Jin, Edward K. F. Lee	A digital technique for reducing clock jitter effects in time-interleaved A/D converter.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
17	Daniel Widmann, Markus Grözing, Manfred Berroth	Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
16	Jafar Talebzadeh, Mohammad Reza Hassanzadeh, Mohammad Yavari, Omid Shoaei	A 10-bit 150-MS/s, parallel pipeline A/D converter in 0.6-µm CMOS.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
15	Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee	A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
15	Xiangyu Peng, Zixiang Zheng, Yue Zhang, Wei Wang 0187	A Real-Time Calibration Method for Time-Interleaved Analog-to-Digital Convert System in Wideband Digital Radar.	IEEE Trans. Instrum. Meas.	2024	DBLP DOI BibTeX RDF
15	Amy Whitcombe, Somnath Kundu, Hariprasad Chandrakumar, Abhishek Agrawal, Thomas William Brown, Steven Callender, Brent R. Carlton, Stefano Pellerano	22.3 A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking.	ISSCC	2024	DBLP DOI BibTeX RDF
15	Hongzhi Zhao, Minglei Zhang, Yan Zhu 0001, Rui Paulo Martins, Chi-Hang Chan	A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
15	Yue Hu, Yuekai Liu, Xinyu Qin, Yan Liu 0016, Mingqiang Guo, Sai-Weng Sin, Guoxing Wang, Yong Lian 0001, Liang Qi	A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
15	Dengquan Li, Xin Zhao, Yi Shen 0007, Shubin Liu, Zhangming Zhu	A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
15	Chung-Ching Lin, Qiuyan Xu, Huan Hu, Subhanshu Gupta	Design Considerations of Time-Interleaved Discrete-Time Beamformers Toward Wideband Communications.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
15	Jiangbo Wei, Chenghao Zhang, Xinyu Wang, Yuan Chang, Maliang Liu	A Reconfigurable 8-to-10-bit 20-to-5-GS/s time-interleaved time-domain ADC.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
15	Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee	A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
15	Seung Hun Choi, Jeongmin Kim, Jaewoong Ahn, Junyeol An, Jiwoong Kim, Ohjo Kwon, Ki-Duk Kim, Hyung-Min Lee	An Area and Power Efficient Fully Nonlinear 10-bit Column Driver with Time-Shared Multi-Gamma-Slope DAC and Time-Interleaved Sampling Buffer for Mobile AMOLEDs.	A-SSCC	2023	DBLP DOI BibTeX RDF
15	Min Hu, Pengxing Yi, Biting Lei, Wentao Lin	Time Skew Calibration for Time-Interleaved Analog-to-Digital Converters.	APCCAS	2022	DBLP DOI BibTeX RDF
15	Alok Baluni, Shanthi Pavan	Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
15	Deeksha Verma, Behnam Samadpoor Rikan, Khuram Shehzad, Sung Jin Kim, Danial Khan, Venkatesh Kommangunta, Syed Adil Ali Shah, YoungGun Pu, Sang-Sun Yoo, Keum-Cheol Hwang, Youngoo Yang, Kang-Yoon Lee	A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration.	IEEE Access	2021	DBLP DOI BibTeX RDF
15	Min-Kyun Chae, Hye-Jung Kwon, Seung-Jun Bae, Nam-Jong Kim, Hong-June Park	A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
15	Minglei Zhang, Yan Zhu 0001, Chi-Hang Chan, Rui Paulo Martins	A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
15	Ning Ding, Yusong Mu, Yuping Guo, Teng Chen, Yuchun Chang	A 6.4-GS/s 10-b Time-Interleaved SAR ADC with Time-Skew Immune Sampling Network in 28-nm CMOS.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
15	Maowei Yin, Zhongfu Ye	First Order Statistic Based Fast Blind Calibration of Time Skews for Time-Interleaved ADCs.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
15	Armia Salib, Mark F. Flanagan, Barry Cardiff	Time-Skew Estimation for Random Sampling Sequence Time-Interleaved ADCs.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
15	Alok Baluni, Shanthi Pavan	A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and > 00 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC.	CICC	2020	DBLP DOI BibTeX RDF
15	Yongtao Qiu, Jie Zhou, Youjiang Liu, Guifu Zhang, Yinong Liu	Novel adaptive blind calibration technique of time-skew mismatches for any channel time-interleaved analogue-to-digital converters.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
15	Armia Salib, Mark F. Flanagan, Barry Cardiff	A High-Precision Time Skew Estimation and Correction Technique for Time-Interleaved ADCs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
15	Xiao Wang 0021, Fule Li, Wen Jia, Zhihua Wang 0001	A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
15	Chan-Hsiang Weng, Tzu-An Wei, Hung-Yi Hsieh, Su-Hao Wu, Ting-Yang Wang	A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
15	Ankesh Jain, Shanthi Pavan	Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
15	Wenning Jiang, Yan Zhu 0001, Chi-Hang Chan, Boris Murmann, Seng-Pan U, Rui Paulo Martins	A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler.	A-SSCC	2018	DBLP DOI BibTeX RDF
15	Benwei Xu, Yuan Zhou 0011, Yun Chiu	A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
15	Armia Salib, Barry Cardiff, Mark F. Flanagan	A low-complexity correlation-based time skew estimation technique for time-interleaved SAR ADCs.	ISCAS	2017	DBLP DOI BibTeX RDF
15	Yongzhen Chen, Yimin Wu, Fubiao Cao, Fan Ye 0001, Junyan Ren	A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs.	ASICON	2017	DBLP DOI BibTeX RDF
15	Lei Qiu 0002, Yuanjin Zheng, Liter Siek	Multichannel Time Skew Calibration for Time-Interleaved ADCs Using Clock Signal.	Circuits Syst. Signal Process.	2016	DBLP DOI BibTeX RDF
15	Jean-Adrien Vernhes, Marie Chabert, Bernard Lacaze, Guy Lesthievent, Roland Baudin, Marie-Laure Boucheret	Blind estimation of unknown time delay in periodic non-uniform sampling: Application to desynchronized time interleaved-ADCs.	ICASSP	2016	DBLP DOI BibTeX RDF
15	Lei Qiu 0002, Kai Tang 0002, Yuanjin Zheng, Liter Siek	A digital time skew calibration technique for time-interleaved ADCs.	ISCAS	2015	DBLP DOI BibTeX RDF
15	Vanessa Hung-Chu Chen, Lawrence T. Pileggi	A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
15	Mohammad Niaboli-Guilani, Amir Bazrafshan-Jorshari, Reza Meshkin	A Low-Power Digital Calibration of Sampling Time Mismatches in Time-Interleaved a/d Converters.	J. Circuits Syst. Comput.	2014	DBLP DOI BibTeX RDF
15	Benjamin K. Ng, Chan-Tong Lam	Single-carrier time-interleaved space-time code for frequency-selective fading channels.	SAM	2014	DBLP DOI BibTeX RDF
15	Vanessa Hung-Chu Chen, Lawrence T. Pileggi	22.2 A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI.	ISSCC	2014	DBLP DOI BibTeX RDF
15	Lei Qiu 0002, Yuanjin Zheng, Di Zhu 0003, Liter Siek	A statistic based time skew calibration method for time-interleaved ADCs.	ISCAS	2014	DBLP DOI BibTeX RDF
15	Bei Yu, Chixiao Chen, Fan Ye 0001, Junyan Ren	A mixed sample-time error calibration technique in time-interleaved ADCs.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
15	Anu Kalidas Muralidharan Pillai, Håkan Johansson	Low-complexity two-rate based multivariate impulse response reconstructor for time-skew error correction in m-channel time-interleaved ADCs.	ISCAS	2013	DBLP DOI BibTeX RDF
15	Anu Kalidas Muralidharan Pillai, Håkan Johansson	Time-skew error correction in two-channel time-interleaved ADCs based on a two-rate approach and polynomial impulse responses.	MWSCAS	2012	DBLP DOI BibTeX RDF
15	Raouf Khalil, Marie-Minerve Louërat, Roger Petigny, Hugo Gicquel	Background time skew calibration for time-interleaved ADC using phase detection method.	NEWCAS	2012	DBLP DOI BibTeX RDF
15	Benjamín T. Reyes, Venu Gopinathan, Pablo Sergio Mandolesi, Mario R. Hueda	Joint sampling-time error and channel skew calibration of time-interleaved ADC in multichannel fiber optic receivers.	ISCAS	2012	DBLP DOI BibTeX RDF
15	Edinei Santin, Luís Bica Oliveira, João Goes	Fast and accurate estimation of gain and sample-time mismatches in time-interleaved ADCs using on-chip oscillators.	ISCAS	2012	DBLP DOI BibTeX RDF
15	Yiwen Zhang, Xiaoshi Zhu, Chixiao Chen, Fan Ye 0001, Junyan Ren	A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation.	APCCAS	2012	DBLP DOI BibTeX RDF
15	Bei Yu, Chixiao Chen, Yu Zhu, Peng Zhang, Yiwen Zhang, Xiaoshi Zhu, Fan Ye 0001, Junyan Ren	A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation.	A-SSCC	2011	DBLP DOI BibTeX RDF
15	Shahzad Saleem, Christian Vogel 0001	Adaptive compensation of frequency response mismatches in high-resolution time-interleaved ADCs using a low-resolution ADC and a time-varying filter.	ISCAS	2010	DBLP DOI BibTeX RDF
15	Håkan Johansson	A Polynomial-Based Time-Varying Filter Structure for the Compensation of Frequency-Response Mismatch Errors in Time-Interleaved ADCs.	IEEE J. Sel. Top. Signal Process.	2009	DBLP DOI BibTeX RDF
15	Afshin Haftbaradaran, Kenneth W. Martin	A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
15	Young-Gyu Yoon, Jaewook Kim, Tae-Kwang Jang, SeongHwan Cho	A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators.	IEEE Trans. Circuits Syst. I Regul. Pap.	2008	DBLP DOI BibTeX RDF
15	Afshin Haftbaradaran, Kenneth W. Martin	A Sample-Time Error Compensation Technique for Time-Interleaved ADC Systems.	CICC	2007	DBLP DOI BibTeX RDF
15	Trevor C. Caldwell, David A. Johns	A time-interleaved continuous-time ΔΣ modulator with 20-MHz signal bandwidth.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
15	Shafiq M. Jamal, Daihong Fu, Mahendra P. Singh, Paul J. Hurst, Stephen H. Lewis	Correction to "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter".	IEEE Trans. Circuits Syst. I Regul. Pap.	2005	DBLP DOI BibTeX RDF
15	Trevor C. Caldwell, David A. Johns	A time-interleaved continuous-time ΔΣ modulator with 20MHz signal bandwidth.	ESSCIRC	2005	DBLP DOI BibTeX RDF
15	Shafiq M. Jamal, Daihong Fu, Mahendra P. Singh, Paul J. Hurst, Stephen H. Lewis	Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter.	IEEE Trans. Circuits Syst. I Regul. Pap.	2004	DBLP DOI BibTeX RDF
15	Jonas Elbornsson, Fredrik Gustafsson, Jan-Erik Eklund	Amplitude and gain error influence on time error estimation algorithm for time interleaved A/D converter system.	ICASSP	2002	DBLP DOI BibTeX RDF
13	Daniel Widmann, Tobias Tannert, Xuan-Quang Du, Thomas Veigel, Markus Grözing, Manfred Berroth	A Time-Interleaved Digital-to-Analog Converter up to 118 GS/s With Integrated Analog Multiplexer in 28-nm FD-SOI CMOS Technology.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
13	Hamid Karrari, Pietro Andreani, Siyu Tan	A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS.	IEEE Access	2024	DBLP DOI BibTeX RDF
13	Hamidreza Mafi, Naim Ben-Hamida, Sadok Aouini, Yvon Savaria	Digital Compensation of Timing Skew Mismatches in Time-Interleaved ADCs by Source Separation.	IEEE Trans. Instrum. Meas.	2024	DBLP DOI BibTeX RDF
13	Dengquan Li, Longsheng Wang, Yi Shen 0007, Shubin Liu, Zhangming Zhu	A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm.	IEEE Trans. Instrum. Meas.	2024	DBLP DOI BibTeX RDF
13	Yuan Li, Zhihong Lin, Wenbo Dong, Ziwen Hu, Chill Wang, Shenglong Zhuo, Yifan Wu, Hengwei Yu, Patrick Yin Chiang	An Angle-Insensitive 138-dB Dynamic Range Light Sensor With 4 Time-Interleaved Channels 32-ppm/°C Temperature-Independent Flicker Detection.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
13	Jiawei Wang, Zhao Gao, Xu Cheng 0002, Jue Wang, Zhen Li, Jun Han 0003, Xiaoyang Zeng	A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
13	Yen-Po Lin, Pen-Jui Peng, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh	7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Ewout Martens, Adam Cooman, Pratap Tumkur Renukaswamy, Shun Nagata, Sehoon Park, Jorge-Luis Lagos 0001, Nereo Markulic, Jan Craninckx	22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC.	ISSCC	2024	DBLP DOI BibTeX RDF