| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Run Yan, Yin Su, Hui Guo 0004, Yashuai Lü, Jin Wang, Nong Xiao, Li Shen 0007, Yongwen Wang, Libo Huang |
MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray Tracing.  |
IEEE Trans. Very Large Scale Integr. Syst.  |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang |
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Luo, Bochang Li, Lidan Wang 0001, Jinpei Tan, Shukai Duan, Chunxiang Zhu |
Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for In-Memory Computing. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Changmin Song, Hoyong Jung, KyoungSeop Chang, Kwanglae Cho, Seungyong Yoon, Young-Chan Jang |
A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Lucas Compassi Severo, Tailize C. De-Oliveira, Paulo César Comassetto de Aguirre, Wilhelmus A. M. Van Noije, Alessandro Gonçalves Girardi |
Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass Filters. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhuojun Chen, Wenhao Yang, Jinghang Chen, Zujun Wang, Ding Ding |
Improving Radiation Reliability of SRAM-Based Physical Unclonable Function With Self-Healing and Pre-Irradiation Masking Techniques. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Erfan Bank Tavakoli, Michael Riera, Masudul Hassan Quraishi, Fengbo Ren |
FSpGEMM: A Framework for Accelerating Sparse General Matrix-Matrix Multiplication Using Gustavson's Algorithm on FPGAs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Eduardo Ortega, Jonti Talukdar, Woohyun Paik, Tyler K. Bletsch, Krishnendu Chakrabarty |
Rowhammer Vulnerability of DRAMs in 3-D Integration. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Christopher Vega, Patanjali SLPSK, Swarup Bhunia |
IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering Attacks. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhaojun Lu, Xueyan Wang, Md Tanvir Arafin, Haoxiang Yang, Zhenglin Liu, Jiliang Zhang 0002, Gang Qu 0001 |
An RRAM-Based Computing-in-Memory Architecture and Its Application in Accelerating Transformer Inference. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi |
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongqiang Zhang 0006, Jiao Qin, Jie Han 0001, Guangjun Xie |
Design of a Stochastic Computing Architecture for the Phansalkar Algorithm. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Testability Evaluation for Local Design Modifications. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Jari Nurmi, Snorre Aunet, Alireza Saberkari |
Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2022. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Basant Kumar Mohanty |
Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Isa H. Altoobaji, Ahmad Hassan, Mohamed Ali 0001, Yves Audet, Ahmed Lakhssassi |
A Low-Power 0.68-Gbps Data Communication System for Capacitive Digital Isolator With 1.9-ns Propagation Delay. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Jun Liu 0070, Songren Cheng, Tian Chen, Xi Wu 0003, Huaguo Liang |
A Self-Biased Current Reference Source-Based Pre-Bond TSV Test Solution. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Rakesh Varma Rena, Raviteja Kammari, Vijay Shankar Pasupureddi |
A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Zhang, Mark M. Tehranipoor, Farimah Farahmandi |
TrustGuard: Standalone FPGA-Based Security Monitoring Through Power Side-Channel. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Bo Zhang 0098, Zeming Cheng, Massoud Pedram |
Design of a High-Performance Iterative Barrett Modular Multiplier for Crypto Systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Dengquan Li, Tian Feng, Jiale Ding, Yi Shen 0007, Shubin Liu, Zhangming Zhu |
A Wideband Input Buffer Based on Cascade Complementary Source Follower. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu |
A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiao Hu 0007, Zhihao Li, Zhongfeng Wang 0001, Xianhui Lu |
ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Johnson Loh, Tobias Gemmeke |
Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Xingyu Wang, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara |
A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Tianyou Bao, Pengzhou He, Shi Bai 0001, Jiafeng Xie |
TINA: TMVP-Initiated Novel Accelerator for Lightweight Ring-LWE-Based PQC. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Junjie An, Zhidao Zhou, Linfang Wang, Wang Ye, Weizeng Li, Hanghang Gao, Zhi Li, Jinghui Tian, Yan Wang, Hongyang Hu, Jinshan Yue, Lingyan Fan, Shibing Long, Qi Liu 0010, Chunmeng Dou |
Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Christian Lanius, Tobias Gemmeke |
Fully Digital, Standard-Cell-Based Multifunction Compute-in-Memory Arrays for Genome Sequencing. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Likai Pei, Xiaodong Meng, Xing Li |
A Novel Digital-Controlled Current-Mode Single-Inductor-Multiple-Output Buck Converter With Individual Output Overload Protection. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Zhang, Md Latifur Rahman, Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi |
SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Md. Moshiur Rahman 0001, Swarup Bhunia |
Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Chenjia Xie, Zhuang Shao, Zhichao Chen, Yuan Du, Li Du |
An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Shiwei Liu, Chen Mu, Hao Jiang, Yunzhengmao Wang, Jinshan Zhang 0006, Feng Lin, Keji Zhou, Qi Liu 0010, Chixiao Chen |
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, Sung Kyu Lim |
A PPA Study for Heterogeneous 3-D IC Options: Monolithic, Hybrid Bonding, and Microbumping. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Chen Yang 0005, Yishuo Meng, Jiawei Xi, Siwei Xiang, Jianfei Wang, Kuizhi Mei |
WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Zheng 0001, Mingjun Cheng, Jiasong Chen, Huaien Gao, Xiaoming Xiong, Shuting Cai |
BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Vijaypal Singh Rathor, Munesh Singh, Kshira Sagar Sahoo, Saraju P. Mohanty |
GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar |
A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Daijoon Hyun, Younggwang Jung, Youngsoo Shin |
Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Shourya Gupta, Shuo Li 0008, Benton H. Calhoun |
Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Liang Chang 0002, Xin Zhao, Ting Yue, Xi Yang, Chenglong Li, Shuisheng Lin, Jun Zhou 0017 |
IPOCIM: Artificial Intelligent Architecture Design Space Exploration With Scalable Ping-Pong Computing-in-Memory Macro. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Yifei Zheng, Boyu Li, Qianheng Dong, Yutao Ying, Deyuan Song, Jing Zhu 0006, Weifeng Sun, Qinsong Qian, Long Zhang, Sheng Li, Denggui Wang, Jianjun Zhou |
A 200-V Half-Bridge Monolithic GaN Power IC With High-Speed Level Shifter and dVS/dt Noise Immunity Enhancement Structure. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Si-Huang Liu, Chia-Yi Kuo, Yannan Mo, Tao Su |
An Area-Efficient, Conflict-Free, and Configurable Architecture for Accelerating NTT/INTT. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Siavash Mowlavi, Stavros Giannakopoulos, Alexander Grabowski, Lars Svensson |
A Review of IC Drivers for VCSELs in Datacom Applications. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoxiao Zheng, Mao Ye 0007, Zhiwei Li, Yao Li, Qiuwei Wang, Yiqiang Zhao |
A CMOS AFE Array With DC Input Current Cancellation for FMCW LiDAR. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao 0007, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu |
Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao 0007, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu |
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuan Dai, Jingyuan Li, Qilong Zhu, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang |
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Renas Ercan, Yunjia Xia, Yunyi Zhao, Rui C. V. Loureiro, Shufan Yang, Hubin Zhao |
An Ultralow-Power Real-Time Machine Learning Based fNIRS Motion Artifacts Detection. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsi-Kai Peng, Shen-Iuan Liu |
A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Manuel Brosch, Matthias Probst, Matthias Glaser, Georg Sigl |
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahsa Zareie, Kamal El-Sankary, Ezz I. El-Masry, Ximing Fu |
An Open-Loop VCO-ADC Based on a Linearized Current Control Technique. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Jingqi Zhang, Zhiming Chen 0001, Mingzhi Ma, Rongkun Jiang, Hongshuo Li, Weijiang Wang |
High-Performance ECC Scalar Multiplication Architecture Based on Comb Method and Low-Latency Window Recoding Algorithm. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho |
Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Fredrik Feyling, Hampus Malmberg, Carsten Wulff, Hans-Andrea Loeliger, Trond Ytterdal |
Design and Analysis of the Leapfrog Control-Bounded A/D Converter. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Ke Chang, Qian Xing, Guoliang Jia, Yang Pu, Yan Wang, Yuxin Wang, Yanlong Zhang, Guohe Zhang |
An Improved DEM for Multibit DT ΣΔMs Based on Poles Splitting Technique and Segmented VQ. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Kasra Ahmadi, Saeed Aghapour, Mehran Mozaffari Kermani, Reza Azarderakhsh |
Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Thai-Ha Tran, Duc-Thuan Dam, Ba-Anh Dao, Van-Phuc Hoang, Cong-Kha Pham, Trong-Thuc Hoang |
Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Charalampos Eleftheriadis, Georgios Chatzitsompanis, Georgios Karakonstantis |
Enabling Voltage Over-Scaling in Multiplierless DSP Architectures via Algorithm-Hardware Co-Design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Bofan Chen, Zhiqun Li, Wei Shi, Yan Yao, Zhi-Ying Xia, Bing-Yan Qiu, Hao Ji |
A 6-18-GHz 6-bit Full-360° Vector-Sum Phase Shifter With Low Error in 40-nm CMOS. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Sunwoong Kim, Cameron James Norris, James I. Oelund, Rob A. Rutenbar |
Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Hao Lan, Shen-Iuan Liu |
A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Agnimesh Ghosh, Andrei Spelman, Tze Hin Cheung, Dhanashree Boopathy, Kari Stadius, Manil Dev Gomony, Mikko Valkama, Jussi Ryynänen, Marko Kosunen, Vishnu Unnikrishnan |
Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdulaziz Alshaya, Sudhakar Pamarti, Christos Papavassiliou |
FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Sureum Choi, Daejin Han, Chanyeong Choi, Yeongkyo Seo |
Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Ana Mitrovic, Eby G. Friedman |
Thermal Exploration of RSFQ Integrated Circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Haoming Zhang, Shuowei Li, Tetsuya Iizuka |
A Single Ring-Oscillator-Based Test Structure for Timing Characterization of Dynamic Circuit. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Pengcheng Huang, Yaohua Wang, Zhenyu Zhao, Daheng Yue |
CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Na Bai, Xin Xiao, Yaohua Xu, Yi Wang, Liang Wang, Xinjie Zhou |
Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia-Zhao Lin, Po-Ta Chen, Hung-Yuan Chin, Pei-Yun Tsai, Sz-Yuan Lee |
Design and Implementation of a Real-Time Imaging Processor for Spaceborne Synthetic Aperture Radar With Configurability. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Bin Li 0023, Yunfei Yan, Yuanxin Wei, Heru Han |
Scalable and Parallel Optimization of the Number Theoretic Transform Based on FPGA. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Joseph Franklin Clements, Yingjie Lao |
Reliable Hardware Watermarks for Deep Learning Systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongge Li, Yuhao Chen |
Hybrid Stochastic Number and Its Neural Network Computation. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Dongdong Xu 0002, Xiang Wang 0006, Qiang Hao, Jiqing Wang, Shuangjie Cui, Bo Liu |
A High-Performance Transparent Memory Data Encryption and Authentication Scheme Based on Ascon Cipher. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao-Yu Chen, Yan-Siou Dai, Hao-Chiao Hong |
A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Zuzana Jelcicová, Evangelia Kasapaki, Oskar Andersson, Jens Sparsø |
PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Md Toufiq Hasan Anik, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi |
On the Resiliency of Protected Masked S-Boxes Against Template Attack in the Presence of Temperature and Aging Misalignments. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Yiting Liu, Hai Zhou 0001, Jia Wang 0003, Fan Yang 0001, Xuan Zeng 0001, Li Shang |
Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Aibin Yan, Litao Wang, Jie Cui 0004, Zhengfeng Huang, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen |
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Kai Huang, Saul Rodriguez 0001 |
Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeju Li, Qinfan Wang, Zihan Zou, Qiao Shen 0001, Na Xie, Hao Cai, Hao Zhang, Bo Liu 0019 |
Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Chenghan Wang, Qinzhi Xu, Chuanjun Nie, He Cao, Jianyun Liu, Daoqing Zhang, Zhiqiang Li |
A Multiscale Anisotropic Thermal Model of Chiplet Heterogeneous Integration System. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Musha Ji'e, Hongxin Peng, Shukai Duan, Lidan Wang 0001, Fengqing Zhang, Dengwei Yan |
Design and FPGA Implementation of Grid-Scroll Hamiltonian Conservative Chaotic Flows With a Line Equilibrium. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf |
HW-FUTEX: Hardware-Assisted Futex Syscall. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | YaJuan Hui, Qingzhen Li, Leimin Wang, Cheng Liu 0008, Deming Zhang, Xiangshui Miao |
In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Sai Pentapati, Sung Kyu Lim |
Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Rui Xiao, Yewei Zhang, Bo Wang 0020, Yanfeng Xu, Jicong Fan, Haibin Shen, Kejie Huang |
A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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| 1 | Woojung Kim, Woojin Hong, Jae Joon Kim, Myunghee Lee |
A 5.4-Gb/s, 0.57-pJ/bit, Single-Loop Referenceless CDR With an Unlimited Bilateral Frequency Detection Scheme. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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| 1 | Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh |
Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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| 1 | Nurzhan Zhuldassov, Rassul Bairamkulov, Eby G. Friedman |
Thermal Optimization of Hybrid Cryogenic Computing Systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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| 1 | Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan 0001, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri |
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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| 1 | Wenzhe Zhao, Guoming Yang, Tian Xia 0008, Fei Chen, Nanning Zheng 0001, Pengju Ren |
HIPU: A Hybrid Intelligent Processing Unit With Fine-Grained ISA for Real-Time Deep Neural Network Inference Applications. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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| 1 | Yongqiang Zhang 0006, Siting Liu 0001, Jie Han 0001, Zhendong Lin, Shaowei Wang, Xin Cheng 0001, Guangjun Xie |
An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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| 1 | Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer |
A New Static Compaction of Deterministic Test Sets. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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| 1 | Kwangmin Kim, Hyoseok Song, Byeongcheol Lee, Byungsub Kim |
A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits: A High-Speed FFE SST Transmitter Example. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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| 1 | Malek Souilem, Nawel Zgolli, Telmo Reis Cunha, Wael Dghais, Belgacem Hamdi |
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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| 1 | Wenbo Guan, Xiaoyan Tang, Hongliang Lu, Yuming Zhang, Yimen Zhang |
ATT-TA: A Cooperative Multiagent Deep Reinforcement Learning Approach for TSV Assignment in 3-D ICs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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| 1 | Ayesha Siddique, Khaza Anuarul Hoque |
Exposing Reliability Degradation and Mitigation in Approximate DNNs Under Permanent Faults. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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| 1 | Jianjun Luo 0003, Hailuan Liu, Ying He, César Vargas Rosales, Lingyan Fan |
High-Density NVMe SSD With DRAM-Less eRAID Architecture. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
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