Search results for "ADC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
82	Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A low power, variable resolution two-step flash ADC.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	two-step flash ADC, variable resolution, low power
74	Jonas Elbornsson, Fredrik Gustafsson, Jan-Erik Eklund	Blind equalization of time errors in a time-interleaved ADC system.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
73	Peng Juan, Ma Hong, Tian Chen	Modeling of ADC Nonlinearity by Time-Delay-Based Power Series.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	ADC nonlinearity, Time-delay-Based modeling, power series
73	Heinz Mattes, Stéphane Kirmser, Sebastian Sattler	Next Generation ADC Massive Parallel Testing with Real Time Parameter Evaluation.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	delta-sigma-converter, ??-modulation, FPGA, mixed-signal test, ADC test
73	Yih-Chyun Jenq	Digital Signal Processing with Interleaved ADC Systems.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	interleaved ADC, DSP algorithm, aliasing, filter banks, A/D converter
73	Chia-Nan Yeh, Yen-Tai Lai	A novel flash analog-to-digital converter.	ISCAS	2008	DBLP DOI BibTeX RDF
72	Jincheol Yoo, Daegyu Lee, Kyusun Choi, Jongsoo Kim	A power and resolution adaptive flash analog-to-digital converter.	ISLPED	2002	DBLP DOI BibTeX RDF	TIQ comparator, flash ADC, inverter quantization, adaptive, threshold, analog-to-digital converter
65	Ji Hwan (Paul) Chun, Hak-soo Yu, Jacob A. Abraham	An efficient linearity test for on-chip high speed ADC and DAC using loop-back.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	BIST, linearity, ADC, mixed signal test, DAC
65	Weng-leng Mok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins	A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC.	ISCAS	2007	DBLP DOI BibTeX RDF
65	Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran	ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective.	VLSI Design	2006	DBLP DOI BibTeX RDF
65	Degang Chen 0001, Zhongjun Yu, Randall L. Geiger	An adaptive, truly background calibration method for high speed pipeline ADC design.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
65	Zhongjun Yu, Degang Chen 0001, Randall L. Geiger	Accurate testing of ADC's spectral performance using imprecise sinusoidal excitations.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
64	W. D. Bartlett	Determination of coherence errors in ADC spectral domain testing.	VTS	1997	DBLP DOI BibTeX RDF	coherence errors, ADC spectral domain testing, clock frequencies input, spectral domain based test, effective number of bits test, 10 MHz, 10 bit, analog-to-digital converter, analogue-digital conversion
64	Bing Ma, Charles R. Meyer, Martin D. Pickles, Thomas L. Chenevert, Peyton H. Bland, Craig J. Galbán, Alnawaz Rehemtulla, Lindsay W. Turnbull, Brian D. Ross	Voxel-by-Voxel Functional Diffusion Mapping for Early Evaluation of Breast Cancer Treatment.	IPMI	2009	DBLP DOI BibTeX RDF
63	Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi	CMOS flash analog-to-digital converter for high speed and low voltage applications.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	TIQ comparator, fat tree encoder, flash ADC, analog-to-digital converter, low voltage, high speed
63	Yuan-Tzu Ting, Li Wei Chao, Wei Chung Chao	A Practical Implementation Of Dynamic Testing Of An Ad Converter.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	AD converter, effective bits, differential nonlinearity, integral nonlinearity, mixed frequency estimation algorithm, weighted least square method, spectral average method, frequency domain estimation, logical analyzer, instrument controller, high speed data acquisition device, GPIB, Datel ADC-HS12B, programmable signal generator, algorithm, software, automatic testing, histogram, PC, signal to noise ratio, analogue-digital conversion, dynamic testing
56	R. de Vries, Augustus J. E. M. Janssen	Decreasing the Sensitivity of ADC Test Parameters by Means of Wobbling.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	wobble, ADC, dither, spectral test
55	Xiaodong Zhang 0008, Magdy A. Bayoumi	A Low Power 4-bit Interleaved Burst Sampling ADC for Sub-GHz Impulse UWB Radio.	ISCAS	2007	DBLP DOI BibTeX RDF
55	Tae-Hwan Oh, Sang-Min Yoo, Kyoung-Ho Moon, Jae-Whui Kim	A 3.0 V 72mW 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC in 0.54 mm2.	ISCAS	2006	DBLP DOI BibTeX RDF
55	Young-Jae Cho, Kyung-Hoon Lee, Hee-Cheol Choi, Young-Ju Kim, Kyoung-Jun Moon, Seung-Hoon Lee, Seok-Bong Hyun, Seong-Su Park	A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems.	APCCAS	2006	DBLP DOI BibTeX RDF
55	Naoki Kurosawa, Haruo Kobayashi 0001, Kensuke Kobayashi	Channel linearity mismatch effects in time-interleaved ADC systems.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
55	Eric Fogleman, Ian Galton, Henrik Jensen 0001	An area-efficient differential input ADC with digital common mode rejection.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
55	Frank Sill, Davies W. de Lima Monteiro	Pipelined successive approximation conversion (PSAC) with error correction for a CMOS ophthalmic sensor.	SBCCI	2009	DBLP DOI BibTeX RDF	pipelined SAC, error correction, ADC
55	Brendan Mullane, Ciaran MacNamee, Vincent O'Brien, Thomas Fleischmann	An on-chip solution for static ADC test and measurement.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	ADC-BiST, code histogram, linearity measurements, test, system-on-chip, analog to digital converter
55	Jaeyong Lee, Sungil Cho, Kwangsub Yoon	12bits 40mhz pipelined ADC with duty-correction circuit.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	adc(analog-to-digital converter), pipeline, cmos, dll
55	DongHyun Ko, Ji-Hoon Jung, YoungGun Pu, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam	A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 µm CMOS Process.	DELTA	2008	DBLP DOI BibTeX RDF	ADC(Analog-to-Digital Converter), DAC (Digital-to-Analog Converter), Sigma-Delta Modulator
55	Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel	A Level-Crossing Flash Asynchronous Analog-to-Digital Converter.	ASYNC	2006	DBLP DOI BibTeX RDF
55	Le Jin, Degang Chen 0001, Randall L. Geiger	A digital self-calibration algorithm for ADCs based on histogram test using low-linearity input signals.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
55	Hai Phuong Le, Aladin Zayegh, Jugdutt Singh	Noise Analysis of a Reduced Complexity Pipeline Analog-to-Digital Converter.	DELTA	2004	DBLP DOI BibTeX RDF
55	Maria del Mar Hershenson	Design of pipeline analog-to-digital converters via geometric programming.	ICCAD	2002	DBLP DOI BibTeX RDF
55	Pierrick Gachet, Christophe Mauras, Patrice Quinton, Yannick Saouter	Alpha du centaur: a prototype environment for the design of parallel regular alorithms.	ICS	1989	DBLP DOI BibTeX RDF
54	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
54	Parastoo Nikaeen, Boris Murmann, Robert W. Dutton	Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs.	ISQED	2008	DBLP DOI BibTeX RDF	flash ADC, comparator, SNR, substrate noise
46	Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas	Design of a Low Power, Variable-Resolution Flash ADC.	VLSI Design	2009	DBLP DOI BibTeX RDF
46	Hooman Farkhani, Mohammad Maymandi-Nejad, Manoj Sachdev	A fully digital ADC using a new delay element with enhanced linearity.	ISCAS	2008	DBLP DOI BibTeX RDF
46	Zheng Yang 0004, Jan Van der Spiegel	A 10-bit 8.3MS/s switched-current successive approximation ADC for column-parallel imagers.	ISCAS	2008	DBLP DOI BibTeX RDF
46	Liang Rong, Martin Gustafsson 0002, Ana Rusu, Mohammed Ismail 0001	Systematic Design of a Flash ADC for UWB Applications.	ISQED	2007	DBLP DOI BibTeX RDF
46	Masoud Babaie, Hamid Movahedian, Mehrdad Sharif Bakhtiar	A Novel Method for Systematic Error Prediction of CMOS Folding and Interpolating ADC.	APCCAS	2006	DBLP DOI BibTeX RDF
46	Youngbok Kim, Anuj Agarwal, Sameer R. Sonkusale	Low power current mode ADC for CMOS sensor IC.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
46	Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng	A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
46	Shigeto Tanaka, Yuji Gohda, Yasuhiro Sugimoto	The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADC.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
46	Zhongjun Yu, Degang Chen 0001, Randall L. Geiger, Ioannis Papantonopoulos	Pipeline ADC linearity testing with dramatically reduced data capture time.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
46	Hanqing Xing, Degang Chen 0001, Randall L. Geiger	A two-step DDEM ADC for accurate and cost-effective DAC testing.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
46	Eugenio Culurciello, Andreas G. Andreou	An 8-bit, 1mW successive approximation ADC in SOI CMOS.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
46	B. E. Jonsson, Hannu Tenhunen	A dual 3-V 32-MS/s CMOS switched-current ADC for telecommunication applications.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
46	Aigars Gertners, Valery Zagursky, Dzintra Saldava	Behavior model of mixed ADC systems.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	identification, behavior model, nonlinear system, high-level modeling, mixed system
46	Anand Mohan, Aladin Zayegh, Aleksandar Stojcevski	A High Speed Analog to Digital Converter for Ultra Wide Band Applications.	EUC Workshops	2007	DBLP DOI BibTeX RDF	Flash Topology, UWB, Power Saving, ADC, CMOS Technology
46	Hu Xiao, Ma Hong, Peng Juan, Tian Chen	State-of-the-Art in Volterra Series Modeling for ADC Nonlinearity.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	Volterra series, model, memory, nonlinear, analog to digital converter (ADC)
46	Ricky Yiu-kee Choi, Chi-Ying Tsui	A Low Energy Two-Step Successive Approximation Algorithm for ADC Design.	ISQED	2008	DBLP DOI BibTeX RDF	Successive Approximation Register ADC, Low Power
45	Guillaume Ferré, Maher Jridi, Lilian Bossuet, Bertrand Le Gal, Dominique Dallet	A new orthogonal online digital calibration for time-interleaved analog-to-digital converters.	ISCAS	2008	DBLP DOI BibTeX RDF
45	Fernando Mourão, Leonardo Rocha 0001, Renata Braga Araújo, Thierson Couto, Marcos André Gonçalves, Wagner Meira Jr.	Understanding temporal aspects in document classification.	WSDM	2008	DBLP DOI BibTeX RDF	digital libraries, text classification, temporal analysis
45	Mohammad Taherzadeh-Sani, Anas A. Hamoui	Analysis of dynamic element matching (DEM) in pipelined ADCs.	ISCAS	2006	DBLP DOI BibTeX RDF
45	Kyung-Hoon Lee, Young-Jae Cho, Hee-Cheol Choi, Yong-Hyun Park, Doo-Hwan Sa, Young-Lok Kim, Seung-Hoon Lee	A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter.	APCCAS	2006	DBLP DOI BibTeX RDF
45	Henrik Lundin, Mikael Skoglund, Peter Händel	Optimal index-bit allocation for dynamic post-correction of analog-to-digital converters.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
45	Xin Dai, Degang Chen 0001, Randall L. Geiger	A cost-effective histogram test-based algorithm for digital calibration of high-precision pipelined ADCs.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
45	Shih-Chang Hsia, Wen-Ching Lee	A Very Low-Power Flash A/D Converter Based on Cmos Inverter Circuit.	IWSOC	2005	DBLP DOI BibTeX RDF	CMOS inverter, flash, A/D converter
45	Yunmei Chen, Weihong Guo 0002, Qingguo Zeng, Xiaolu Yan, Feng Huang 0001, Hao Zhang 0030, Guojun He, Baba C. Vemuri, Yijun Liu	Estimation, Smoothing, and Characterization of Apparent Diffusion Coefficient Profiles from High Angular Resolution DWI.	CVPR (1)	2004	DBLP DOI BibTeX RDF
45	Eduardo J. Peralías, Adoración Rueda, José Luis Huertas	New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	mixed-signal IC test, testable ADC, BIST, design for test, pipelined analog to digital converters
44	Daniela De Venuto, Leonardo Reyneri	Fast PWM-Based Test for High Resolution SigmaDelta ADCs.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Test of high resolution ADC, Sigma-Delta ADC, PWM test signal
38	John A. McNeill, Sanjeev Goluguri, Abhilash Nair	"Split-ADC" Digital Background Correction of Open-Loop Residue Amplifier Nonlinearity Errors in a 14b Pipeline ADC.	ISCAS	2007	DBLP DOI BibTeX RDF
37	Umar H. Rizvi, Gerard J. M. Janssen, Jos H. Weber	BER analysis of single-carrier MPAM in the presence of ADC quantization noise.	PIMRC	2008	DBLP DOI BibTeX RDF
37	Diego Pedro Morales, Antonio García 0001, Alberto J. Palma, Miguel A. Carvajal, Encarnación Castillo, Luis F. Capitán-Vallvey	Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration.	FPL	2008	DBLP DOI BibTeX RDF
37	Hee-Cheol Choi, Young-Ju Kim, Se-Won Lee, Jae-Yeol Han, Oh-Bong Kwon, Younglok Kim, Seung-Hoon Lee	A 52mW 0.56mm2 1.2V 12b 120MS/s SHA-Free dual-channel Nyquist ADC based on mid-code calibration.	ISCAS	2008	DBLP DOI BibTeX RDF
37	Nitz Saputra, Michiel A. P. Pertijs, Kofi A. A. Makinwa, Johan H. Huijsing	Sigma delta ADC with a dynamic reference for accurate temperature and voltage sensing.	ISCAS	2008	DBLP DOI BibTeX RDF
37	He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier.	ISCAS	2008	DBLP DOI BibTeX RDF
37	Santiago Rodriguez-Parera, André Bourdoux, François Horlin, Jordi Carrabina, Liesbet Van der Perre	Front-End ADC Requirements for Uniform Bandpass Sampling in SDR.	VTC Spring	2007	DBLP DOI BibTeX RDF
37	Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud	A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
37	Athon Zanikopoulos, Pieter Harpe, Hans Hegt, Arthur H. M. van Roermund	Design of the Basic Building Block of a High-Speed Flexible and Modular Pipelined ADC.	ISCAS	2007	DBLP DOI BibTeX RDF
37	Cheng Chen, Jiren Yuan	A 10-bit 500-MS/s 124-mW Subranging Folding ADC in 0.13 µm CMOS.	ISCAS	2007	DBLP DOI BibTeX RDF
37	Jere A. M. Järvinen, Mikko Saukoski, Kari Halonen	A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor Interface.	ISCAS	2007	DBLP DOI BibTeX RDF
37	Zhengming Fu, Eugenio Culurciello	An ultra-low power silicon-on-sapphire ADC for energy-scavenging sensors.	ISCAS	2006	DBLP DOI BibTeX RDF
37	Alessandro Cabrini, Franco Maloberti, Riccardo Rovatti, Gianluca Setti	On-line calibration of offset and gain mismatch in time-interleaved ADC using a sampled-data chaotic bit-stream.	ISCAS	2006	DBLP DOI BibTeX RDF
37	Seogheon Ham, Yonghee Lee, Wunki Jung, Seunghyun Lim, Kwisung Yoo, Youngcheol Chae, Jihyun Cho, Dongmyung Lee, Gunhee Han	CMOS image sensor with analog gamma correction using nonlinear single-slope ADC.	ISCAS	2006	DBLP DOI BibTeX RDF
37	M. R. Nabavi	A 1-V 12-bit switched-op amp pipelined ADC with power optimization.	ISCAS	2006	DBLP DOI BibTeX RDF
37	Guo-Ming Sung, Jyi-Hrong Tzeng, Chen-Shen Liao, Shih-Chieh Shu	A Low-power 7-b 33-Msamples/s Switched-current Pipelined ADC for Motor Control.	APCCAS	2006	DBLP DOI BibTeX RDF
37	Se-Won Kim, Young-Jae Cho, Kyung-Hoon Lee, Seung-Hoon Lee, Jae-Yup Lee, Hyun-Chul Noh, Hee-Sub Lee	An 8b 240 MS/s 1.36 mm2 104 mW 0.18 um CMOS ADC for DVDs with dual-mode inputs.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
37	Dinh Hung Dang, Yvon Savaria, Mohamad Sawan	A novel approach for implementing ultra-high speed flash ADC using MCML circuits.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
37	Martijn F. Snoeij, Albert J. P. Theuwissen, Johan H. Huijsing	A 1.8 V 3.2µW comparator for use in a CMOS imager column-level single-slope ADC.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
37	Qiong Wu 0013, Albert Z. Wang	A 12 bits/200 MHz resolution/sampling/power-optimized ADC in 0.25µm SiGe BiCMOS.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
37	Takeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata	A 1V supply successive approximation ADC with rail-to-rail input voltage range.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
37	Tae-Hwan Oh, Ho-Young Lee, Ho-Jin Park, Jae-Whui Kim	A 1.8V 8-bit 250Msample/s Nyquist-rate CMOS pipelined ADC.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
37	Kamal El-Sankary, Mohamad Sawan	A new digital background calibration technique for pipelined ADC.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
37	F. Esahani, Philipp Basedau, Roland Ryter, Rolf Becker	An 82 dB CMOS continuous-time complex bandpass sigma-delta ADC for GSM/EDGE.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
37	F. Hashemi, Khayrollah Hadidi, Abdollah Khoei	Design of a CMOS image sensor with pixel-level ADC in 0.35µm process.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
37	S. Mathur, M. Das, Preetam Tadeparthy, S. Ray, S. Mukherjee, B. L. Dinakaran	A 115mW 12-bit 50 MSPS pipelined ADC.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
37	Kuniyuki Tani, Norihiro Nikai, Atsushi Wada, Tetsuro Sawai	A pipelined ADC macro design for multiple applications.	ASP-DAC	2001	DBLP DOI BibTeX RDF
37	Zulhakimi Razak, Tughrul Arslan	Analog to Digital Converter Specification for UMTS/FDD Receiver Applications.	DELTA	2008	DBLP DOI BibTeX RDF	UMTS/FDD, specification, pipeline, ADC
37	Jian Ruan, Chung-Len Lee	A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application.	DELTA	2008	DBLP DOI BibTeX RDF	Sample-and-hold amplifier, Two-stage structure, Bootstrapped switch, Bottom-plate sampling, Pipelined ADC
37	Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell	Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	test flow optimization, analog and mixed-signal testing, ADC test
37	Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell	Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	Built-In Self-Test (BIST), analog and mixed-signal testing, ADC test
36	Ondrej Subrt, Petr Struhovský, Pravoslav Martínek, Jirí Hospodka	Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform.	DDECS	2008	DBLP DOI BibTeX RDF
36	Hanqing Xing, Degang Chen 0001, Randall L. Geiger, Le Jin	System identification -based reduced-code testing for pipeline ADCs' linearity test.	ISCAS	2008	DBLP DOI BibTeX RDF
36	Tomoki Tanoue, Munehiko Nagatani, Takao Waho	A Ternary Analog-to-Digital Converter System.	ISMVL	2007	DBLP DOI BibTeX RDF
36	Mohammad Taherzadeh-Sani, Anas A. Hamoui	Digital background calibration of interstage-gain and capacitor-mismatch errors in pipelined ADCs.	ISCAS	2006	DBLP DOI BibTeX RDF
36	SeongHwan Cho, Sungmin Ock, Sang-Hoon Lee, Joonsuk Lee	A low power pipelined analog-to-digital converter using series sampling capacitors.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
36	Shailesh Radhakrishnan, Mingzhen Wang, Chien-In Henry Chen	A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
36	Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen	A new CCII-based pipelined analog to digital converter.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
36	George Ginis, John M. Cioffi	Optimum bandwidth partitioning with analog-to-digital converter constraints.	IEEE Trans. Commun.	2004	DBLP DOI BibTeX RDF
36	Hanjun Jiang, Haibo Fei, Degang Chen 0001, Randall L. Geiger	A background digital self-calibration scheme for pipelined ADCs based on transfer curve estimation.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
36	Roman Genov, Gert Cauwenberghs	Algorithmic partial analog-to-digital conversion in mixed-signal array processors.	ISCAS (1)	2003	DBLP DOI BibTeX RDF