Search results for "ALTERA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
47	Erwin Halim, Nadira Altera, Placide Poba-Nzaou	The Impact of Perceived Risks to Continuance Intention on Using NFC Technology.	ICT	2023	DBLP DOI BibTeX RDF
47	Altera	User-configurable adapter interface chips for PS/2 micro channel.	Microprocess. Microsystems	1990	DBLP DOI BibTeX RDF
44	Richard H. Stern	West Coast Federal Appeals Court Upholds Chip Protection Act Violation Finding.	IEEE Micro	2007	DBLP DOI BibTeX RDF	antitrust violation, Semiconductor Chip Protection Act, chip piracy, monopoly, Altera, Clear Logic, reverse engineering, ASICs, law, bitstream
44	Petr Pfeifer	Multifunctional Programmable Single-Board CAN Monitoring Module.	FPL	2000	DBLP DOI BibTeX RDF	Student Papers, FPL2000, programmable device, ALTERA, FLEX6000, EPF6016, SJA1000, PC/104, CAN
38	Jay Kraut	Hardware Edge Detection using an Altera Stratix NIOS2 Development Kit.	CCECE	2006	DBLP DOI BibTeX RDF
38	P. Moore, Máire McLoone, Sakir Sezer	Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor.	AICT/SAPIR/ELETE	2005	DBLP DOI BibTeX RDF
38	Viktor Fischer, Milos Drutarovský, Martin Simka, Nathalie Bochard	High Performance True Random Number Generator in Altera Stratix FPLDs.	FPL	2004	DBLP DOI BibTeX RDF
38	François Charot, Eslam Yahya, Charles Wagner	Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA.	FPL	2003	DBLP DOI BibTeX RDF
33	Omar A. Al Rayahi, Mohammed A. S. Khalid	UWindsor Nios II: A soft-core processor for design space exploration.	EIT	2009	DBLP DOI BibTeX RDF
33	Arias Tanti Hapsari, Eniman Y. Syamsudin, Imron Pramana	Design of vehicle position tracking system using short message services and its implementation on FPGA.	ASP-DAC	2005	DBLP DOI BibTeX RDF
33	Hong Wang 0007, Robert A. Walker 0001	Implementing a Scalable ASC Processor.	IPDPS	2003	DBLP DOI BibTeX RDF
27	Ahmad Mouri Zadeh Khaki, Ebrahim Farshidi, Karim Ansari-Asl, Sawal Hamid Md. Ali, Masuri Othman	Design and Analysis of a Multirate 5-bit High-Order 52 fsrms Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA.	IEEE Access	2021	DBLP DOI BibTeX RDF
27	Matej Bartík	Reverse Engineering of Arrow USB Programmer2 JTAG Adapter for Intel/Altera FPGAs.	MECO	2020	DBLP DOI BibTeX RDF
27	Qasem Abu Al-Haija, Ibrahim Marouf, Mohammad M. Asad, Pankaj Mishra	Pipelined Implementation of Millar-Rabin Primality Tester Using Altera FPGA Kit.	SSCC	2019	DBLP DOI BibTeX RDF
27	Mohammad M. Asad, Ibrahim Marouf, Qasem Abu Al-Haija, Abdullah AlShuaibi	Performance Analysis of 128-bit Modular Inverse Based Extended Euclidean Using Altera FPGA Kit.	EUSPN/ICTH	2019	DBLP DOI BibTeX RDF
27	Pan Li 0001, Rui Zhang, Jing Zhang, Jie Li, Guanxing Zhao, Hua Li	Design of Radar Electromagnetic Environment Simulation System Based on Altera Stratix® III Series FPGA.	ICSAI	2018	DBLP DOI BibTeX RDF
27	Umut Ulutas, Mustafa Tosun, Vecdi Emre Levent, Duygu Büyükaydin, Toygar Akgün, H. Fatih Ugurdag	FPGA Implementation of a Dense Optical Flow Algorithm Using Altera OpenCL SDK.	ICT Innovations	2017	DBLP DOI BibTeX RDF
27	Harald Homulle, Edoardo Charbon	Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures.	FPT	2017	DBLP DOI BibTeX RDF
27	Qing Y. Tang, Mohammed A. S. Khalid	Acceleration of k-Means Algorithm Using Altera SDK for OpenCL.	ACM Trans. Reconfigurable Technol. Syst.	2016	DBLP DOI BibTeX RDF
27	Ricardo Tapiador, Antonio Rios-Navarro, Alejandro Linares-Barranco, Minkyu Kim 0001, Deepak Kadetotad, Jae-sun Seo	Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs.	CoRR	2016	DBLP BibTeX RDF
27	Ian Janik, Mohammed A. S. Khalid	Synthesis and evaluation of SHA-1 algorithm using altera SDK for OpenCL.	MWSCAS	2016	DBLP DOI BibTeX RDF
27	Derek Chiou	Intel Acquires Altera: How Will the World of FPGAs be Affected?	FPGA	2016	DBLP DOI BibTeX RDF
27	Zhenzhong Xiao, Dirk Koch, Mikel Luján	A partial reconfiguration controller for Altera Stratix V FPGAs.	FPL	2016	DBLP DOI BibTeX RDF
27	Dustin Richmond, Jeremy Blackstone, Matthew Hogains, Kevin Thai, Ryan Kastner	Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler.	FCCM	2016	DBLP DOI BibTeX RDF
27	Hiroki Nakahara, Akira Jinguji, Tomonori Fujii, Simpei Sato	An acceleration of a random forest classification using Altera SDK for OpenCL.	FPT	2016	DBLP DOI BibTeX RDF
27	Naraig Manjikian	Retargeting and enhancing a compact multitasking kernel for the Altera Nios II processor.	CCECE	2016	DBLP DOI BibTeX RDF
27	Pawel Swierczynski, Amir Moradi 0001, David F. Oswald, Christof Paar	Physical Security Evaluation of the Bitstream Encryption Mechanism of Altera Stratix II and Stratix III FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2015	DBLP DOI BibTeX RDF
27	Ian Janik, Qing Y. Tang, Mohammed A. S. Khalid	An overview of Altera SDK for OpenCL: A user perspective.	CCECE	2015	DBLP DOI BibTeX RDF
27	Quentin Gautier, Alexandria Shearer, Janarbek Matai, Dustin Richmond, Pingfan Meng, Ryan Kastner	Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK.	FPT	2014	DBLP DOI BibTeX RDF
27	Linus Feiten, Andreas Spilla, Matthias Sauer 0002, Tobias Schubert 0001, Bernd Becker 0001	Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs.	Inf. Secur. J. A Glob. Perspect.	2013	DBLP DOI BibTeX RDF
27	Athanasios Kalantzopoulos, Emmanouil Galetakis, Christos Katsenos, Evangelos Zigouris	An Interactive Remote Laboratory on Basic Computer Architecture Using Altera DE2 Board.	Int. J. Online Eng.	2013	DBLP DOI BibTeX RDF
27	Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling	Harnessing the power of FPGAs using altera's OpenCL compiler.	FPGA	2013	DBLP DOI BibTeX RDF
27	Amir Moradi 0001, David F. Oswald, Christof Paar, Pawel Swierczynski	Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering.	FPGA	2013	DBLP DOI BibTeX RDF
27	Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, Rabia Shahid, Malik Umar Sharif	Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs.	IACR Cryptol. ePrint Arch.	2012	DBLP BibTeX RDF
27	Phani Balaji Swamy Tangellapalli, Syed Rafay Hasan	Towards low area overhead ARQ based soft error tolerant data paths for SRAM-based Altera FPGAs.	MWSCAS	2012	DBLP DOI BibTeX RDF
27	Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj	Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs.	CHES	2011	DBLP DOI BibTeX RDF
27	Christophe Alias, Alain Darte, Alexandru Plesco	Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool.	ASAP	2010	DBLP DOI BibTeX RDF
27	Bassam Shaer, Steven Silvester, Darrell Card	LADAR System Development Using the Altera DE1 Board.	ESA	2010	DBLP BibTeX RDF
27	Dan Mansur	Newest additions to Altera's integrated transceiver portfolio.	Hot Chips Symposium	2009	DBLP DOI BibTeX RDF
27	Coral Gonzalez-Concejero, Victoria Rodellar, Agustín Álvarez Marquina, Elvira Martínez de Icaya, Pedro Gómez Vilda	An FFT/IFFT Design versus Altera and Xilinx Cores.	ReConFig	2008	DBLP DOI BibTeX RDF
27	Hamid R. Zarandi, Seyed Ghassem Miremadi	Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
27	Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu	Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits.	IWDC	2004	DBLP DOI BibTeX RDF
27	Marcin Rogawski	Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices	CoRR	2003	DBLP BibTeX RDF
27	Marcin Rogawski	Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices.	IACR Cryptol. ePrint Arch.	2003	DBLP BibTeX RDF
27	Razak Mohammedali	Altera FPGA Technology Provides Innovative Solutions for Evolving Market Needs.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
27	Karl Rihaczek	Audiatur et altera pars.	Datenschutz und Datensicherheit	2002	DBLP BibTeX RDF
27	Alex Panato, Marcelo Barcelos, Ricardo Reis 0001	An IP of an Advanced Encryption Standard for Altera" Devices.	SBCCI	2002	DBLP BibTeX RDF
27	James O. Hamblen, Gregory E. Ruhl	Using the Altera UP-1 Board for Prototyping and VGA Video Display Generation.	MSE	1999	DBLP DOI BibTeX RDF
27	Andrzej Hlawiczka, Jacek Binda	Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures.	FPL	1994	DBLP DOI BibTeX RDF
27	André Klindworth	A Tool-Set for Simulating Altera-PLDs Using VHDL.	FPL	1994	DBLP DOI BibTeX RDF
22	Scott Cromar, Jaeho Lee, Deming Chen	FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation.	DAC	2009	DBLP DOI BibTeX RDF	glitch power, FPGA, high-level synthesis, power reduction
22	Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck	Fpga-based data acquisition system for a positron emission tomography (PET) scanner.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, positron emission tomography
22	Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong	Place-and-Route Impact on the Security of DPL Designs in FPGAs.	HOST	2008	DBLP DOI BibTeX RDF
22	Kevin Oo Tinmaung, David Howland, Russell Tessier	Power-aware FPGA logic synthesis using binary decision diagrams.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, binary decision diagram, dynamic power
22	Stevan M. Bererber, Chih-Hong Wang, Kevin K. Wei	Design of a CDMA System in FPGA Technology.	VTC Spring	2007	DBLP DOI BibTeX RDF
22	Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan	Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories.	DFT	2007	DBLP DOI BibTeX RDF
22	V. Amudha, B. Venkataramani, R. Vinoth Kumar, S. Ravishankar	SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System.	VLSI Design	2007	DBLP DOI BibTeX RDF
22	Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier	An adaptive Reed-Solomon errors-and-erasures decoder.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, power reduction, Reed-Solomon
22	Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown	A Multithreaded Soft Processor for SoPC Area Reduction.	FCCM	2006	DBLP DOI BibTeX RDF
22	Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown	Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.	SLIP	2006	DBLP DOI BibTeX RDF
22	Martin Simka, Milos Drutarovský, Viktor Fischer, J. Fayolle	Model of a true random number generator aimed at cryptographic applications.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	Design of a radix-2m hybrid array multiplier using carry save adder format.	SBCCI	2005	DBLP DOI BibTeX RDF	hybrid multiplier, low power, carry save adder
22	H. G. Epassa, François R. Boyer, Yvon Savaria	Implementation of a cycle by cycle variable speed processor.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
22	Paul Metzgen	A high performance 32-bit ALU for programmable logic.	FPGA	2004	DBLP DOI BibTeX RDF	ALU, Apex 20KE, Nios, FPGA, programmable logic, soft processors
22	Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang	Performance-driven mapping for CPLD architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
22	Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson	Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
22	Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland	Implementing Asynchronous Circuits on LUT Based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
22	Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana	A Sum of Absolute Differences Implementation in FPGA Hardware.	EUROMICRO	2002	DBLP DOI BibTeX RDF
11	Charles Eric LaForest, J. Gregory Steffan	Efficient multi-ported memories for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, parallel, memory, multi-port
11	Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici	Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture.	FPGA	2010	DBLP DOI BibTeX RDF	conjugate gradient (CG), finite-element modeling (FEM), field-programmable gate array (FPGA)
11	Flavius Opritoiu, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu	A high-speed AES architecture implementation.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cryptochip, optimization, fpga, hardware, aes
11	Shiuh-Jer Huang, Shian-Shin Wu	Vision-Based Robotic Motion Control for Non-autonomous Environment.	J. Intell. Robotic Syst.	2009	DBLP DOI BibTeX RDF	Self-organizing fuzzy control, FPGA chip, Visual servo, Robotic system
11	Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung	Self-Measurement of Combinatorial Circuit Delays in FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, Testing, configuration, delay measurement
11	G. Seetharaman, B. Venkataramani	Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA
11	Camel Tanougast, Michael Janiaut, Yves Berviller, Hassan Rabah, Serge Weber, Ahmed Bouridane	An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis.	IEEE Trans. Circuits Syst. Video Technol.	2009	DBLP DOI BibTeX RDF
11	Michael Dyer, Saeid Nooshabadi, David S. Taubman	Design and Analysis of System on a Chip Encoder for JPEG2000.	IEEE Trans. Circuits Syst. Video Technol.	2009	DBLP DOI BibTeX RDF
11	Miad Faezipour, Mehrdad Nourani, Rina Panigrahy	A hardware platform for efficient worm outbreak detection.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	shared counters, worm outbreak, hashing, false positive, Network Intrusion Detection System, false negative, polymorphic worm
11	Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada	All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.	DDECS	2009	DBLP DOI BibTeX RDF
11	Xin Xiao, Erdal Oruklu, Jafar Saniie	Fast memory addressing scheme for radix-4 FFT implementation.	EIT	2009	DBLP DOI BibTeX RDF
11	Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani	Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller.	FPGA	2009	DBLP DOI BibTeX RDF	adc, sd card, fpga, real-time, multiplexing, data acquisition, fft
11	Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau	Measuring and modeling variabilityusing low-cost FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	variability
11	Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour	Towards automated ECOs in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	pst, optimization, fpga, boolean satisfiability, resynthesis
11	Taehoon Kim, Sungwoo Tak	A real-time hardware-software codesign technique of network protocols to provide QoS.	ICHIT	2009	DBLP DOI BibTeX RDF	QoS communications architecture, real-time scheduling, network protocols, hardware-software codesign
11	Robson Dornelles, Felipe Sampaio, Daniel Palomino 0001, Luciano Volcan Agostini	Transforms and quantization design targeting the H.264/AVC intra prediction constraints.	SBCCI	2009	DBLP DOI BibTeX RDF	IQ modules, Q, T, IT, video coding, high performance, H.264/AVC, VLSI design, low latency, intra-prediction
11	Valerij Matrose, Carsten Gremzow	Improved placement for hierarchical FPGAs exploiting local interconnect resources.	SBCCI	2009	DBLP DOI BibTeX RDF	FPGA, interconnect, placement
11	Jie Zhou 0007, Yong Dou, Jianxun Zhao, Fei Xia, Yuanwu Lei, Yuxing Tang	A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA.	APPT	2009	DBLP DOI BibTeX RDF
11	Pouya Dormiani, Milos D. Ercegovac, Jean-Michel Muller	Design and Implementation of a Radix-4 Complex Division Unit with Prescaling.	ASAP	2009	DBLP DOI BibTeX RDF
11	Saraju P. Mohanty, Elias Kougianos, Wei Cai, Manish Ratnani	VLSI architectures of perceptual based video watermarking for real-time copyright protection.	ISQED	2009	DBLP DOI BibTeX RDF
11	Yu-Te Su, Chun-Yang Hu, Tzuu-Hseng S. Li	FPGA-Based Vocabulary Recognition Module for Humanoid Robot.	FIRA	2009	DBLP DOI BibTeX RDF	FPGA-based, humanoid robot
11	J. Manikandan, B. Venkataramani, V. Avanthi	FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System.	VLSI Design	2009	DBLP DOI BibTeX RDF
11	Kimmo U. Järvinen, Jorma Skyttä	On Parallelization of High-Speed Processors for Elliptic Curve Cryptography.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
11	Joshua Noseworthy, Miriam Leeser	Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
11	Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung	Outer Loop Pipelining for Application Specific Datapaths in FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
11	Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle	Radio frequency identification prototyping.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low-power, RFID, prototyping, Design automation
11	Eero Aho, Jarno Vanne, Timo D. Hämäläinen	Configurable Data Memory for Multimedia Processing.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	stride access, configurable, parallel memory, skewing scheme, SIMD processing
11	Jason Yu, Guy G. Lemieux, Christopher Eagleston	Vector processing as a soft-core CPU accelerator.	FPGA	2008	DBLP DOI BibTeX RDF	C2H, FPGA, configurable, embedded processor, application specific, soft processor, data-level parallelism
11	Jeremy Buboltz, Taskin Koçak	Front End Device for Content Networking.	DATE	2008	DBLP DOI BibTeX RDF
11	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming.	DATE	2008	DBLP DOI BibTeX RDF
11	Carlo Brandolese, William Fornaciari	Measurement, Analysis and Modeling of RTOS System Calls Timing.	DSD	2008	DBLP DOI BibTeX RDF
11	Weijun Zhang, Yujie Dun, Weixiang Shi, Baogang Miao, Bingo Zhang	High Productivity Computing System Based on FPGA and Its Application on Plasma Simulation.	HPCC	2008	DBLP DOI BibTeX RDF