Search results for "ALU"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
129	Paul Metzgen	A high performance 32-bit ALU for programmable logic.	FPGA	2004	DBLP DOI BibTeX RDF	ALU, Apex 20KE, Nios, FPGA, programmable logic, soft processors
117	Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno	Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors.	ASYNC	2001	DBLP DOI BibTeX RDF
116	James Phillips, Stamatis Vassiliadis	High-Performance 3-1 Interlock Collapsing ALU's.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	3-1 interlock collapsing ALU, execution interlocks, multiple instruction issuing machines, parallel architectures, delay, digital arithmetic, CMOS technology, critical path, reduced instruction set computing, Boolean equations
102	Steven S. Gorshe, Bella Bose	A self-checking ALU design with efficient codes.	VTS	1996	DBLP DOI BibTeX RDF	self-checking ALU design, self-testing ALU, VLSI, logic testing, built-in self test, integrated circuit testing, logic design, error detection codes, error detecting codes, integrated logic circuits, unidirectional errors
93	Soontae Kim	Reducing ALU and Register File Energy by Dynamic Zero Detection.	IPCCC	2007	DBLP DOI BibTeX RDF
93	R. D. (Shawn) Blanton, John P. Hayes	Design of a fast, easily testable ALU.	VTS	1996	DBLP DOI BibTeX RDF	ALU, adder design, L-testable design, level-testable, carry-lookahead addition, fault diagnosis, logic testing, integrated circuit testing, automatic testing, digital arithmetic, integrated circuit design, adders, logic arrays, test patterns, area overhead, functional faults, carry logic, arithmetic-logic unit, 8 bit
82	Shruti R. Patil, Xiaofeng Yao, Hao Meng, Jianping Wang, David J. Lilja	Design of a spintronic arithmetic and logic unit using magnetic tunnel junctions.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	alu design, magnetic tunnel junction, spintronic alu design, spintronics
81	Yu Zhou, Hui Guo	Application Specific Low Power ALU Design.	EUC (1)	2008	DBLP DOI BibTeX RDF
80	Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy 0001	A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies.	ISLPED	2004	DBLP DOI BibTeX RDF	DSM leakage control and scaling trends, dual supply ALU design, low power techniques
69	Ronald D. Blanton, John P. Hayes	On the design of fast, easily testable ALU's.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
69	Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao, Michael Nicolaidis	An SFS Berger check prediction ALU and its application to self-checking processor designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
68	R. S. Hogg, W. I. Hughes, David W. Lloyd	A Novel Asynchronous ALU for Massively Parallel Architectures.	PDP	1996	DBLP DOI BibTeX RDF	novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit
68	Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto	A 13.3ns double-precision floating-point ALU and multiplier.	ICCD	1995	DBLP DOI BibTeX RDF	double-precision floating-point ALU, floating-point multiplier, carry select addition, prerounding techniques, noise tolerant precharge circuit, two-cycle latency, 13.3 ns, 0.3 micron, 2.5 V, 150 MHz, normalization, floating point arithmetic, CMOS integrated circuits, multiplying circuits, CMOS technology, arithmetic logic unit
62	Yves Quentin	Origin of the Alu family: a family of Alu-like monomers gave birth to the left and the right arms of the Alu elements.	Nucleic Acids Res.	1992	DBLP DOI BibTeX RDF
57	Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura	A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection.	IPDPS	2005	DBLP DOI BibTeX RDF
57	Steven Hsu, Amit Agarwal 0001, Kaushik Roy 0001, Ram Krishnamurthy 0001, Shekhar Borkar	An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS.	ISLPED	2005	DBLP DOI BibTeX RDF	dual-Vt/Vcc, flip-flop, hot spot, level converter
57	Mark G. Arnold	LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS.	PATMOS	2004	DBLP DOI BibTeX RDF
57	Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam	A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy.	ISCA	2004	DBLP DOI BibTeX RDF	Complexity-effective design, Temporal Redundancy, Instruction Reuse
57	Warren A. Hunt Jr., Bishop Brock	The Verification of a Bit-slice ALU.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
48	Muhammad Taha, Tarek Helmy, Reda Abo Alez	Agent Based Arabic Language Understanding.	Web Intelligence/IAT Workshops	2007	DBLP DOI BibTeX RDF
48	Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles	Exploring the VLSI Scalability of Stream Processors.	HPCA	2003	DBLP DOI BibTeX RDF
47	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	An algorithm for mapping loops onto coarse-grained reconfigurable architectures.	LCTES	2003	DBLP DOI BibTeX RDF	ALU array, memory bandwidth utilization, coarse-grained reconfigurable architecture, mapping algorithm
45	Bhaskar Chatterjee, Manoj Sachdev	Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
45	Francesco Pessolano, R. I. M. P. Meijer	A 260ps Quasi-static ALU in 90nm CMOS.	PATMOS	2004	DBLP DOI BibTeX RDF
45	Kunihiro Yamada, Yukihisa Naoe, Masanori Kojima, Tadanori Mizuno	A New MPEG-2 Solution Using a 2nd ALU in the RISC.	KES	2003	DBLP DOI BibTeX RDF
45	Karthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, Doug Burger	Routed Inter-ALU Networks for ILP Scalability and Performance.	ICCD	2003	DBLP DOI BibTeX RDF
44	Makoto Ozone, Tatsuo Hiramatsu, Katsunori Hirase, Kazuhisa Iizuka	Reconfigurable Processor LSI Based on ALU Array with Limitations of Connections of ALUs for Software Radio.	ITNG	2009	DBLP DOI BibTeX RDF	ALU array, software define radio, data flow graph, reconfigurable processor
44	Wenzhe Luo, Graham A. Jullien, Neil M. Wigley, William C. Miller, Zhongde Wang	An array processor for inner product computations using a Fermat number ALU.	ASAP	1995	DBLP DOI BibTeX RDF	inner product computations, Fermat number ALU, parallel independent computations, polynomial mapping, computational ring, parallel architectures, residue number systems
42	Konstantina Miteloudi, Joppe W. Bos, Olivier Bronchain, Björn Fay, Joost Renes	PQ.V.ALU.E: Post-Quantum RISC-V Custom ALU Extensions on Dilithium and Kyber.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
42	Konstantina Miteloudi, Joppe W. Bos, Olivier Bronchain, Björn Fay, Joost Renes	PQ.V.ALU.E: Post-quantum RISC-V Custom ALU Extensions on Dilithium and Kyber.	CARDIS	2023	DBLP DOI BibTeX RDF
36	Miroslav N. Velev	Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units.	CHARME	2005	DBLP DOI BibTeX RDF
36	Hugo de Garis, Thayne Batty, Wang Ce	FemtoComputing: New Architectural Ideas for Procedural and Evolutionary Computers Whose Components Switch in Femto-Seconds.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
36	Michael Nicolaidis	Carry checking/parity prediction adders and ALUs.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
36	Kwong-Sak Leung, Kin-Hong Lee, Sin Man Cheang	Parallel Programs Are More Evolvable than Sequential Programs.	EuroGP	2003	DBLP DOI BibTeX RDF
36	Ivo Bolsens	Challenges and Opportunities for FPGA Platforms.	FPL	2002	DBLP DOI BibTeX RDF
36	David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha	Early Zero Detection.	ICCD	1996	DBLP DOI BibTeX RDF	half-adder form, branch penalties, branch resolution, zero detection, speculative execution, ILP
36	F. Kampf, P. Koch, K. Roy, M. Sullivan, Z. Delalic, S. DasGupta	Optimization of a digital neuron design.	Annual Simulation Symposium	1990	DBLP DOI BibTeX RDF
35	David W. Matula, Asger Munk Nielsen	Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations
34	Xingtuo Zhang, Yiyi Zhang, Alu Xu, Chunli Meng, Zhonghuan Su	Electrical Insulator Surface Condition Analysis Based on Joint Fully Convolutional and Multiscale Spatial Pooling Attention Network.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
34	Stéphane D'Alu, Hervé Rivano, Olivier Simonin 0001	TDoA for In-Flight Relative Localization in UAV Swarm using Ultra-Wide Band.	IPIN-WiP	2023	DBLP BibTeX RDF
34	Fabrizio Vecchio, Francesca Miraglia, Francesca Alù, Elda Judica, Maria Cotelli, Maria Concetta Pellicciari, Paolo Maria Rossini	Human Brain Networks in Physiological and Pathological Aging: Reproducibility of Electroencephalogram Graph Theoretical Analysis in Cortical Connectivity.	Brain Connect.	2022	DBLP DOI BibTeX RDF
34	Aravind Nagulu, Ahmed Mekkawy, Mykhailo Tymchenko, Dimitrios L. Sounas, Andrea Alù, Harish Krishnaswamy	Ultra-Wideband Switched-Capacitor Delays and Circulators - Theory and Implementation.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
34	Mirko Barbuto, Andrea Alù, Filiberto Bilotti, Alessandro Toscano	Dual-Circularly Polarized Topological Patch Antenna With Pattern Diversity.	IEEE Access	2021	DBLP DOI BibTeX RDF
34	Fabrizio Vecchio, Francesca Miraglia, Chiara Pappalettera, Alessandro Orticoni, Francesca Alù, Elda Judica, Maria Cotelli, Paolo Maria Rossini	Entropy as Measure of Brain Networks' Complexity in Eyes Open and Closed Conditions.	Symmetry	2021	DBLP DOI BibTeX RDF
34	Mykhailo Tymchenko, Aravind Nagulu, Harish Krishnaswamy, Andrea Alù	Universal Frequency-Domain Analysis of N-Path Networks.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
34	Fabrizio Vecchio, Chiara Pappalettera, Francesca Miraglia, Francesca Alù, Alessandro Orticoni, Elda Judica, Maria Cotelli, Francesca Pistoia, Paolo Maria Rossini	Graph Theory on Brain Cortical Sources in Parkinson's Disease: The Analysis of 'Small World' Organization from EEG.	Sensors	2021	DBLP DOI BibTeX RDF
34	Andrea Alù	Opportunities for Millemeter-Wave Wireless Technologies Using Metasurfaces.	BCICTS	2021	DBLP DOI BibTeX RDF
34	Francesca Miraglia, Fabrizio Vecchio, Camillo Marra, Davide Quaranta, Francesca Alù, Benedetta Peroni, Giuseppe Granata, Elda Judica, Maria Cotelli, Paolo Maria Rossini	Small World Index in Default Mode Network Predicts Progression from Mild Cognitive Impairment to Dementia.	Int. J. Neural Syst.	2020	DBLP DOI BibTeX RDF
34	Ying-Tao Luo, Peng-Qi Li, Dong-Ting Li, Yu-Gui Peng, Zhi-Guo Geng, Shu-Huan Xie, Yong Li, Andrea Alù, Jie Zhu, Xue Feng Zhu	Probability-Density-Based Deep Learning Paradigm for the Fuzzy Design of Functional Metastructures.	CoRR	2020	DBLP BibTeX RDF
34	Mario Miscuglio, Yaliang Gui, Xiaoxuan Ma, Shuai Sun, Tarek A. El-Ghazawi, Tatsuo Itoh, Andrea Alù, Volker J. Sorger	Analog Computing with Metatronic Circuits.	CoRR	2020	DBLP BibTeX RDF
34	Francesca Alù, Francesca Miraglia, Alessandro Orticoni, Elda Judica, Maria Cotelli, Paolo Maria Rossini, Fabrizio Vecchio	Approximate Entropy of Brain Network in the Study of Hemispheric Differences.	Entropy	2020	DBLP DOI BibTeX RDF
34	Alex Krasnok, Andrea Alù	Active Nanophotonics.	Proc. IEEE	2020	DBLP DOI BibTeX RDF
34	Andrea Alù	Magnet-Free Nonreciprocity [Scanning the Section].	Proc. IEEE	2020	DBLP DOI BibTeX RDF
34	Andrea Alù, Hilmi Volkan Demir, Chennupati Jagadish	Active Nanophotonics [Scanning the Issue].	Proc. IEEE	2020	DBLP DOI BibTeX RDF
34	Ahmed Kord, Dimitrios L. Sounas, Andrea Alù	Microwave Nonreciprocity.	Proc. IEEE	2020	DBLP DOI BibTeX RDF
34	Stéphane D'Alu, Oana Iova, Olivier Simonin 0001, Hervé Rivano	Demo: In-flight Localisation of Micro-UAVs using Ultra-Wide Band.	EWSN	2020	DBLP BibTeX RDF
34	Andrea Alù	Magnet-Free Routes to Nonreciprocal Photonics.	ECOC	2020	DBLP DOI BibTeX RDF
34	Lina Han, Jiquan Zhang, Yichen Zhang, Qing Ma, Alu Si, Qiuling Lang	Hazard Assessment of Earthquake Disaster Chains Based on a Bayesian Network Model and ArcGIS.	ISPRS Int. J. Geo Inf.	2019	DBLP DOI BibTeX RDF
34	Alu Si, Jiquan Zhang, Siqin Tong, Quan Lai, Rui Wang, Na Li, Yongbin Bao	Regional Landslide Identification Based on Susceptibility Analysis and Change Detection.	ISPRS Int. J. Geo Inf.	2018	DBLP DOI BibTeX RDF
34	Li Na, Jiquan Zhang, Yulong Bao, Yongbin Bao, Risu Na, Siqin Tong, Alu Si	Himawari-8 Satellite Based Dynamic Monitoring of Grassland Fire in China-Mongolia Border Regions.	Sensors	2018	DBLP DOI BibTeX RDF
34	Patrice Raveneau, Stephane D'Alu, Hervé Rivano	Localisation based on Wi-Fi fingerprints: A crowdsensing approach with a device-to-device aim.	PerCom Workshops	2017	DBLP DOI BibTeX RDF
34	Laëtitia Matignon, Stephane D'Alu, Olivier Simonin 0001	Multi-robot human scene observation based on hybrid metric-topological mapping.	ECMR	2017	DBLP DOI BibTeX RDF
34	Francesco Monticone, Andrea Alù	Leaky-Wave Theory, Techniques, and Applications: From Microwaves to Visible Frequencies.	Proc. IEEE	2015	DBLP DOI BibTeX RDF
34	Pai-Yen Chen, Andrea Alù	THz beamforming using graphene-based devices.	RWS	2013	DBLP DOI BibTeX RDF
34	Yang Zhao, Andrea Alù	Optical nanoantennas and their applications.	RWS	2013	DBLP DOI BibTeX RDF
34	Andrea Alù, Nader Engheta	Optical Metamaterials Based on Optical Nanocircuits.	Proc. IEEE	2011	DBLP DOI BibTeX RDF
34	Andrea Alù, Carmine Sapia, Alessandro Toscano, Lucio Vegni	Radio frequency animal identification: electromagnetic analysis and experimental evaluation of the transponder-gate system.	Int. J. Radio Freq. Identif. Technol. Appl.	2006	DBLP DOI BibTeX RDF
34	Mauro Manzini, Andrea Alù, Filiberto Bilotti, Lucio Vegni	Polygonal patch antennas for wireless communications.	IEEE Trans. Veh. Technol.	2004	DBLP DOI BibTeX RDF
34	Peter Adebayo Idowu, A. O. Alu, E. R. Adagunodo	The Effect of Information Technology on the Growth of the Banking Industry in Nigeria.	Electron. J. Inf. Syst. Dev. Ctries.	2002	DBLP DOI BibTeX RDF
33	Ioannis Voyiatzis	An ALU-Based BIST Scheme for Word-Organized RAMs.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Memory control and access, Reliability, Test generation, Built-In Tests, Testing and Fault-Tolerance, Semiconductor Memories
33	Pak-Keung Leung, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	A low power asynchronous GF(2173) ALU for elliptic curve crypto-processor.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
33	Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang 0001, Whay Sing Lee	Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor.	ISCA	1998	DBLP DOI BibTeX RDF
24	Sunwoo Kim, Won Woo Ro	FPGA implementation of highly parallelized decoder logic for network coding (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, network coding, fpga implementation, galois field arithmetic
24	Fatemeh Eslami, Amirali Baniasadi, Mostafa Farahani	Application Specific Transistor Sizing for Low Power Full Adders.	ASAP	2009	DBLP DOI BibTeX RDF
24	Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala	A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	performance, design
24	Xiaohong Qiu, Jaliya Ekanayake, Scott Beason, Thilina Gunarathne, Geoffrey C. Fox, Roger S. Barga, Dennis Gannon	Cloud technologies for bioinformatics applications.	SC-MTAGS	2009	DBLP DOI BibTeX RDF	Dryad, MPI, bioinformatics, multicore, cloud, Hadoop
24	Yuzhong Jiao, Xin'an Wang, Xuewen Ni	A Fully Data-Driven Reconfigurable Architecture with Very Coarse-Grained Execution Units.	Infoscale	2009	DBLP DOI BibTeX RDF	Processing element (PE), Execution unit (EU), Very-coarse-grained, Fully-data-driven, Reconfigurable architecture
24	Swaroop Ghosh, Kaushik Roy 0001	Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.	ASP-DAC	2008	DBLP DOI BibTeX RDF
24	Toshinori Sato, Shingo Watanabe	Instruction Scheduling for Variation-Originated Variable Latencies.	ISQED	2008	DBLP DOI BibTeX RDF	variable latency adder, long latency adder, instruction criticality, microprocessors, parameter variations
24	Sean O'Rourke, Noah Zaitlen, Nebojsa Jojic, Eleazar Eskin	Reconstructing the Phylogeny of Mobile Elements.	RECOMB	2007	DBLP DOI BibTeX RDF
24	Krishnan Sundaresan, Nihar R. Mahapatra	An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires.	DAC	2007	DBLP DOI BibTeX RDF
24	A. J. KleinOsowski, Kevin KleinOsowski, Vijay Rangarajan, Priyadarshini Ranganath, David J. Lilja	The Recursive NanoBox Processor Grid: A Reliable System Architecture for Unreliable Nanotechnology Devices.	DSN	2004	DBLP DOI BibTeX RDF	architecture, VLSI, fault-injection, nanotechnology, fault-masking
24	Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer	False-Noise Analysis for Domino Circuits.	DATE	2004	DBLP DOI BibTeX RDF
24	Ahmet Bindal, Silvio Brugada, T. Ha, Willie Sana, Mandeep Singh, Vinilkant Tejaswi, David Wyland	A Simple Micro-Threaded Data-Driven Processor.	DSD	2004	DBLP DOI BibTeX RDF
24	Timothy Daryl Stanley	Bringing bits, bytes, devices and computers to life with designs in multimedia logic.	SIGITE Conference	2004	DBLP DOI BibTeX RDF	binary visualization, multimedia logic, logic simulation, computer design
24	Vasily G. Moshnyaga	Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	bit-truncation, low-power design, video processing, switching activity
24	Edwin A. Hakkennes, Stamatis Vassiliadis	Multimedia Execution Hardware Accelerator.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	multimedia architectures, multimedia instruction set, multimedia processors, compound instructions, multimedia, hardware accelerators, subword parallelism, SIMD processors, vector architectures
24	Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler	A design space evaluation of grid processor architectures.	MICRO	2001	DBLP DOI BibTeX RDF
24	Narasimhan Ramasubramanian, Ram Subramanian, Santosh Pande	Automatic Analysis of Loops to Exploit Operator Parallelism on Reconfigurable Systems.	LCPC	1998	DBLP DOI BibTeX RDF
24	Hyunman Chang, Changhee Lee, Myung Hoon Sunwoo	SliM-II: A Linear Array SIMD Processor for Real-time Image Processing.	ICPADS	1997	DBLP DOI BibTeX RDF
24	David M. Dahle, Jeffrey D. Hirschberg, Kevin Karplus, Hansjörg Keller, Eric Rice, Don Speck, Douglas H. Williams, Richard Hughey	Kestrel: Design of an 8-bit SIMD Parallel Processor.	ARVLSI	1997	DBLP DOI BibTeX RDF
24	Hyunman Chang, Soohwan Ong, Myung Hoon Sunwoo	A Linear Array Parallel Image Processor: SliM-II.	ASAP	1997	DBLP DOI BibTeX RDF
24	Suntae Hwang, Rochit Rajsuman, Yashwant K. Malaiya	On the testing of microprogrammed processor.	MICRO	1990	DBLP BibTeX RDF
24	Diederik Verkest, Luc J. M. Claesen, Hugo De Man	Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment.	EURO-DAC	1990	DBLP DOI BibTeX RDF
24	T. R. N. Rao, Harry J. Reinheimer	Fault-tolerant modularized arithmetic logic units.	AFIPS National Computer Conference	1977	DBLP DOI BibTeX RDF
24	William B. Langdon, Wolfgang Banzhaf	Repeated patterns in genetic programming.	Nat. Comput.	2008	DBLP DOI BibTeX RDF	Genetic alogorithms, ALU, Macky-Glass, Poly-10, Nuclear protein localisation, Tiny GP, GPquick, Evolution of program shape, Sensitivity analysis, Frequent subgraphs, SINE, Frequent subtrees
23	Alan Marshall, Tony Stansfield, Igor Kostarnov, Jean Vuillemin, Brad L. Hutchings	A Reconfigurable Arithmetic Array for Multimedia Application.	FPGA	1999	DBLP DOI BibTeX RDF	4-bit ALU, FPGA, multimedia, reconfigurable computing
23	Kazumi Hatayama, Kazunori Hikone, Takeshi Miyazaki, Hiromichi Yamada	A practical approach to instruction-based test generation for functional modules of VLSI processors.	VTS	1997	DBLP DOI BibTeX RDF	VLSI processors, instruction-based test generation, functional test pattern generation, gate level faults, constrained test generation, ALU oriented test pattern generation system, VLSI, functional modules, ALPS
23	Waldo C. Kabat, Anthony S. Wojcik	On the Design of 4-Valued Digital Systems.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	T-gate, 4-valued ALU, Post algebra, multivalued logic, Boolean algebra, digital system design
21	S. Senthilmurugan, K. Gunaseelan	Performance Analysis of Multicore Processor Using FOFO-Based Approximate Compatible ALU.	J. Circuits Syst. Comput.	2024	DBLP DOI BibTeX RDF