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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 322 occurrences of 165 keywords
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Results
Found 391 publication records. Showing 391 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
88 | Naser MohammadZadeh, Morteza NajafVand, Shaahin Hessabi, Maziar Goudarzi |
Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
ODYSSEY, embedded systems, ASIP, JPEG |
83 | Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael De Nil, Jef L. van Meerbergen |
Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP. |
HiPEAC |
2008 |
DBLP DOI BibTeX RDF |
|
83 | Sung Dae Kim, Jeong Hoo Lee, Chung Jin Hyun, Myung Hoon Sunwoo |
ASIP approach for implementation of H.264/AVC. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
75 | Thorsten von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll |
ASIP-eFPGA Architecture for Multioperable GNSS Receivers. |
SAMOS |
2008 |
DBLP DOI BibTeX RDF |
arithmetic oriented eFPGA, multioperable GNSS, ASIP |
75 | Quang Dinh, Deming Chen, Martin D. F. Wong |
Efficient ASIP design for configurable processors with fine-grained resource sharing. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
multi-cycle IO, compilation, ASIP, resource sharing, configurable processor |
75 | Tilman Glökler, Andreas Hoffmann 0002, Heinrich Meyr |
Methodical Low-Power ASIP Design Space Exploration. |
J. VLSI Signal Process. |
2003 |
DBLP DOI BibTeX RDF |
ICORE, low power, ASIP, application-specific instruction set processor, low energy, LISA |
68 | Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll |
Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
eFPGA, Parametrisable architecture, Arithmetic oriented, Processor-eFPGA coupling, ASIP |
63 | Maziar Goudarzi, Shaahin Hessabi |
The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models. |
SAMOS |
2005 |
DBLP DOI BibTeX RDF |
|
62 | David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rudolf Mathar |
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. |
CHES |
2009 |
DBLP DOI BibTeX RDF |
Barreto-Naehrig curves, elliptic-curve cryptography (ECC), design-space exploration, Application-specific instruction-set processor (ASIP), arithmetic, pairing-based cryptography |
62 | Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
ASIP architecture exploration for efficient IPSec encryption: A case study. |
ACM Trans. Embed. Comput. Syst. |
2007 |
DBLP DOI BibTeX RDF |
computer-aided design, ADL, ASIP, IPSec |
62 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
An efficient technique for exploring register file size in ASIP synthesis. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis |
57 | Li Zhang, Shuangfei Li, Zan Yin, Wenyuan Zhao |
A Research on an ASIP Processing Element Architecture Suitable for FPGA Implementation. |
CSSE (3) |
2008 |
DBLP DOI BibTeX RDF |
|
57 | Koen Van Renterghem, Pieter Demuytere, Dieter Verhulst, Jan Vandewege, Xing-Zhi Qiu |
Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Hai Lin 0004, Yunsi Fei |
A novel multi-objective instruction synthesis flow for application-specific instruction set processors. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
instruction set synthesis, application-specific instruction set processor (ASIP) |
50 | Per Karlström, Dake Liu |
NoGAP: A Micro Architecture Construction Framework. |
SAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
50 | Muhammad Ali Babar 0001, Barbara A. Kitchenham, Piyush Maheshwari |
The Value of Architecturally Significant Information Extracted from Patterns for Architecture Evaluation: A Controlled Experiment. |
ASWEC |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Götz Kappen, Tobias G. Noll |
Application specific instruction processor based implementation of a GNSS receiver on an FPGA. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Seiichiro Hiratsuka, Satoshi Goto, Takeshi Ikenaga |
An ultra-low complexity motion estimation algorithm and its implementation of specific processor. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Nikolaos Vassiliadis, A. Chormoviti, Nikolaos Kavvadias, Spiridon Nikolaidis 0001 |
The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
50 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran |
Dual-pipeline heterogeneous ASIP design. |
CODES+ISSS |
2004 |
DBLP DOI BibTeX RDF |
dual-pipeline, instruction set generation, ASIP, superscalar |
50 | Hideaki Yanagisawa, Minoru Uehara, Hideki Mori |
Development Methodology of ASIP Based on Java Byte Code Using HW/SW Co-Design System for Processor Design. |
ICDCS Workshops |
2004 |
DBLP DOI BibTeX RDF |
HW/SW Codesign system, C-DASH, ASIP, Java processor, ISA |
50 | Min Jiang, Bing Yang, Xinan Wang, Tianyi Zhang |
SW/HW Co-design of a Java-based ASIP for Pervasive Computing in Mobile Applications. |
DELTA |
2004 |
DBLP DOI BibTeX RDF |
SWHW Co-design, Java-based ASIP(JASIP), Pervasive Computing, Mobile Multimedia |
50 | Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr |
A novel approach for flexible and consistent ADL-driven ASIP design. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
ADL, embedded processors, ASIP |
50 | Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar |
Exploring the Number of Register Windows in ASIP Synthesis. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Regular language recognition, Processor and memory configuration, ASIP Synthesis, Context switch, Register windows |
45 | Timo Vogt, Norbert Wehn |
A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Kang Zhao, Jinian Bian, Sheqin Dong |
A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. |
CSCWD |
2007 |
DBLP DOI BibTeX RDF |
|
45 | Götz Kappen, S. el Bahri, O. Priebe, Tobias G. Noll |
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
45 | Olivier Muller, Amer Baghdadi, Michel Jézéquel |
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr |
ASIP design and synthesis for non linear filtering in image processing. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Koen Van Renterghem, Dieter Verhulst, S. Verschuere, Pieter Demuytere, Jan Vandewege, Xing-Zhi Qiu |
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Leonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos |
Automatic ADL-Based Assembler Generation for ASIP Programming Support. |
SAMOS |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Masaharu Imai, Akira Kitajima |
Verification Challenges in Configurable Processor Design with ASIP Meister. |
CHARME |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
Integrated On-Chip Storage Evaluation in ASIP Synthesis. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. |
SCOPES |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan |
Evaluating register file size in ASIP design. |
CODES |
2001 |
DBLP DOI BibTeX RDF |
instruction power model, synthesis, application specific instruction set processor, instruction set, register file, register spill |
45 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
ASIP Design Methodologies : Survey and Issues. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
45 | Andreas Pyttel, Alexander Sedlmeier, Christian Veith |
PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
FPGA, modular, statechart, application-specific |
45 | Luigi Raffo, Silvio P. Sabatini, Mauro Mantelli, Alessandro De Gloria, Giacomo M. Bisio |
Design of an ASIP architecture for low-level visual elaborations. |
IEEE Trans. Very Large Scale Integr. Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
45 | Clifford Liem, Trevor C. May, Pierre G. Paulin |
Register assignment through resource classification for ASIP microcode generation. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
43 | Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. |
ACM Trans. Embed. Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
coarse-grained FPGA, VLIW, ASIP |
43 | Hai Lin 0004, Yunsi Fei |
Utilizing custom registers in application-specific instruction set processors for register spills elimination. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
custom register, ASIP, register file |
39 | Wan Qiao, Dake Liu, Shaohan Liu |
QFEC ASIP: A Flexible Quad-Mode FEC ASIP for Polar, LDPC, Turbo, and Convolutional Code Decoding. |
IEEE Access |
2018 |
DBLP DOI BibTeX RDF |
|
39 | Agus Bejo, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda |
A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach. |
J. Inf. Process. |
2014 |
DBLP DOI BibTeX RDF |
|
39 | Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner 0001 |
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context. |
ISVLSI |
2013 |
DBLP DOI BibTeX RDF |
|
38 | Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre |
A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration. |
J. VLSI Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
data grouping and reuse, optimization, parallelism, application-specific instruction-set processor, design exploration |
38 | Svetislav Momcilovic, Tiago Dias 0001, Nuno Roma, Leonel Sousa |
Application Specific Instruction Set Processor for Adaptive Video Motion Estimation. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Integrated Verification Approach during ADL-Driven Processor Design. |
IEEE International Workshop on Rapid System Prototyping |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Ramesh Chidambaram, Rene van Leuken 0001, Marc Quax, Ingolf Held, Jos Huisken |
A multistandard FFT processor for wireless system-on-chip implementations. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre |
Application specific instruction-set processor generation for video processing based on loop optimization. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan |
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
38 | David Goodwin, Darin Petkov |
Automatic generation of application specific processors. |
CASES |
2003 |
DBLP DOI BibTeX RDF |
automatic instruction-set generation, ASIPs, configurable processors, extensible processors |
38 | Jens Wagner, Rainer Leupers |
C compiler design for a network processor. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Andreas Hoffmann 0002, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr |
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Jens Wagner, Rainer Leupers |
C Compiler Design for an Industrial Network Processor. |
LCTES/OM |
2001 |
DBLP DOI BibTeX RDF |
compilers, network processors, embedded processors |
37 | Nidhi Arora, Kiran Chandramohan, Nagaraju Pothineni, Anshul Kumar |
Instruction Selection in ASIP Synthesis Using Functional Matching. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Functional Matching, ASIP, Covering, Confluence, Structural Matching |
37 | Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa López-Vallejo, Pedro M. Crespo, Vicente Atxa, Jon Altuna |
Joint Source-Channel Decoding ASIP Architecture for Sensor Networks. |
ICESS |
2007 |
DBLP DOI BibTeX RDF |
DSC, Sensor Networks, VLIW, ASIP, Turbo Codes, Joint Source-Channel Coding, Factor Graphs |
37 | T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua |
Compiler-directed customization of ASIP cores. |
CODES |
2002 |
DBLP DOI BibTeX RDF |
soft cores, embedded, customization, ASIP |
37 | Kurt Keutzer, Sharad Malik, A. Richard Newton |
From ASIC to ASIP: The Next Design Discontinuity. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
Programmable platforms, Design methodology, Application Specific Integrated Circuits, ASIC, Application Specific Instruction Set Processors, ASIP |
32 | Sung Dae Kim, Myung Hoon Sunwoo |
ASIP Approach for Implementation of H.264/AVC. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
low power design, H.264/AVC, hardware accelerator, application specific instruction-set processor, data reuse, hardware software codesign |
32 | Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor |
Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals. |
SAMOS |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Jin Ho Ha, Jin Soo Kim, Myung Hoon Sunwoo |
AN ASIP Approach for H.264/AVC Implementation Having Novel Coprocessors. |
SiPS |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Philip Brisk, Ajay Kumar Verma, Paolo Ienne |
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Sung Dae Kim, Myung Hoon Sunwoo |
Low Power ASIP Architecture Optimization based on Target Application Profiling. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
32 | David Montgomery, Ali Akoglu |
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Daniele Lo Iacono, J. Zory, Ettore Messina, Nicolo Piazzese, G. Saia, A. Bettinelli |
ASIP architecture for multi-standard wireless terminals. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Zheng Shen, Hu He 0001, Yanjun Zhang, Yihe Sun |
VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design. |
IIH-MSP |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel |
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Yun Zhu, Xi Li 0003, Yuchang Gong, Zhi-Gang Wang |
PN-based Formal Modeling and Verification for ASIP Architecture. |
ICESS |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Newton Cheung, Jörg Henkel, Sri Parameswaran |
Rapid Configuration and Instruction Selection for an ASIP: A Case Study. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
Exploring Storage Organization in ASIP Synthesis. |
DSD |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai |
Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Yann Bajot, Habib Mehrez |
Customizable DSP architecture for ASIP core design. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | William E. Dougherty, David J. Pursley, Donald E. Thomas |
Subsetting Behavioral Intellectual Property for Low Power ASIP Design. |
J. VLSI Signal Process. |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Jianjun Guo, Kui Dai, Zhiying Wang 0003 |
A High Performance Heterogeneous Architecture and Its Optimization Design. |
HPCC |
2006 |
DBLP DOI BibTeX RDF |
SDTA, ASIP, Data Parallel |
30 | Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke |
Automated data cache placement for embedded VLIW ASIPs. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
cache, ASIP, cache optimization, embedded applications |
30 | Seng Lin Shee, Sri Parameswaran, Newton Cheung |
Novel architecture for loop acceleration: a case study. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
tightly coupled, architecture, ASIP, hardware/software partitioning, coprocessor, loop optimization, latency hiding, loop pipelining, loop acceleration |
30 | Andreas Hoffmann 0002, Frank Fiedler, Achim Nohl, Surender Parupalli |
A Methodology and Tooling Enabling Application Specific Processor Design. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
SIMD, VLIW, ASIP |
30 | Tim Good, Mohammed Benaissa |
AES on FPGA from the Fastest to the Smallest. |
CHES |
2005 |
DBLP DOI BibTeX RDF |
low area, Application Specific Instruction Processor (ASIP), Field Programmable Gate Array (FPGA), pipelined, Advanced Encryption Standard (AES), finite field, high throughput, design exploration |
30 | Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann 0002, Rainer Leupers, Heinrich Meyr |
Application specific compiler/architecture codesign: a case study. |
LCTES-SCOPES |
2002 |
DBLP DOI BibTeX RDF |
ASIP, architecture exploration, retargetable compiler |
30 | M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha |
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
Trimaran, performance, design space exploration, VLIW, ASIP |
30 | T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik |
Processor Evaluation in an Embedded Systems Design Environment. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
ASAP scheduler, Architecture constrained scheduler, ASIP, Processor architecture, Real-time constraints, Application profiling |
30 | Young Geol Kim, Tag Gon Kim |
A Design and Tool Reuse Methodology for Rapid Prototyping of Application Specific Instruction Set Processors. |
IEEE International Workshop on Rapid System Prototyping |
1999 |
DBLP DOI BibTeX RDF |
Rapid prototyping, ASIP, Design reuse, Architecture description, Retargetable simulator |
30 | Stephanie Dogimont, Martin Gumm, Friederich Mombers, Daniel Mlynek, Alessandro Torielli |
Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture. |
ASAP |
1997 |
DBLP DOI BibTeX RDF |
RISC CPU, parallel multimedia architecture, high performance control structure, parallel motion estimation architecture, MPEG2 coding, combined MIMD-SIMD approach, motion estimation, ASIP, subword parallelism, embedded controller |
25 | Hai Lin 0004, Yunsi Fei |
Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
asips, multi-objective design |
25 | Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro |
Dynamically Adapted Low Power ASIPs. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Haris Javaid, Sri Parameswaran |
Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
design space exploration, integer linear programming, MPSoCs |
25 | Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. |
IEEE International Workshop on Rapid System Prototyping |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Seng Lin Shee, Sri Parameswaran |
Design Methodology for Pipelined Heterogeneous Multiprocessor System. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia |
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania |
Fuzzy decision making in embedded system design. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
pareto-set reduction, clustering, decision making, multi-objective optimization |
25 | Jack Whitham, Neil C. Audsley |
Integrating Custom Instruction Specifications into C Development Processes. |
ARC |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Maria Mbaye, D. Lebel, Normand Bélanger, Yvon Savaria, Samuel Pierre |
Design exploration with an application-specific instruction-set processor for ELA deinterlacing. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Harold Ishebabi, Gerd Ascheid, Heinrich Meyr, Oguzhan Atak, Abdullah Atalar, Erdal Arikan |
An efficient parallelization technique for high throughput FFT-ASIPs. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Kang Zhao, Jinian Bian |
A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Harm Peters, Ramanathan Sethuraman, Aleksandar Beric, Patrick Meuwissen, Srinivasan Balakrishnan, Carlos A. Alba Pinto, W. M. Kruijtzer, Fabian Ernst, Ghiath Alkadi, Jef L. van Meerbergen, Gerard de Haan |
Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications. |
IEEE Trans. Circuits Syst. Video Technol. |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Hong Yue, Ming-che Lai, Kui Dai, Zhiying Wang 0003 |
Design of a Configurable Embedded Processor Architecture for DSP Functions. |
ICPADS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu |
A power-driven multiplication instruction-set design method for ASIPs. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Bruce R. Childers, Jack W. Davidson |
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
Counterflow pipelines, automatic architectural synthesis, application-specific processors |
25 | Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren 0001 |
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
Multi-objective Optimization of a Parameterized VLIW Architecture. |
Evolvable Hardware |
2004 |
DBLP DOI BibTeX RDF |
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