The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Searching for ASIP with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1993-1997 (15) 1998-2000 (24) 2001-2002 (20) 2003-2004 (36) 2005 (29) 2006 (37) 2007 (32) 2008 (31) 2009 (23) 2010-2011 (31) 2012 (18) 2013 (18) 2014 (17) 2015 (16) 2016-2017 (20) 2018-2021 (15) 2022-2024 (9)
Publication types (Num. hits)
article(91) book(1) incollection(2) inproceedings(293) phdthesis(4)
Venues (Conferences, Journals, ...)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
The graphs summarize 322 occurrences of 165 keywords

Results
Found 391 publication records. Showing 391 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
88Naser MohammadZadeh, Morteza NajafVand, Shaahin Hessabi, Maziar Goudarzi Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF ODYSSEY, embedded systems, ASIP, JPEG
83Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael De Nil, Jef L. van Meerbergen Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP. Search on Bibsonomy HiPEAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
83Sung Dae Kim, Jeong Hoo Lee, Chung Jin Hyun, Myung Hoon Sunwoo ASIP approach for implementation of H.264/AVC. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
75Thorsten von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll ASIP-eFPGA Architecture for Multioperable GNSS Receivers. Search on Bibsonomy SAMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF arithmetic oriented eFPGA, multioperable GNSS, ASIP
75Quang Dinh, Deming Chen, Martin D. F. Wong Efficient ASIP design for configurable processors with fine-grained resource sharing. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF multi-cycle IO, compilation, ASIP, resource sharing, configurable processor
75Tilman Glökler, Andreas Hoffmann 0002, Heinrich Meyr Methodical Low-Power ASIP Design Space Exploration. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF ICORE, low power, ASIP, application-specific instruction set processor, low energy, LISA
68Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF eFPGA, Parametrisable architecture, Arithmetic oriented, Processor-eFPGA coupling, ASIP
63Maziar Goudarzi, Shaahin Hessabi The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models. Search on Bibsonomy SAMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
62David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rudolf Mathar Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. Search on Bibsonomy CHES The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Barreto-Naehrig curves, elliptic-curve cryptography (ECC), design-space exploration, Application-specific instruction-set processor (ASIP), arithmetic, pairing-based cryptography
62Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr ASIP architecture exploration for efficient IPSec encryption: A case study. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF computer-aided design, ADL, ASIP, IPSec
62Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar An efficient technique for exploring register file size in ASIP synthesis. Search on Bibsonomy CASES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis
57Li Zhang, Shuangfei Li, Zan Yin, Wenyuan Zhao A Research on an ASIP Processing Element Architecture Suitable for FPGA Implementation. Search on Bibsonomy CSSE (3) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
57Koen Van Renterghem, Pieter Demuytere, Dieter Verhulst, Jan Vandewege, Xing-Zhi Qiu Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
55Hai Lin 0004, Yunsi Fei A novel multi-objective instruction synthesis flow for application-specific instruction set processors. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF instruction set synthesis, application-specific instruction set processor (ASIP)
50Per Karlström, Dake Liu NoGAP: A Micro Architecture Construction Framework. Search on Bibsonomy SAMOS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
50Muhammad Ali Babar 0001, Barbara A. Kitchenham, Piyush Maheshwari The Value of Architecturally Significant Information Extracted from Patterns for Architecture Evaluation: A Controlled Experiment. Search on Bibsonomy ASWEC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
50Götz Kappen, Tobias G. Noll Application specific instruction processor based implementation of a GNSS receiver on an FPGA. Search on Bibsonomy DATE Designers' Forum The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
50Seiichiro Hiratsuka, Satoshi Goto, Takeshi Ikenaga An ultra-low complexity motion estimation algorithm and its implementation of specific processor. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
50Nikolaos Vassiliadis, A. Chormoviti, Nikolaos Kavvadias, Spiridon Nikolaidis 0001 The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms. Search on Bibsonomy PATMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
50Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran Dual-pipeline heterogeneous ASIP design. Search on Bibsonomy CODES+ISSS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF dual-pipeline, instruction set generation, ASIP, superscalar
50Hideaki Yanagisawa, Minoru Uehara, Hideki Mori Development Methodology of ASIP Based on Java Byte Code Using HW/SW Co-Design System for Processor Design. Search on Bibsonomy ICDCS Workshops The full citation details ... 2004 DBLP  DOI  BibTeX  RDF HW/SW Codesign system, C-DASH, ASIP, Java processor, ISA
50Min Jiang, Bing Yang, Xinan Wang, Tianyi Zhang SW/HW Co-design of a Java-based ASIP for Pervasive Computing in Mobile Applications. Search on Bibsonomy DELTA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF SWHW Co-design, Java-based ASIP(JASIP), Pervasive Computing, Mobile Multimedia
50Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr A novel approach for flexible and consistent ADL-driven ASIP design. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF ADL, embedded processors, ASIP
50Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar Exploring the Number of Register Windows in ASIP Synthesis. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Regular language recognition, Processor and memory configuration, ASIP Synthesis, Context switch, Register windows
45Timo Vogt, Norbert Wehn A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
45Kang Zhao, Jinian Bian, Sheqin Dong A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. Search on Bibsonomy CSCWD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Götz Kappen, S. el Bahri, O. Priebe, Tobias G. Noll Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers. Search on Bibsonomy ASAP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Olivier Muller, Amer Baghdadi, Michel Jézéquel ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr ASIP design and synthesis for non linear filtering in image processing. Search on Bibsonomy DATE Designers' Forum The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Koen Van Renterghem, Dieter Verhulst, S. Verschuere, Pieter Demuytere, Jan Vandewege, Xing-Zhi Qiu A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Leonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos Automatic ADL-Based Assembler Generation for ASIP Programming Support. Search on Bibsonomy SAMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Masaharu Imai, Akira Kitajima Verification Challenges in Configurable Processor Design with ASIP Meister. Search on Bibsonomy CHARME The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar Integrated On-Chip Storage Evaluation in ASIP Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. Search on Bibsonomy SCOPES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
45Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan Evaluating register file size in ASIP design. Search on Bibsonomy CODES The full citation details ... 2001 DBLP  DOI  BibTeX  RDF instruction power model, synthesis, application specific instruction set processor, instruction set, register file, register spill
45Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar ASIP Design Methodologies : Survey and Issues. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
45Andreas Pyttel, Alexander Sedlmeier, Christian Veith PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF FPGA, modular, statechart, application-specific
45Luigi Raffo, Silvio P. Sabatini, Mauro Mantelli, Alessandro De Gloria, Giacomo M. Bisio Design of an ASIP architecture for low-level visual elaborations. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
45Clifford Liem, Trevor C. May, Pierre G. Paulin Register assignment through resource classification for ASIP microcode generation. Search on Bibsonomy ICCAD The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
43Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF coarse-grained FPGA, VLIW, ASIP
43Hai Lin 0004, Yunsi Fei Utilizing custom registers in application-specific instruction set processors for register spills elimination. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF custom register, ASIP, register file
39Wan Qiao, Dake Liu, Shaohan Liu QFEC ASIP: A Flexible Quad-Mode FEC ASIP for Polar, LDPC, Turbo, and Convolutional Code Decoding. Search on Bibsonomy IEEE Access The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
39Agus Bejo, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach. Search on Bibsonomy J. Inf. Process. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
39Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner 0001 A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context. Search on Bibsonomy ISVLSI The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
38Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF data grouping and reuse, optimization, parallelism, application-specific instruction-set processor, design exploration
38Svetislav Momcilovic, Tiago Dias 0001, Nuno Roma, Leonel Sousa Application Specific Instruction Set Processor for Adaptive Video Motion Estimation. Search on Bibsonomy DSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr Integrated Verification Approach during ADL-Driven Processor Design. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Ramesh Chidambaram, Rene van Leuken 0001, Marc Quax, Ingolf Held, Jos Huisken A multistandard FFT processor for wireless system-on-chip implementations. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre Application specific instruction-set processor generation for video processing based on loop optimization. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
38David Goodwin, Darin Petkov Automatic generation of application specific processors. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF automatic instruction-set generation, ASIPs, configurable processors, extensible processors
38Jens Wagner, Rainer Leupers C compiler design for a network processor. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
38Andreas Hoffmann 0002, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
38Jens Wagner, Rainer Leupers C Compiler Design for an Industrial Network Processor. Search on Bibsonomy LCTES/OM The full citation details ... 2001 DBLP  DOI  BibTeX  RDF compilers, network processors, embedded processors
37Nidhi Arora, Kiran Chandramohan, Nagaraju Pothineni, Anshul Kumar Instruction Selection in ASIP Synthesis Using Functional Matching. Search on Bibsonomy VLSI Design The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Functional Matching, ASIP, Covering, Confluence, Structural Matching
37Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa López-Vallejo, Pedro M. Crespo, Vicente Atxa, Jon Altuna Joint Source-Channel Decoding ASIP Architecture for Sensor Networks. Search on Bibsonomy ICESS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF DSC, Sensor Networks, VLIW, ASIP, Turbo Codes, Joint Source-Channel Coding, Factor Graphs
37T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua Compiler-directed customization of ASIP cores. Search on Bibsonomy CODES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF soft cores, embedded, customization, ASIP
37Kurt Keutzer, Sharad Malik, A. Richard Newton From ASIC to ASIP: The Next Design Discontinuity. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Programmable platforms, Design methodology, Application Specific Integrated Circuits, ASIC, Application Specific Instruction Set Processors, ASIP
32Sung Dae Kim, Myung Hoon Sunwoo ASIP Approach for Implementation of H.264/AVC. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF low power design, H.264/AVC, hardware accelerator, application specific instruction-set processor, data reuse, hardware software codesign
32Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals. Search on Bibsonomy SAMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Jin Ho Ha, Jin Soo Kim, Myung Hoon Sunwoo AN ASIP Approach for H.264/AVC Implementation Having Novel Coprocessors. Search on Bibsonomy SiPS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Philip Brisk, Ajay Kumar Verma, Paolo Ienne Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Sung Dae Kim, Myung Hoon Sunwoo Low Power ASIP Architecture Optimization based on Target Application Profiling. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32David Montgomery, Ali Akoglu Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications. Search on Bibsonomy ASAP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Daniele Lo Iacono, J. Zory, Ettore Messina, Nicolo Piazzese, G. Saia, A. Bettinelli ASIP architecture for multi-standard wireless terminals. Search on Bibsonomy DATE Designers' Forum The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Zheng Shen, Hu He 0001, Yanjun Zhang, Yihe Sun VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design. Search on Bibsonomy IIH-MSP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
32Yun Zhu, Xi Li 0003, Yuchang Gong, Zhi-Gang Wang PN-based Formal Modeling and Verification for ASIP Architecture. Search on Bibsonomy ICESS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Newton Cheung, Jörg Henkel, Sri Parameswaran Rapid Configuration and Instruction Selection for an ASIP: A Case Study. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
32Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar Exploring Storage Organization in ASIP Synthesis. Search on Bibsonomy DSD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
32Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32Yann Bajot, Habib Mehrez Customizable DSP architecture for ASIP core design. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32William E. Dougherty, David J. Pursley, Donald E. Thomas Subsetting Behavioral Intellectual Property for Low Power ASIP Design. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
30Jianjun Guo, Kui Dai, Zhiying Wang 0003 A High Performance Heterogeneous Architecture and Its Optimization Design. Search on Bibsonomy HPCC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF SDTA, ASIP, Data Parallel
30Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke Automated data cache placement for embedded VLIW ASIPs. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF cache, ASIP, cache optimization, embedded applications
30Seng Lin Shee, Sri Parameswaran, Newton Cheung Novel architecture for loop acceleration: a case study. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF tightly coupled, architecture, ASIP, hardware/software partitioning, coprocessor, loop optimization, latency hiding, loop pipelining, loop acceleration
30Andreas Hoffmann 0002, Frank Fiedler, Achim Nohl, Surender Parupalli A Methodology and Tooling Enabling Application Specific Processor Design. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF SIMD, VLIW, ASIP
30Tim Good, Mohammed Benaissa AES on FPGA from the Fastest to the Smallest. Search on Bibsonomy CHES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF low area, Application Specific Instruction Processor (ASIP), Field Programmable Gate Array (FPGA), pipelined, Advanced Encryption Standard (AES), finite field, high throughput, design exploration
30Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann 0002, Rainer Leupers, Heinrich Meyr Application specific compiler/architecture codesign: a case study. Search on Bibsonomy LCTES-SCOPES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF ASIP, architecture exploration, retargetable compiler
30M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Trimaran, performance, design space exploration, VLIW, ASIP
30T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik Processor Evaluation in an Embedded Systems Design Environment. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF ASAP scheduler, Architecture constrained scheduler, ASIP, Processor architecture, Real-time constraints, Application profiling
30Young Geol Kim, Tag Gon Kim A Design and Tool Reuse Methodology for Rapid Prototyping of Application Specific Instruction Set Processors. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Rapid prototyping, ASIP, Design reuse, Architecture description, Retargetable simulator
30Stephanie Dogimont, Martin Gumm, Friederich Mombers, Daniel Mlynek, Alessandro Torielli Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture. Search on Bibsonomy ASAP The full citation details ... 1997 DBLP  DOI  BibTeX  RDF RISC CPU, parallel multimedia architecture, high performance control structure, parallel motion estimation architecture, MPEG2 coding, combined MIMD-SIMD approach, motion estimation, ASIP, subword parallelism, embedded controller
25Hai Lin 0004, Yunsi Fei Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF asips, multi-objective design
25Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro Dynamically Adapted Low Power ASIPs. Search on Bibsonomy ARC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
25Haris Javaid, Sri Parameswaran Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study. Search on Bibsonomy CODES+ISSS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF design space exploration, integer linear programming, MPSoCs
25Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
25Seng Lin Shee, Sri Parameswaran Design Methodology for Pipelined Heterogeneous Multiprocessor System. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
25Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. Search on Bibsonomy DATE Designers' Forum The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania Fuzzy decision making in embedded system design. Search on Bibsonomy CODES+ISSS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF pareto-set reduction, clustering, decision making, multi-objective optimization
25Jack Whitham, Neil C. Audsley Integrating Custom Instruction Specifications into C Development Processes. Search on Bibsonomy ARC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Maria Mbaye, D. Lebel, Normand Bélanger, Yvon Savaria, Samuel Pierre Design exploration with an application-specific instruction-set processor for ELA deinterlacing. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Harold Ishebabi, Gerd Ascheid, Heinrich Meyr, Oguzhan Atak, Abdullah Atalar, Erdal Arikan An efficient parallelization technique for high throughput FFT-ASIPs. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Kang Zhao, Jinian Bian A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Harm Peters, Ramanathan Sethuraman, Aleksandar Beric, Patrick Meuwissen, Srinivasan Balakrishnan, Carlos A. Alba Pinto, W. M. Kruijtzer, Fabian Ernst, Ghiath Alkadi, Jef L. van Meerbergen, Gerard de Haan Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Technol. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Hong Yue, Ming-che Lai, Kui Dai, Zhiying Wang 0003 Design of a Configurable Embedded Processor Architecture for DSP Functions. Search on Bibsonomy ICPADS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu A power-driven multiplication instruction-set design method for ASIPs. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Bruce R. Childers, Jack W. Davidson Custom Wide Counterflow Pipelines for High-Performance Embedded Applications. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Counterflow pipelines, automatic architectural synthesis, application-specific processors
25Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren 0001 A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti Multi-objective Optimization of a Parameterized VLIW Architecture. Search on Bibsonomy Evolvable Hardware The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
Displaying result #1 - #100 of 391 (100 per page; Change: )
Pages: [1][2][3][4][>>]
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by L3S.
Previously maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.
open data data released under the ODC-BY 1.0 license