Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
78 | David Goodwin, Darin Petkov |
Automatic generation of application specific processors. |
CASES |
2003 |
DBLP DOI BibTeX RDF |
automatic instruction-set generation, ASIPs, configurable processors, extensible processors |
69 | Sung Dae Kim, Myung Hoon Sunwoo |
Low Power ASIP Architecture Optimization based on Target Application Profiling. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
62 | Muhammad Rashid, Ludovic Apvrille, Renaud Pacalet |
Evaluation of ASIPs Design with LISATek. |
SAMOS |
2008 |
DBLP DOI BibTeX RDF |
LISATek, ASIPs, JPEG, Customized Instructions |
52 | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu |
A power-driven multiplication instruction-set design method for ASIPs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran, Aleksandar Ignjatovic |
Application specific forwarding network and instruction encoding for multi-pipe ASIPs. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
multi-pipe ASIP, VLIW, forwarding, instruction encoding |
52 | M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha |
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
Trimaran, performance, design space exploration, VLIW, ASIP |
41 | Ya-Shuai Lü, Li Shen 0007, Zhiying Wang 0003, Nong Xiao |
Dynamically utilizing computation accelerators for extensible processors in a software approach. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
computation accelerator, ASIP, dynamic binary translation |
41 | Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. |
ACM Trans. Embed. Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
coarse-grained FPGA, VLIW, ASIP |
41 | Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. |
IEEE International Workshop on Rapid System Prototyping |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Miao Wang, Guiming Wu, Zhiying Wang 0003 |
Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors. |
ISPA |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Mehdi Modarressi, Shaahin Hessabi, Maziar Goudarzi |
A Reconfigurable Cache Architecture for Object-Oriented Embedded Systems. |
CCECE |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre |
Application specific instruction-set processor generation for video processing based on loop optimization. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Bruce R. Childers, Jack W. Davidson |
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
Counterflow pipelines, automatic architectural synthesis, application-specific processors |
41 | Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato |
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Bruce R. Childers, Jack W. Davidson |
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications. |
IEEE PACT |
2000 |
DBLP DOI BibTeX RDF |
|
41 | Clifford Liem, Trevor C. May, Pierre G. Paulin |
Register assignment through resource classification for ASIP microcode generation. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
39 | Harold Ishebabi, Gerd Ascheid, Heinrich Meyr, Oguzhan Atak, Abdullah Atalar, Erdal Arikan |
An efficient parallelization technique for high throughput FFT-ASIPs. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Satish Pillai, Margarida F. Jacome |
Symbolic Binding for Clustered VLIW ASIPs. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
39 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
|
39 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Hierarchical test generation and design for testability methods for ASPPs and ASIPs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
39 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
39 | Luigi Carro, G. A. Pereira, C. Alba, Altamiro Amadeu Susin |
System Design using ASIPs. |
ECBS |
1996 |
DBLP DOI BibTeX RDF |
|
37 | Hai Lin 0004, Yunsi Fei |
Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
asips, multi-objective design |
37 | Rafael Peset Llopis, Ramanathan Sethuraman, Carlos A. Alba Pinto, Harm Peters, Steffen Maul, Marcel Oosterhuis |
A low-cost and low-power multi-standard video encoder. |
CODES+ISSS |
2003 |
DBLP DOI BibTeX RDF |
multi-standard, low-power, ASIPs, hardware/software partitioning, low-cost, video encoder |
27 | Lars Bauer, Muhammad Shafique 0001, Jörg Henkel |
Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Carlo Galuzzi, Koen Bertels |
The Instruction-Set Extension Problem: A Survey. |
ARC |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Muhammad Rashid, Ludovic Apvrille, Renaud Pacalet |
Application Specific Processors for Multimedia Applications. |
CSE |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Steve Leibson, Grant Martin |
Design and verification of complex SoC with configurable, extensible processors. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre |
Loop-oriented metrics for exploring an application-specific architecture design-space. |
ASAP |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Yee Jern Chong, Sri Parameswaran |
Automatic application specific floating-point unit generation. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Hai Lin 0004, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi |
Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Seng Lin Shee, Sri Parameswaran |
Design Methodology for Pipelined Heterogeneous Multiprocessor System. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, Manas Pandey |
A design flow for configurable embedded processors based on optimized instruction set extension synthesis. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Harm Peters, Ramanathan Sethuraman, Aleksandar Beric, Patrick Meuwissen, Srinivasan Balakrishnan, Carlos A. Alba Pinto, W. M. Kruijtzer, Fabian Ernst, Ghiath Alkadi, Jef L. van Meerbergen, Gerard de Haan |
Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications. |
IEEE Trans. Circuits Syst. Video Technol. |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Leonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos |
Automatic ADL-Based Assembler Generation for ASIP Programming Support. |
SAMOS |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia |
Micro embedded monitoring for security in application specific instruction-set processors. |
CASES |
2005 |
DBLP DOI BibTeX RDF |
micro embedded monitoring, microinstructions, self-monitoring instructions, application specific instruction-set processors, security monitoring |
27 | Bita Gorjiara, Daniel D. Gajski |
Custom Processor Design Using NISC: A Case-Study on DCT algorithm. |
ESTIMedia |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski |
Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Tilman Glökler, Andreas Hoffmann 0002, Heinrich Meyr |
Methodical Low-Power ASIP Design Space Exploration. |
J. VLSI Signal Process. |
2003 |
DBLP DOI BibTeX RDF |
ICORE, low power, ASIP, application-specific instruction set processor, low energy, LISA |
27 | Chidamber Kulkarni, Matthias Gries, Christian Sauer 0001, Kurt Keutzer |
Programming challenges in network processor deployment. |
CASES |
2003 |
DBLP DOI BibTeX RDF |
IPv4 forwarding, programming heterogeneous architectures, mapping, programming model, multi-threading, resource sharing |
27 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Energy-efficient instruction set synthesis for application-specific processors. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
low power, customization, application-specific instruction set processor (ASIP), instruction encoding, energy-delay product |
27 | Jeonghun Cho, Yunheung Paek, David B. Whalley |
Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms. |
LCTES-SCOPES |
2002 |
DBLP DOI BibTeX RDF |
dual memory, memory assignment, non-orthogonal architecture, compiler, graph coloring, maximum spanning tree |
27 | T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua |
Compiler-directed customization of ASIP cores. |
CODES |
2002 |
DBLP DOI BibTeX RDF |
soft cores, embedded, customization, ASIP |
27 | Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh |
Design Tools for Application Specific Embedded Processors. |
EMSOFT |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Margarida F. Jacome, Gustavo de Veciana |
Lower bound on latency for VLIW ASIP datapaths. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Shubhankar Suman Singh, Smruti R. Sarangi |
ISAMod: A Tool for Designing ASIPs by Comparing Different ISAs. |
VLSID |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Vikkitharan Gnanasambandapillai, Jorgen Peddersen, Roshan G. Ragel, Sri Parameswaran |
FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Shahriar Shahabuddin, Olli Silvén, Markku J. Juntti |
Programmable ASIPs for Multimode MIMO Transceiver. |
J. Signal Process. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv |
Generating ASIPs with Reduced Number of Connections to the Register-File. |
Int. J. Parallel Program. |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Paolo Meloni, Claudio Rubattu, Giuseppe Tuveri, Danilo Pani, Luigi Raffo, Francesca Palumbo |
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs. |
J. Syst. Archit. |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Roberto Urban, Heinrich Theodor Vierhaus, Mario Schölzel, Enrico Altmann, Horst Seelig |
Non-Cyclic Design Space Exploration for ASIPs - Compiler-Centered Microprocessor Design (CoMet). |
J. Circuits Syst. Comput. |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Jakub Podivinsky, Marcela Simková, Ondrej Cekan, Zdenek Kotásek |
FPGA Prototyping and Accelerated Verification of ASIPs. |
DDECS |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv |
Generating ASIPs with reduced number of connections to the register-file. |
SAMOS |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Erkan Diken, Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal, Felipe Augusto Chies |
Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths. |
Microprocess. Microsystems |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Hong Chinh Doan, Haris Javaid, Sri Parameswaran |
Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs. |
DATE |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal |
Automatic complex instruction identification for efficient application mapping onto ASIPs. |
LASCAS |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv |
Using Multi-op Instructions as a Way to Generate ASIPs with Optimized Pipeline Structure. |
FCCM |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Roel Jordans, Lech Józwiak, Henk Corporaal |
Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm. |
MECO |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Erkan Diken, Roel Jordans, Lech Józwiak, Henk Corporaal |
Construction and exploitation of VLIW asips with multiple vector-widths. |
MECO |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal |
A framework for automatic custom instruction identification on multi-issue ASIPs. |
INDIN |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Hsuanchun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda |
Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing. |
J. Inf. Process. |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal |
Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs. |
MECO |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Erkan Diken, Rosilde Corvino, Lech Józwiak |
Rapid and accurate energy estimation of vector processing in VLIW ASIPs. |
MECO |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Majid Nezakatolhoseini, Mohammad Amin Taherkhani |
A Framework For Performance Evaluation Of ASIPS In Network-Based IDS |
CoRR |
2012 |
DBLP BibTeX RDF |
|
25 | Unmesh D. Bordoloi, Bogdan Tanasa, Mehdi Baradaran Tahoori, Petru Eles, Zebo Peng, Syed Zafar Shazli, Samarjit Chakraborty |
Reliability-Aware Instruction Set Customization for ASIPs with Hardened Logic. |
RTCSA |
2012 |
DBLP DOI BibTeX RDF |
|
25 | David Kammler |
Memory architectures for ASIPs. |
|
2012 |
RDF |
|
25 | Lech Józwiak, Menno Lindwer |
Issues and Challenges in Development of Massively-Parallel Heterogeneous MPSoCs Based on Adaptable ASIPs. |
PDP |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Daniel Shapiro, Jonathan Parri, John-Marc Desmarais, Voicu Groza, Miodrag Bolic |
ASIPs for artificial neural networks. |
SACI |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Christian Brehm, Norbert Wehn, Sacha Loitz, Wolfgang Kunz |
Validation of channel decoding ASIPs a case study. |
International Symposium on Rapid System Prototyping |
2011 |
DBLP DOI BibTeX RDF |
|
25 | David Kammler, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, Heinrich Meyr |
Automatic Generation of Memory Interfaces for ASIPs. |
Int. J. Embed. Real Time Commun. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Zdenek Prikryl, Jakub Kroustek, Tomas Hruska, Dusan Kolár |
Fast Translated Simulation of ASIPs. |
MEMICS |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran, Aleksandar Ignjatovic |
HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. |
IET Comput. Digit. Tech. |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro |
Dynamically Adapted Low Power ASIPs. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Naser MohammadZadeh, Shaahin Hessabi, Maziar Goudarzi, Mahdi Malaki |
A Framework for Object-Oriented Embedded System Development Based on OO-ASIPs. |
J. Circuits Syst. Comput. |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Peter Hallschmid, Resve A. Saleh |
Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll |
Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
eFPGA, Parametrisable architecture, Arithmetic oriented, Processor-eFPGA coupling, ASIP |
25 | Vladimír Guzma, Shuvra S. Bhattacharyya, Pertti Kellomäki, Jarmo Takala |
Trade-offs in mapping high-level dataflow graphs onto ASIPs. |
SoC |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Gert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet |
Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite. |
SoC |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Mile K. Stojcev |
Design of Energy-Efficient Application-Specific Instruction Set Processors (ASIPs), Tilman Glokler, Heinrich Meyr, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7730-0, Hardcover, pp 234, plus XX. |
Microelectron. Reliab. |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Vijayakumar Kalyanaraman, Matthias Müller 0002, Sven Simon 0001, Mario Steinert, Holger Gryska |
A power dissipation comparison of ALU-architectures for ASIPs. |
ECCTD |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Vijayakumar Kalyanaraman, Matthias Müller 0002, Sven Simon 0001, Mario Steinert, Holger Gryska |
Power reduction of ASIPs by distributing the workload on several ASIP-instances. |
ECCTD |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke |
Automated data cache placement for embedded VLIW ASIPs. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
cache, ASIP, cache optimization, embedded applications |
25 | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu |
A power-driven multiplication instruction-set design method for ASIPs. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft |
Object-Oriented Embedded System Development Based on Synthesis and Reuse of OO-ASIPs. |
J. Univers. Comput. Sci. |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Wilson D. Pace, Elizabeth W. Staton, Gregory S. Higgins, Deborah S. Main, David R. West, Daniel M. Harris |
Application of Information Technology: Database Design to Ensure Anonymous Study of Medical Errors: A Report from the ASIPS collaborative. |
J. Am. Medical Informatics Assoc. |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Dirk Fischer 0001, Jürgen Teich, Ralph Weper, Michael Thies |
BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs. |
J. Circuits Syst. Comput. |
2003 |
DBLP DOI BibTeX RDF |
|
25 | R. Govindarajan, Erik R. Altman, Guang R. Gao |
A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors. |
Des. Autom. Embed. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Efficient instruction encoding for automatic instruction set design of configurable ASIPs. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Dirk Fischer 0001, Jürgen Teich, Michael Thies, Ralph Weper |
Efficient architecture/compiler co-exploration for ASIPs. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
architecture/compiler codesign, multiobjective design space exploration, ASIP, retargetable compilation |
25 | Andreas Hoffmann 0002, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr |
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Ashok Sudarsanam, Sharad Malik |
Simultaneous reference allocation in code generation for dual data memory bank ASIPs. |
ACM Trans. Design Autom. Electr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
memory bank assignment, code generation, register allocation, code optimization, graph labelling |
25 | Margarida F. Jacome, Gustavo de Veciana, Viktor S. Lapinskii |
Exploring Performance Tradeoffs for Clustered VLIW ASIPs. |
ICCAD |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Jürgen Teich, Ralph Weper, Dirk Fischer 0001, Stefan Trinkert |
A joined architecture/compiler design environment for ASIPs. |
CASES |
2000 |
DBLP DOI BibTeX RDF |
|
25 | S. Ramanathan, V. Visvanathan, S. K. Nandy 0001 |
Synthesis of ASIPs for DSP algorithms. |
Integr. |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Margarida F. Jacome, Gustavo de Veciana, Cagdas Akturan |
Resource constrained dataflow retiming heuristics for VLIW ASIPs. |
CODES |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi |
A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. |
ASP-DAC |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Masaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi |
A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs. |
EURO-DAC |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi |
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. |
DAC |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Frederick Onion, Alexandru Nicolau, Nikil D. Dutt |
Incorporating compiler feedback into the design of ASIPs. |
ED&TC |
1995 |
DBLP DOI BibTeX RDF |
|
25 | Ashok Sudarsanam, Sharad Malik |
Memory bank and register allocation in software synthesis for ASIPs. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
|