|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 11 occurrences of 11 keywords
|
|
|
Results
Found 5 publication records. Showing 5 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
97 | Wendy Belluomini, Chris J. Myers, H. Peter Hofstee |
Verification of Delayed-Reset Domino Circuits Using ATACS. |
ASYNC |
1999 |
DBLP DOI BibTeX RDF |
|
62 | Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng |
Technology mapping of timed circuits. |
ASYNC |
1995 |
DBLP DOI BibTeX RDF |
gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits |
51 | Teruo Kobayashi, Osamu Iba, Hiroshi Ebine, Shigeharu Aoyagi |
Advanced Train Administration and Communication System based on ADS Technologies. |
ISADS |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Allen E. Sjogren, Chris J. Myers |
Interfacing synchronous and asynchronous modules within a high-speed pipeline. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Allen E. Sjogren, Chris J. Myers |
Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline. |
ARVLSI |
1997 |
DBLP DOI BibTeX RDF |
Mixed synchronous/asynchronous interfacing, stoppable clocks, high-speed pipelines, globally synchronous locally asynchronous, metastability, synchronization failure |
Displaying result #1 - #5 of 5 (100 per page; Change: )
|
|