Search results for "Analog"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
90	Bassem A. Alhalabi, Magdy A. Bayoumi	A scalable analog architecture for neural networks with on-chip learning and refreshing.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	analogue storage, scalable analog architecture, on-chip learning, on-chip refreshing, analog storage, analog functional blocks, analog pass switches, system versatility, learning speed, local analog synaptic updating scheme, unbounded scalability, neural networks, learning (artificial intelligence), neural chips, analogue processing circuits
79	Mike Brunoli, Masao Hotta, Felicia James, Rudy Koch, Roy McGuffin, Andrew J. Moore	Analog intellectual property: now? Or never?	DAC	2002	DBLP DOI BibTeX RDF
79	John Lowell	Computer aided design for analog applications (panel session): an assessment.	DAC	1985	DBLP DOI BibTeX RDF
77	Thelma Estrin	The UCLA Brain Research Institute data processing laboratory.	History of Medical Informatics	1987	DBLP DOI BibTeX RDF
73	Shekhar Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles G. Sodini	Tomorrow's analog: just dead or just different?	DAC	2006	DBLP DOI BibTeX RDF	analog CAD tools, analog design methodologies, mixed-signal design, analog design, RF design
66	Rajesh Ramadoss, Michael L. Bushnell	Test generation for mixed-signal devices using signal flow graphs.	VLSI Design	1996	DBLP DOI BibTeX RDF	mixed-signal devices, reverse simulation approach, component tolerances, analog input sinusoids, test generation results, analog backtrace method, high-order analog circuits, fault diagnosis, test generation, integrated circuit testing, automatic testing, circuit analysis computing, mixed analogue-digital integrated circuits, signal flow graphs, signal flow graphs, nonlinear circuits
65	Janusz Rzeszut, Bozena Kaminska, Yvon Savaria	A new method for testing mixed analog and digital circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	charge-coupled device circuits, mixed analog and digital circuits, analog test points, simultaneous observation, analog multiplexer, signal path, analog shift register, input voltage, integrated circuit testing, shift registers, mixed analogue-digital integrated circuits, charge coupled device, analogue processing circuits
64	Anirudh Devgan, Bulent Basaran, David Colleran, Mar Hershenson	Accelerated design of analog, mixed-signal circuits in Titan.	ISPD	2009	DBLP DOI BibTeX RDF	analog circuit layout, analog/digital, custom design, layout, physical design, analog circuits, mixed-signal circuits
64	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi	Correct-by-construction layout-centric retargeting of large analog designs.	DAC	2004	DBLP DOI BibTeX RDF	analog integrated circuit design, analog layout automation, analog synthesis and optimization, layout symmetry
59	Boris Murmann	Digitally Assisted Analog Circuits.	IEEE Micro	2006	DBLP DOI BibTeX RDF	analog signals, digital computing, analog circuits, analog-to-digital converter
57	Tathagato Rai Dastidar, P. P. Chakrabarti 0001	A verification system for transient response of analog circuits.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Ana CTL, model checking, query language, Analog circuits, equivalence checking, transient response
55	Eric E. Fabris, Luigi Carro, Sergio Bampi	A Universal High-Performance Analog Interface for Signal Processing SOCs.	SBCCI	2003	DBLP DOI BibTeX RDF
54	Salvador Mir, Marcelo Lubaszewski, Bernard Courtois	Unified built-in self-test for fully differential analog circuits.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	on-line/off-line analog test, unified BIST, fully differential analog circuits, common-mode feedback, analog BIST
54	Alexandre R. S. Romariz, P. U. A. Ferreira, J. V. Campêlo Jr., Marcio L. Graciano Jr., José C. da Costa	Design of a Hybrid Digital-Analog Neural Co-Processor for Signal Processing.	EUROMICRO	1996	DBLP DOI BibTeX RDF	hybrid digital-analog neural co-processor, digitally-controlled multiplexing, CMOS analog circuits, VLSI, signal processing, VLSI design, multilayer perceptrons, VLSI implementation, hybrid architecture, capacitors, analog multipliers
54	Rajesh Ramadoss, Michael L. Bushnell	Test Generation for Mixed-Signal Devices Using Signal Flow Graphs.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	analog test generation, mixed-signal test generation, back tracing, parametric faults, catastrophic faults
53	Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy	Survival strategies for mixed-signal systems-on-chip (panel session).	DAC	2000	DBLP DOI BibTeX RDF
52	Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham	A novel test generation approach for parametric faults in linear analog circuits .	VTS	1996	DBLP DOI BibTeX RDF	digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits
51	Jorge Luís Machado do Amaral, José Franco Machado do Amaral, Cristina Costa Santini, Ricardo Tanscheit, Marley M. B. R. Vellasco, Marco Aurélio Cavalcanti Pacheco, Antonio Carneiro de Mesquita Filho	Evolvable Building Blocks for Analog Fuzzy Logic Controllers.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
50	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Low Cost On-Line Testing Strategy for RF Circuits.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	on-line analog testing, DSP-based testing, analog test
49	Saied Hemati, Amir H. Banihashemi	Iterative decoding in analog CMOS.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	analog CMOS, analog iterative decoder, asynchronous iterative decoding, min-sum decoding, soft decoding, analog circuit, turbo codes, iterative decoding, low-density parity-check codes
49	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Ultimate low cost analog BIST.	DAC	2003	DBLP DOI BibTeX RDF	DSP-based analog test, low cost analog BIST, test of analog circuits
49	Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham	Efficient multisine testing of analog circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	waveform analysis, biquadratic filters, multisine testing, test waveform generation, test confidence, fault-based automatic test pattern generator, successive gradient method, sinusoidal signals, fault coverage maximization, biquadratic filter, AC testing, analog IC, fault diagnosis, built-in self test, integrated circuit testing, automatic testing, analog circuits, built-in test, analogue integrated circuits, linear analog circuits
49	Paul Mueller, Jan Van der Spiegel, David Blackman, Timothy Chiu, Thomas Clare, Christopher Donham, Tzu-pu Hsieh, Marc Loinaz	Design and Fabrication of VLSI Components for a General Purpose Analog Neural Computer.	Analog VLSI Implementation of Neural Systems	1989	DBLP DOI BibTeX RDF
49	Steven Bibyk, Mohammed Ismail 0001	Issues in Analog VLSI and MOS Techniques for Neural Computing.	Analog VLSI Implementation of Neural Systems	1989	DBLP DOI BibTeX RDF
49	John G. Harris, Christof Koch, Jin Luo, John L. Wyatt Jr.	Resistive Fuses: Analog Hardware for Detecting Discontinuities in Early Vision.	Analog VLSI Implementation of Neural Systems	1989	DBLP DOI BibTeX RDF
48	Alvernon Walker, Parag K. Lala	A Transition Based BIST Approach for Passive Analog Circuits.	ISQED	2000	DBLP DOI BibTeX RDF	Built-in Self Test, Analog Test, Analog BIST, Mixed-Signal BIST
48	Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng	Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test.	VTS	2000	DBLP DOI BibTeX RDF	cross-correlation signature register, CCSR, implicit functional testing, harmonic distortion, THD, classification, synthesis, noise, BIST, convex hull, polygon, discrimination, analog test, cross-correlation, mixed-signal, pseudo-random, pseudo-random, labview, impulse response, performance parameter, analog BIST
48	Michel Renovell, Florence Azaïs, Yves Bertrand	A design-for-test technique for multistage analog circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	design-for-test technique, multistage analog circuits, DFT approach, op-amp-based modules, testability resources, transparent paths, external I/O, local I/O, test mode, on-chip digital resources, analog response penalty, controllability, controllability, integrated circuit testing, design for testability, observability, observability, mixed-signal circuits, mixed analogue-digital integrated circuits, test management, production testing
48	Anirudh Devgan, Ronald A. Rohrer	Efficient simulation of interconnect and mixed analog-digital circuits in ACES.	VLSI Design	1995	DBLP DOI BibTeX RDF	adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation
47	I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson S. Hall, David V. Anderson	Mapping algorithm for large-scale field programmable analog array.	ISPD	2005	DBLP DOI BibTeX RDF	floating gates, mapping, field programmable analog array
47	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	A Statistical Sampler for a New On-Line Analog Test Method.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	DSP-based testing, on-line testing, analog test
47	Jonathan W. Mills, Matt Parker, Bryce Himebaugh, Craig A. Shue, Brian Kopecky, Chris Weilemann	"Empty space" computes: the evolution of an unconventional supercomputer.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	Lukasiewicz logic, extended analog computer, general purpose analog computer, hybrid digital-analog architecture
46	Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting	Metrology for analog module testing using analog testability bus.	ICCAD	1996	DBLP DOI BibTeX RDF	analog module, analog module testing, multiple instantiation, test response analysis, test waveform, testability bus, design for testability
46	Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty	Test infrastructure design for mixed-signal SOCs with wrapped analog cores.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
46	Anuja Sehgal, Fang Liu 0029, Sule Ozev, Krishnendu Chakrabarty	Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores.	DATE	2005	DBLP DOI BibTeX RDF
46	Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty	A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs.	ICCD	2005	DBLP DOI BibTeX RDF
46	Tathagato Rai Dastidar, P. P. Chakrabarti 0001	A Verification System for Transient Response of Analog Circuits Using Model Checking.	VLSI Design	2005	DBLP DOI BibTeX RDF
45	Yvan Maidon, Thomas Zimmer, André Ivanov	An Analog Circuit Fault Characterization Methodology.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	analog circuit testing, analog fault diagnosis, analog fault characterization
43	Bo Liu 0003, Francisco V. Fernández 0001, Georges G. E. Gielen, Rafael Castro-López, Elisenda Roca	A memetic approach to the automatic design of high-performance analog integrated circuits.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Analog circuit sizing, analog design automation, constrained optimization, memetic algorithm
43	Eric E. Fabris, Luigi Carro, Sergio Bampi	Modeling and designing high performance analog reconfigurable circuits.	SBCCI	2004	DBLP DOI BibTeX RDF	analog programmability, band-pass sigma-delta modulator, analog design, FPAA
43	Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell	TI-BIST: a temperature independent analog BIST for switched-capacitor filters.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	temperature independent analog BIST, simulation, built-in self test, BIST, analogue circuits, switched capacitor filters, switched-capacitor filters, analog BIST
43	Ramakrishna Voorakaranam, Abhijit Chatterjee	Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test.	ARVLSI	1999	DBLP DOI BibTeX RDF	analog verification, fault diagnosis, test generation, analog testing, Backtrace
43	Chanchal Chatterjee, Vwani P. Roychowdhury	An efficient contrast-enhancement method using the analog to digital converter.	Mach. Vis. Appl.	1996	DBLP DOI BibTeX RDF	Analog enhancement, Analog to digital converter
43	Hari Vijay Venkatanarayanan, Michael L. Bushnell	An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip.	VLSI Design	2006	DBLP DOI BibTeX RDF
43	Hamid Reza Ghasemi, Zainalabedin Navabi	An Effective VHDL-AMS Simulation Algorithm with Event Partitioning.	VLSI Design	2005	DBLP DOI BibTeX RDF
42	Eric Soenen	Physical design methodology for analog circuitsin a system-on-a-chip environment.	ISPD	2009	DBLP DOI BibTeX RDF	analog design automation
42	Göran Jerke, Jens Lienig	Constraint-driven design: the next step towards analog design automation.	ISPD	2009	DBLP DOI BibTeX RDF	constraint-driven design, constraints, layout, physical design, analog design
42	Didier Keymeulen, Adrian Stoica, Ricardo Salem Zebulum, Srinivas Katkoori, Pradeep Fernando, Hariharan Sankaran, Mohammad M. Mojarradi, Taher Daud	Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.	ICES	2008	DBLP DOI BibTeX RDF	Self-Healing and Compensation, Self-reconfigurable, Field Programmable Analog Array
42	Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. Ayoubi	Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	non-refreshing static storage, on-chip learning neural networks, analog learning
42	Mehdi Ehsanian, Bozena Kaminska, Karim Arabi	A new digital test approach for analog-to-digital converter testing.	VTS	1996	DBLP DOI BibTeX RDF	digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion
41	Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou	Intrinsic response for analog module testing using an analog testability bus.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	analog testability bus, intrinsic response, design for testability, analog testing, boundary scan
41	Chauchin Su, Yue-Tsang Chen	Crosstalk Effect Removal for Analog Measurement in Analog Test Bus.	VTS	2000	DBLP DOI BibTeX RDF	Analog Test Bus, Design for Testability, Analog Test, Mixed Signal Test
41	Carver Mead	Adaptive Retina.	Analog VLSI Implementation of Neural Systems	1989	DBLP DOI BibTeX RDF
41	Christopher R. Carroll	A Neural Processor for Maze Solving.	Analog VLSI Implementation of Neural Systems	1989	DBLP DOI BibTeX RDF
41	Jan Van der Spiegel, G. Kreider, C. Claeys, I. Debusschere, Giulio Sandini, Paolo Dario, Fausto Fantini, P. Bellutti, Giovanni Soncini	A Foveated Retina-Like Sensor Using CCD Technology.	Analog VLSI Implementation of Neural Systems	1989	DBLP DOI BibTeX RDF
41	John Lazzaro, Carver Mead	Circuit Models of Sensory Transduction in the Cochlea.	Analog VLSI Implementation of Neural Systems	1989	DBLP DOI BibTeX RDF
41	Misha A. Mahowald, Tobi Delbrück	Cooperative Stereo Matching Using Static and Dynamic Image Features.	Analog VLSI Implementation of Neural Systems	1989	DBLP DOI BibTeX RDF
41	Eric A. Vittoz, Xavier Arreguit	CMOS Integration of Herault-Jutten Cells for Separation of Sources.	Analog VLSI Implementation of Neural Systems	1989	DBLP DOI BibTeX RDF
41	Tobi Delbrück	A Chip that Focuses an Image on Itself.	Analog VLSI Implementation of Neural Systems	1989	DBLP DOI BibTeX RDF
41	Haralabos C. Papadopoulos, Carl-Erik W. Sundberg	Precoded Modulo-Precanceling Systems for Simulcasting Analog FM and Digital Data.	IEEE Trans. Commun.	2008	DBLP DOI BibTeX RDF
41	Renée St. Amant, Daniel A. Jiménez, Doug Burger	Low-power, high-performance analog neural branch prediction.	MICRO	2008	DBLP DOI BibTeX RDF
41	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi	Multilevel symmetry-constraint generation for retargeting large analog layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
41	Saied Hemati, Amir H. Banihashemi	Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
41	Ami Litman, Shiri Moran-Schein	Smooth scheduling under variable rates or the analog-digital confinement game.	SPAA	2006	DBLP DOI BibTeX RDF	EDF schemes, EDF strategies, concurrent confinement games, confinement games, non-concurrent confinement games, smooth scheduling, variable rates, online scheduling, two players games
41	Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal	Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects.	ITC	2002	DBLP DOI BibTeX RDF
41	Brian A. A. Antao, Arthur J. Brodersen	ARCHGEN: Automated synthesis of analog systems.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
41	Fa-Long Luo, Rolf Unbehauen, Hongqin Xue	Continuous-time computation of the eigenvectors of a class of positive definite matrices.	PDP	1995	DBLP DOI BibTeX RDF	analogue computers, continuous-time computation, analog circuit approach, specialized analog computers, asynchronous parallel processing, continuous-time dynamics, high-speed computational capability, real-time applications fields, parallel processing, neural nets, matrix algebra, eigenvectors, special purpose computers, eigenvalues and eigenfunctions, neural chips, positive definite matrices
39	Eric E. Fabris, Luigi Carro, Sergio Bampi	Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach.	FPL	2004	DBLP DOI BibTeX RDF
39	John C. Gallagher	The Once and Future Analog Alternative: Evolvable Hardware and Analog Computation.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
39	Adrián Núñez-Aldana, Ranga Vemuri	An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis.	DATE	1999	DBLP DOI BibTeX RDF
39	Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia	Viability of analog inner product operations in CMOS imagers.	SBCCI	2007	DBLP DOI BibTeX RDF	CMOS analog hardware, analog image processing, vector quantization
39	Farzan Aminian, Mehran Aminian	Fault Diagnosis of Analog Circuits Using Bayesian Neural Networks with Wavelet Transform as Preprocessor.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	analog fault diagnosis, Bayesiasn learning, neural networks, analog circuits
39	Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee	Analog circuit equivalent faults in the D.C. domain.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	analog circuit faults, fault simulation data, equivalent faults, equivalent fault identification, built-in self test, design for testability, data analysis, fault simulation, fault location, fault location, analogue circuits, linear analog circuits
39	Anna Maria Brosa, Joan Figueras	Characterization of Floating Gate Defects in Analog Cells.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	floating gate defect, low-power/low-voltage analog circuits, analog testing
39	Guido Dröge, Manfred Thole, Ernst-Helmut Horneber	EASY - a System for Computer-Aided Examination of Analog Circuits.	DATE	1998	DBLP DOI BibTeX RDF	analog design system, computer-aided design, analog circuits, symbolic analysis, qualitative analysis
39	Salvador Mir, Marcelo Lubaszewski, Bernard Courtois	Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	analog ATPG, fault diagnosis, fault-based testing, analog BIST
39	Bogdan G. Arsintescu	A Method for Analog Circuits Visualization.	ICCD	1996	DBLP DOI BibTeX RDF	Analog circuits visualization, Design verification tools, Computer aided design for analog circuits
38	Salem Abdennadher, Saghir A. Shaikh	Practices in Testing of Mixed-Signal and RF SoCs.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
38	Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen	M3-a multilevel mixed-mode mixed A/D simulator.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
37	Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao	Fortifying analog models with equivalence checking and coverage analysis.	DAC	2010	DBLP DOI BibTeX RDF	analog validation, model-first design, design methodology, fault coverage, equivalence checking, formal validation
37	Zhihong Feng, Zhigui Lin, Wei Fang, Wei Wang, Zhitao Xiao	Analog Circuit Fault Fusion Diagnosis Method Based on Support Vector Machine.	ISNN (2)	2009	DBLP DOI BibTeX RDF	Multi- classification, Support Vector Machine, Fault diagnosis, Analog circuit
37	Meng-Hui Wang, Yu-Kuo Chung, Wen-Tsai Sung	The Fault Diagnosis of Analog Circuits Based on Extension Theory.	ICIC (1)	2009	DBLP DOI BibTeX RDF	Extension theory (ET), Fault diagnosis, Analog circuit
37	Corneliu Rusu, Lacrimioara Grama, Jarmo Takala	SPICE Simulation of Analog Filters: A Method for Designing Digital Filters.	EUROCAST	2009	DBLP DOI BibTeX RDF	analog filter, SPICE, digital filter
37	Mark Po-Hung Lin, Hongbo Zhang 0001, Martin D. F. Wong, Yao-Wen Chang	Thermal-driven analog placement considering device matching.	DAC	2009	DBLP DOI BibTeX RDF	analog placement, thermal matching
37	Mark Po-Hung Lin, Shyh-Chang Lin	Analog placement based on hierarchical module clustering.	DAC	2008	DBLP DOI BibTeX RDF	analog placement, floorplanning
37	A. A. Mariano, B. Boumballa, Dominique Dallet, Yann Deval, Jean-Baptiste Bégueret	High-speed CMOS analog-to-digital converter for front-end receiver applications.	SBCCI	2007	DBLP DOI BibTeX RDF	flash structure, analog-to-digital converter, data-conversion
37	Raffaella Gentilini, Klaus Schneider 0001, Alexander Dreyer	Three-valued automated reasoning on analog properties.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	(multi valued) temporal logics & model checking, interval arithmetic, analog circuits
37	Lei Feng, Won Namgoong	An Analog/Digital Baseband Processor Design of a UWB Channelized Receiver for Transmitted Reference Signals.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	transmitted reference, channelized receiver, coarse acquisition, synchronization, Ultra-wideband, analog-to-digital converter
37	Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri	A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	genetic algorithms, branch-and-bound, performance estimation, VHDL-AMS, Analog synthesis
37	Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi	Hierarchical approach to exact symbolic analysis of large analog circuits.	DAC	2004	DBLP DOI BibTeX RDF	MEMS and/or RF design tools, behavioral modeling, analog, circuit simulation, symbolic analysis, mixed-signal
37	Walter Hartong, Lars Hedrich, Erich Barke	Model checking algorithms for analog verification.	DAC	2002	DBLP DOI BibTeX RDF	nonlinear analog systems, model checking, formal methods
37	Sasikumar Cherubal, Abhijit Chatterjee	Test generation for fault isolation in analog circuits using behavioral models.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	multiple parameter variations, manufacturing tolerances, test generation, fault location, behavioral models, analog circuits, analogue integrated circuits, fault isolation, circuit testing, behavioral descriptions, parametric failures, measurement noise
37	Sudip Chakrabarti, Abhijit Chatterjee	Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal Circuits.	ARVLSI	1999	DBLP DOI BibTeX RDF	fault diagnosis, analog, Design automation, mixed-signal, fault isolation
37	Christian Dufaza, Hassan Ihs	A BIST-DFT technique for DC test of analog modules.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	current and voltage self-testing, Built-In Voltage Sensor, Built-In Self Test, Design For Testability, analog BIST
37	Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey	A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC.	VLSI Design	2005	DBLP DOI BibTeX RDF	MOS Analog Circuits, Digital to Analog Conversion, Mixed Analog -Digital Integrated Circuits, Low Power
36	Diego Pedro Morales, Antonio García 0001, Alberto J. Palma, Miguel A. Carvajal, Encarnación Castillo, Luis F. Capitán-Vallvey	Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration.	FPL	2008	DBLP DOI BibTeX RDF
36	Saied Hemati, Amir H. Banihashemi	Convergence Speed and Throughput of Analog Decoders.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
36	Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum, Mohammad M. Mojarradi, Srinivas Katkoori, Taher Daud	Adaptive and Evolvable Analog Electronics for Space Applications.	ICES	2007	DBLP DOI BibTeX RDF	Adaptive Hardware, Field Programmable Arrays
36	Ricardo Salem Zebulum, Mohammad M. Mojarradi, Adrian Stoica, Didier Keymeulen, Taher Daud	Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications.	AHS	2007	DBLP DOI BibTeX RDF
36	Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp	DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.	DATE	2006	DBLP DOI BibTeX RDF