Search results for "Arrays"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
99	Cheng-Wen Wu, Peter R. Cappello	Easily Testable Iterative Logic Arrays.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	easily testable iterative logic arrays, octagonally connected arrays, combinational arrays, inhomogeneous arrays, bilateral arrays, test complexity, pipelined arrays, logic testing, systolic arrays, upper bound, matrix multiplication, cellular arrays, combinatorial circuits, multidimensional arrays
66	Robert C. Minnick	A Survey of Microcellular Research.	J. ACM	1967	DBLP DOI BibTeX RDF
64	Chun-Yuan Lin, Yeh-Ching Chung, Jen-Shiuh Liu	Efficient Data Distribution Schemes for EKMR-Based Sparse Arrays on Distributed Memory Multicomputers.	J. Supercomput.	2005	DBLP DOI BibTeX RDF	data distribution schemes, data compression methods, sparse ratio, partition methods, Karnaugh map
63	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis	Testing combinational iterative logic arrays for realistic faults.	VTS	1995	DBLP DOI BibTeX RDF	combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model
62	PeiZong Lee, Zvi M. Kedem	Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	nested loop algorithms, multidimensional systolic arrays, correct transformation, programmable systolic arrays, general purpose programmable arrays, planar systolic array implementations, three-dimensional cube-graph algorithm, reindexed Warshall-Floyd path-finding algorithm, parallel algorithms, parallel processing, graph theory, matrix multiplication, data dependence, matrix algebra, cellular arrays, sufficient conditions, necessary conditions, algorithm transformations, automatic compilation
60	Javed Absar, Francky Catthoor	Reuse analysis of indirectly indexed arrays.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	indirectly indexed arrays, irregular access, reuse vector, data reuse, Scratch-pad
56	Sosina Martirosyan, Tran van Trung	On t-Covering Arrays.	Des. Codes Cryptogr.	2004	DBLP DOI BibTeX RDF	t-covering arrays, perfect hash families, orthogonal arrays, algebraic-geometric codes
51	Dong Kyue Kim, Minhwan Kim, Heejin Park	Linearized Suffix Tree: an Efficient Index Data Structure with the Capabilities of Suffix Trees and Suffix Arrays.	Algorithmica	2008	DBLP DOI BibTeX RDF	Index data structures, Suffix trees, Suffix arrays, String algorithms
50	José E. Moreira, Samuel P. Midkiff, Manish Gupta 0002	A comparison of three approaches to language, compiler, and library support for multidimensional arrays in Java.	Java Grande	2001	DBLP DOI BibTeX RDF	Java
49	Steven J. E. Wilton	Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays.	FPGA	2000	DBLP DOI BibTeX RDF
49	Steven J. E. Wilton	SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays.	FPGA	1998	DBLP DOI BibTeX RDF
48	Edwin Hsing-Mean Sha, Kenneth Steiglitz	Reconfigurability and Reliability of Systolic/Wavefront Arrays.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	wavefront arrays, fault-tolerant redundant structures, reliable arrays, application graph, finitely reconfigurable, locally reconfigurable, reliability, lower bound, fault tolerant computing, reconfigurability, time complexity, systolic arrays, systolic arrays, reconfigurable architectures, dynamic graphs, bounded-degree graphs
48	Viktor K. Prasanna, Yu-Chen Tsai	On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	fault-tolerant systolic arrays, linearly connected arrays, processor elements, VLSI model, Diogenes methodology, algorithms, fault tolerant computing, cellular arrays, propagation delay, matrix computations, mapping technique, linear systolic arrays
48	Wei-Kang Huang, Fabrizio Lombardi	An approach for testing programmable/configurable field programmable gate arrays.	VTS	1996	DBLP DOI BibTeX RDF	behavioral characterization, single fault detection, disjoint one-dimensional arrays, unilateral horizontal connections, common vertical input lines, array testing, logic blocks, field programmable gate arrays, field programmable gate arrays, VLSI, logic testing, integrated circuit testing, stuck-at fault, FPGA testing, functional fault, hybrid fault model
48	Michèle Dion, Tanguy Risset, Yves Robert	Resource-constrained scheduling of partitioned algorithms on processor arrays.	PDP	1995	DBLP DOI BibTeX RDF	physical processor arrays, communication capabilities, complex optimization problem, single integer linear programming problem, scheduling, computational complexity, complexity, linear programming, mapping, optimisation, processor arrays, partitioned algorithms, communication links, resource-constrained scheduling, optimal scheduling algorithms, linear processor arrays
47	Gary W. Elko	Future Directions for Microphone Arrays.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
47	Sven Nordholm, Ingvar Claesson, Nedelko Grbic	Optimal and Adaptive Microphone Arrays for Speech Input in Automobiles.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
47	Jörg Bitzer, Klaus Uwe Simmer	Superdirective Microphone Arrays.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
47	Walter L. Kellermann	Acoustic Echo Cancellation for Beamforming Microphone Arrays.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
47	Rainer Martin 0001	Small Microphone Arrays with Postfilters for Noise and Acoustic Echo Reduction.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
47	Maurizio Omologo, Marco Matassoni, Piergiorgio Svaizer	Speech Recognition with Microphone Arrays.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
46	John P. McSorley	Double Arrays, Triple Arrays and Balanced Grids with v=r+c - 1.	Des. Codes Cryptogr.	2005	DBLP DOI BibTeX RDF	double arrays, triple arrays, balanced grids, designs, arrays
46	Wu Jigang, Thambipillai Srikanthan, Xiaodong Wang	Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Degradable VLSI array, algorithm, routing, reconfiguration, faulttolerance
46	Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton	Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays.	FPL	2006	DBLP DOI BibTeX RDF
46	Jürgen Teich, Lothar Thiele	Control generation in the design of processor arrays.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
43	Richard D. Neidinger	Computing Multivariable Taylor Series to Arbitrary Order.	APL	1995	DBLP DOI BibTeX RDF	nested arrays, data structure, APL, numerical method, automatic differentiation, Taylor series, partial derivatives
43	Graham M. Megson, Xian Chen	A synthesis method of LSGP partitioning for given-shape regular arrays.	IPPS	1995	DBLP DOI BibTeX RDF	LSGP partitioning, given-shape regular arrays, computational polytope, activity matrix, timing vector, locally sequential globally parallel, parallel algorithms, data structures, systolic arrays, processor arrays
42	Gary M. Zoppetti, Gagan Agrawal, Rishi Kumar	Impact of Data Distribution on Performance of Irregular Reductions on Multithreaded Architectures.	HPCN	2001	DBLP DOI BibTeX RDF
42	Itsuo Takanami, Tadayoshi Horita	A built-in self-reconfigurable scheme for 3D mesh arrays.	ISPAN	1997	DBLP DOI BibTeX RDF	fault tolerant 3D processor arrays, 3D mesh arrays, self-reconfigurable scheme, track switches, fault compensation, reconfiguration, reconfigurable architectures
42	Seiken Yano	Unified scan design with scannable memory arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits
41	Pantelis K. Varlamos, Panagiotis J. Papakanellos, Christos N. Capsalis	Design of Circular Switched Parasitic Dipole Arrays Using a Genetic Algorithm.	Int. J. Wirel. Inf. Networks	2004	DBLP DOI BibTeX RDF	Circular switched parasitic dipole arrays, electronic beam steering, induced EMF method, genetic algorithms, method of moments
41	Elias Yaacoub, Zaher Dawy	On WCDMA Downlink Capacity with Power Allocation Strategy and Adaptive Antenna Arrays.	ICC	2008	DBLP DOI BibTeX RDF
41	Silvio Ghilardi, Enrica Nicolini, Silvio Ranise, Daniele Zucchelli	Decision procedures for extensions of the theory of arrays.	Ann. Math. Artif. Intell.	2007	DBLP DOI BibTeX RDF	Mathematics Subject Classifications (2000) 68T27, 03B25, 03B70, 68T15
41	Silvio Ghilardi, Enrica Nicolini, Silvio Ranise, Daniele Zucchelli	Deciding Extensions of the Theory of Arrays by Integrating Decision Procedures and Instantiation Strategies.	JELIA	2006	DBLP DOI BibTeX RDF
41	Ralph T. Hoctor, Saleem A. Kassam	Array redundancy for active line arrays.	IEEE Trans. Image Process.	1996	DBLP DOI BibTeX RDF
40	Guy Even, Ami Litman	Overcoming chip-to-chip delays and clock skews.	ASAP	1996	DBLP DOI BibTeX RDF	chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews
39	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	A cellular array designed from a Multiple-valued Decision Diagram and its fault tests.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	multiple-valued decision diagram, fault tests, testable cellular arrays, VLSI, fault diagnosis, logic testing, logic CAD, cellular arrays, cellular array, multivalued logic circuits, switch functions, multiple stuck-at faults
39	Jean Frédéric Myoupo	A Fully-Pipelined Solutions Constructor for Dynamic Programming Problems.	ICCI	1991	DBLP DOI BibTeX RDF	Modular Arrays, Parallel Algorithms, Complexity, Dynamic Programming, Design of Algorithms, Linear Systolic Arrays
39	Osamu Hoshuyama, Akihiko Sugiyama	Robust Adaptive Beamforming.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
39	Joseph H. DiBiase, Harvey F. Silverman, Michael S. Brandstein	Robust Localization in Reverberant Rooms.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
39	Elio D. Di Claudio, Raffaele Parisi	Multi-Source Localization Strategies.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
39	Gary W. Elko	Spatial Coherence Functions for Differential Microphones in Isotropic Noise Fields.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
39	Darren B. Ward, Rodney A. Kennedy, Robert C. Williamson	Constant Directivity Beamforming.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
39	Klaus Uwe Simmer, Jörg Bitzer, Claude Marro	Post-Filtering Techniques.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
39	Simon Doclo, Marc Moonen	GSVD-Based Optimal Filtering for Multi-Microphone Speech Enhancement.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
39	Norbert Strobel, Sascha Spors, Rudolf Rabenstein	Joint Audio-Video Signal Processing for Object Localization and Tracking.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
39	Scott C. Douglas	Blind Separation of Acoustic Signals.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
39	Michael S. Brandstein, Scott M. Griebel	Explicit Speech Modeling for Microphone Array Applications.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
39	Dirk Van Compernolle	Future Directions in Microphone Array Processing.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
39	Julie E. Greenberg, Patrick M. Zurek	Microphone-Array Hearing Aids.	Microphone Arrays	2001	DBLP DOI BibTeX RDF
38	Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein	Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Term Rewriting Systems (TRS), algebraic manipulation, dynamically reconfigurable systems, Fast Fourier Transform (FFT), reconfigurable computing, systolic arrays, rewriting-logic
38	John C. Ramirez, Rami G. Melhem	Computational Arrays with Flexible Redundancy.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	flexible redundancy, computational arrays, processor/switch array, redundant arrays, Markov chain techniques, probability arguments, fault tolerant arrays, defect avoidance, parallel processing, fault tolerant computing, reconfiguration, redundancy, redundancy, embedding, logic design, fault detection, correction, fault masking, faulty processors, reconfiguration algorithms
38	Sy-Yen Kuo, Sheng-Chiech Liang	Concurrent Error Detection and Correction in Real-Time Systolic Sorting Arrays.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	online error correction, two level pipelining, real-time systolic sorting arrays, online error detection, VLSI sorting arrays, functional errors, data errors, real-time systems, parallel algorithms, VLSI, sorting, error correction codes, systolic arrays, error detection codes, concurrent error detection, high-throughput, self-checking, WSI, concurrent error correction
38	H. V. Jagadish, Thomas Kailath	A Family of New Efficient Arrays for Matrix Multiplication.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	regular iterative algorithm, matrix multiplication arrays, iteration vector, conventional arrays, processor cells, iterative methods, matrix algebra, cellular arrays, multiplying circuits
37	Alexander Thomasian, Gang Fu, Chunqi Han	Performance of Two-Disk Failure-Tolerant Disk Arrays.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Redundant arrays of independent disks, RAID5, RAID6, two-disk failure-tolerant arrays, EVENODD, RM2, operation in degraded mode, clustered RAID, fork-join requests, simulation, performance evaluation, queuing analysis, load imbalance, RDP
37	Massimo Maresca	Polymorphic Processor Arrays.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	polymorphic processor arrays, mesh-connected arrays, PPA, low complexity algorithms, PPA programming model, computational complexity, parallel processing, parallel computers, parallel architectures, multiprocessor interconnection networks
37	Jennifer B. Sartor, Stephen M. Blackburn, Daniel Frampton, Martin Hirzel, Kathryn S. McKinley	Z-rays: divide arrays and conquer speed and flexibility.	PLDI	2010	DBLP DOI BibTeX RDF	arraylets, z-rays, compression, arrays, heap
37	Lin Wan, Wenjiang J. Fu, Minghua Deng, Minping Qian	A Method to Correct Systematic Bias in Affymetrix SNP Arrays.	BMEI (1)	2008	DBLP DOI BibTeX RDF	Affymetrix SNP arrays, copy number estimation, systematic bias
37	Morten Kromberg	Arrays of objects.	DLS	2007	DBLP DOI BibTeX RDF	multi-paradigm languages, object orientation, functional programming, language design, arrays
37	Ekow J. Otoo, Doron Rotem, Sridhar Seshadri	Optimal chunking of large multidimensional arrays for data warehousing.	DOLAP	2007	DBLP DOI BibTeX RDF	multi-dimensional arrays, data warehousing, chunking
37	Dean S. Hoskins, Charles J. Colbourn, Douglas C. Montgomery	Software performance testing using covering arrays: efficient screening designs with categorical factors.	WOSP	2005	DBLP DOI BibTeX RDF	D-optimal designs, performance testing, covering arrays
37	Gerhard E. Hoernes, Garth H. Foster	Declaration and Addressing of Varying Density Arrays and Structure.	SIGMOD Workshop, Vol. 1	1974	DBLP DOI BibTeX RDF	DBTG, Data structures, APL, Schema, Arrays, Data base, Addressing, Declaration, PL/I
36	Shoulun Long, Josef Pieprzyk, Huaxiong Wang, Duncan S. Wong	Generalised Cumulative Arrays in Secret Sharing.	Des. Codes Cryptogr.	2006	DBLP DOI BibTeX RDF	Cumulative array, Perfect hash family, Secret sharing
36	Veli Mäkinen, Gonzalo Navarro 0001	Compressed Compact Suffix Arrays.	CPM	2004	DBLP DOI BibTeX RDF
35	John Schewel, Michael Thornburg, Steve Casselman	Transformable computers & hardware object technology.	IPPS	1995	DBLP DOI BibTeX RDF	transformable computers, hardware object technology, reconfigurable aspects, computationally intensive software algorithms, on-the-fly use, field programmable gate arrays, field programmable gate arrays, programming, reconfigurable architectures, programmable logic arrays, hardware design, performance gain
35	Anmol Mathur, Kuang-Chien Chen, C. L. Liu 0001	Re-engineering of timing constrained placements for regular architectures.	ICCAD	1995	DBLP DOI BibTeX RDF	Xilinx 3000 FPGA architecture, engineering requirements, regular architectures, timing constrained placements reengineering, FPGAs, field programmable gate arrays, logic CAD, program debugging, systems re-engineering, logic arrays, design flow, gate arrays, design specification, timing performance, design cycle, design debugging
35	Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
35	Philip Gillett, Miles Johnson, Jamie Carneal	Performance benefits of spherical diffracting arrays versus free field arrays.	ICASSP	2008	DBLP DOI BibTeX RDF
35	Tong Liu 0007, Wei-Kang Huang, Fabrizio Lombardi	Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays.	FPGA	1995	DBLP DOI BibTeX RDF	constant testability, FPGA, testing, manufacturing
34	S. D. Kaushik, Chua-Huang Huang, J. Ramanujam, P. Sadayappan	Multi-phase array redistribution: modeling and evaluation.	IPPS	1995	DBLP DOI BibTeX RDF	block-cyclically distributed arrays, multi-phase approach, parallel programming, processor scheduling, cost model, arrays, High Performance Fortran, communication overhead, array redistribution, modeling and evaluation
34	Peng Zhao, Shimin Cui, Yaoqing Gao, Raúl Silvera, José Nelson Amaral	Forma: A framework for safe automatic array reshaping.	ACM Trans. Program. Lang. Syst.	2007	DBLP DOI BibTeX RDF	reference analysis, data structure, Arrays
33	Martin C. Herbordt, Jade Cravy, Honghai Zhang, Calvin Lin, Hong Rao	An Array Control Unit for High Performance SIMD Arrays.	CAMP	2000	DBLP DOI BibTeX RDF	array control unit, high performance SIMD arrays, array utilization, SIMD arrays, parallel processing
33	T. Utsumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Multiple-Valued Programmable Logic Arrays with Universal Literals.	ISMVL	1997	DBLP DOI BibTeX RDF	universal literals, multiple-valued programmable logic, universal literal generators, operator structures, programmable logic arrays, programmable logic arrays
33	Bradly K. Fawcett, J. Watson	Reconfigurable Processing With Field Programmable Gate Arrays.	ASAP	1996	DBLP DOI BibTeX RDF	reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays
33	Timothy J. Schulz	Coherent array imaging with sparse arrays.	ICIP	1995	DBLP DOI BibTeX RDF	antenna phased arrays, sparse arrays, coherent array imaging, phased-array imaging systems, Fourier inversion, coherent imaging system, image processing, maximum likelihood estimation, maximum-likelihood estimation, missing data, incomplete data, array signal processing, aperture
33	David C. J. Naylor, Simon Jones 0001	A Performance Model for Multilayer Neural Networks in Linear Arrays.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	throughput rate, input-output bandwidth, two-hidden-layer network, performance evaluation, performance, performance model, latency, systolic arrays, multilayer perceptrons, feedforward neural nets, linear arrays, multilayer neural networks
32	Jeremy Kepner	Multicore programming in pMatlab using distributed arrays.	CLADE	2008	DBLP DOI BibTeX RDF	parallel computing, distributed arrays
32	Cemal Yilmaz 0001, Myra B. Cohen, Adam A. Porter	Covering Arrays for Efficient Fault Characterization in Complex Configuration Spaces.	IEEE Trans. Software Eng.	2006	DBLP DOI BibTeX RDF	fault characterization, Software testing, covering arrays, distributed continuous quality assurance
32	Marco A. Panduro, Carlos A. Brizuela, David Covarrubias, Claudio Lopez	A trade-off curve computation for linear antenna arrays using an evolutionary multi-objective approach.	Soft Comput.	2006	DBLP DOI BibTeX RDF	Non-regular arrays, Minor lobes, Radiation pattern, Genetic algorithms, Multi-objective
32	Ming Wu, Xiao-Ming Dong, Huaiyang Li	Queue Network Modeling Approach to Analysis of the Optimal Stripe Unit Size for Disk Arrays under Synchronous I/O Workloads.	IWNAS	2006	DBLP DOI BibTeX RDF	stripe unit size, simulation, RAID, disk arrays, queue network model
32	Phil Ventura, Christopher A. Egert, Adrienne Decker	Ancestor worship in CS1: on the primacy of arrays.	OOPSLA Companion	2004	DBLP DOI BibTeX RDF	data structures, object-oriented programming, CS1, curriculum, object oriented-design, arrays, objects-first
32	Kees van Reeuwijk, Will Denissen, Henk J. Sips, Edwin M. R. M. Paalvast	An Implementation Framework for HPF Distributed Arrays on Message-Passing Parallel Computer Systems.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	message aggregation, parallel computers, message passing, HPF, distributed arrays
32	Kumar N. Ganapathy, Benjamin W. Wah	Optimal Synthesis of Algorithm-Specific Lower-Dimensional Processor Arrays.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	polynomial-time search, transitive closure, processor arrays, optimal design, objective function, Design constraints, uniform recurrence equations
32	William P. Marnane, Will R. Moore	Testing VLSI regular arrays.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	testing regular arrays, C-testability, test vector generation
31	Ali M. Bazzi, Sami H. Karaki	Simulation of a new maximum power point tracking technique for multiple photovoltaic arrays.	EIT	2008	DBLP DOI BibTeX RDF
31	Tansu Filik, T. Engin Tuncer	Design and evaluation of V-shaped arrays for 2-D DOA estimation.	ICASSP	2008	DBLP DOI BibTeX RDF
31	Inas Khalifa, Rodney G. Vaughan	Optimal Configuration of Multi-Faceted Phased Arrays for Wide Angle Coverage.	VTC Spring	2007	DBLP DOI BibTeX RDF
31	Craig B. Zilles	Accordion arrays.	ISMM	2007	DBLP DOI BibTeX RDF	Java, compression, memory management, polymorphism, array, character, unicode
31	Martin Kutrib, Andreas Malcher	Real-Time Reversible Iterative Arrays.	FCT	2007	DBLP DOI BibTeX RDF
31	Adam O'Donovan, Ramani Duraiswami, Jan Neumann	Microphone Arrays as Generalized Cameras for Integrated Audio Visual Processing.	CVPR	2007	DBLP DOI BibTeX RDF
31	Laura Ruff	Functional-Based Comparison between Two Special Classes of Uni- and Bidirectional Systolic Arrays.	SYNASC	2007	DBLP DOI BibTeX RDF
31	Ekow J. Otoo, Doron Rotem	Parallel access of out-of-core dense extendible arrays.	CLUSTER	2007	DBLP DOI BibTeX RDF
31	Simon J. Puglisi, William F. Smyth, Andrew Turpin	Suffix arrays: what are they good for?	ADC	2006	DBLP BibTeX RDF
31	Hiroshi Umeo, Masaya Hisaoka, Shunsuke Akiguchi	A Twelve-State Optimum-Time Synchronization Algorithm for Two-Dimensional Rectangular Cellular Arrays.	UC	2005	DBLP DOI BibTeX RDF
31	Margaret Miró-Julià	Degenerate Arrays: A Framework for Uncertain Data Tables.	EUROCAST	2005	DBLP DOI BibTeX RDF
31	Klaus-Bernd Schürmann, Jens Stoye	Counting Suffix Arrays and Strings.	SPIRE	2005	DBLP DOI BibTeX RDF
31	Dong Kyue Kim, Junha Jo, Heejin Park	A Fast Algorithm for Constructing Suffix Arrays for Fixed-Size Alphabets.	WEA	2004	DBLP DOI BibTeX RDF
31	Steven Hinckley, Paul V. Jansz-Drávetzky, Kamran Eshraghian	Pixel Structure Effects on Crosstalk in Backwall Illuminated CMOS Compatible Photodiode Arrays.	DELTA	2004	DBLP DOI BibTeX RDF
31	Hiroshi Umeo, Masashi Maeda, Norio Fujiwara	An Efficient Mapping Scheme for Embedding Any One-Dimensional Firing Squad Synchronization Algorithm onto Two-Dimensional Arrays.	ACRI	2002	DBLP DOI BibTeX RDF
31	Tatsuo Tsuji, Hidetatsu Kawahara, Teruhisa Hochin, Ken Higuchi	Sharing Extendible Arrays in a Distributed Environment.	IICS	2001	DBLP DOI BibTeX RDF