Search results for "BISR"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
125	Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu	Economic Aspects of Memory Built-in Self-Repair.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	BIRA, BIST, yield, overhead, economic models, BISR, redundancy analysis, built-in self-repair
84	Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu	A Built-In Self-Repair Scheme for NOR-Type Flash Memory.	VTS	2006	DBLP DOI BibTeX RDF
80	Uthman Alsaiari, Resve A. Saleh	Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy.	ISQED	2007	DBLP DOI BibTeX RDF
80	Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey	Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
75	Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni	A Family of Self-Repair SRAM Cores.	IOLTW	2000	DBLP DOI BibTeX RDF	Memory Self-Repair, Memory BIST, BISR
70	Liviu Miclea, Szilárd Enyedi, Alfredo Benso	Itelligent Agents and BIST/BISR - Working Together in Distributed Systems.	ITC	2002	DBLP DOI BibTeX RDF	distributed systems BIST, distributed BISR, Intelligent agent, self-repair, embedded testing, high-level testing
67	Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone	Material Fatigue and Reliability of MEMS Accelerometers.	DFT	2008	DBLP DOI BibTeX RDF
67	S. Habermann, René Kothe, Heinrich Theodor Vierhaus	Built-in Self Repair by Reconfiguration of FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
67	Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone	Reliability Analysis of Self-Repairable MEMS Accelerometer.	DFT	2006	DBLP DOI BibTeX RDF
67	Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu	A built-in self-repair design for RAMs with 2-D redundancy.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
67	Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu	A Processor-Based Built-In Self-Repair Design for Embedded Memories.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
67	Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow	A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.	ITC	2003	DBLP DOI BibTeX RDF	built-in redundancy-analysis, built-in self-test, memory testing, semiconductor memory, built-in self-repair
58	Da-Ming Chang, Jin-Fu Li 0001, Yu-Jen Huang	A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Built-in self-repair (BISR), Built-in redundancy-analysis (BIRA), Two-level redundancy, Random access memory, System-on-chip (SOC)
58	Michael Nicolaidis, Lorena Anghel, Nadir Achouri	Memory Defect Tolerance Architectures for Nanotechnologies.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	word repair, nanotechnologies, BISR, memory repair, high defect densities
51	Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li 0001, Alex Pao, Kevin Chiu, Eliot Chen	A Built-In Self-Repair Scheme for Multiport RAMs.	VTS	2007	DBLP DOI BibTeX RDF
51	Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone	Design and Analysis of Self-Repairable MEMS Accelerometer.	DFT	2005	DBLP DOI BibTeX RDF
51	Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang	Fail Pattern Identification for Memory Built-In Self-Repair.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
51	Lorena Anghel, Nadir Achouri, Michael Nicolaidis	Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologie.	PRDC	2004	DBLP DOI BibTeX RDF
41	Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu	Raisin: Redundancy Analysis Algorithm Simulation.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	repair rate, BIRA, Raisin, yield, BISR, redundancy analysis, algorithm simulation
41	Kwang-Ting (Tim) Cheng	Cocktail approach to functional verification.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	validation, functional verification, multiprocessor SoC, SiP, BISR
41	Kang Yi, Kyeong-Hoon Jung, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil	Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Low power image filter design, Memory yield enhancement, Memory-error resilient design, H.264 codec, BIST, Embedded memory, BISR
41	Kanad Chakraborty	Testing and Reliability Techniques for High-Bandwidth Embedded RAMs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	multiport RAM, BIST (built-in self-test), BISR (built-in self-repair), column-multiplexed addressing, fault tolerance, reliability, bandwidth
41	Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi	Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems.	NCA	2003	DBLP DOI BibTeX RDF	Built-in-self-repair (BISR), Field Reconfiguration, HW/SW Co-reliability, Reliability Assurance, Reliability, High performance computing, Yield, Massively parallel computing, Fault-tolerant memory, Modular Redundancy
34	Olivier Ginez, Jean-Michel Portal, Hassen Aziza	An on-line testing scheme for repairing purposes in Flash memories.	DDECS	2009	DBLP DOI BibTeX RDF
34	Wei Pei, Wen-Ben Jone, Yiming Hu	Fault Modeling and Detection for Drowsy SRAM Caches.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
34	Irith Pomeranz, Sudhakar M. Reddy	Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits.	DFT	2007	DBLP DOI BibTeX RDF
34	Tsu-Wei Tseng, Jin-Fu Li 0001, Da-Ming Chang	A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap.	DATE	2006	DBLP DOI BibTeX RDF
34	Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li 0001	A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy.	DFT	2006	DBLP DOI BibTeX RDF
34	Inki Hong, Miodrag Potkonjak, Ramesh Karri	A heterogeneous built-in self-repair approach using system-level synthesis flexibility.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
34	Rita Zappa, Carolina Selva, Danilo Rimondi, Cosimo Torelli, M. Crestan, Giovanni Mastrodomenico, Lara Albani	Micro Programmable Built-In Self Repair for SRAMs.	MTDT	2004	DBLP DOI BibTeX RDF
34	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Optimal Spare Utilization in Repairable and Reliable Memory Cores.	MTDT	2003	DBLP DOI BibTeX RDF	Embedded Memory Repair and Reliability, Fault-Tolerant Memory Core, System-on-chip, Yield, Built-In-Self-Repair
34	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems.	DFT	2002	DBLP DOI BibTeX RDF
29	Qian Yu, Qing Li 0006, Rui He, Gareth Tyson, Wanxin Shi, Jianhui Lv, Zhenhui Yuan, Peng Zhang, Yulong Lan, Zhicheng Li	BiSR: Bidirectionally Optimized Super-Resolution for Mobile Video Streaming.	WWW	2023	DBLP DOI BibTeX RDF
29	Wei Zou, Benoit Nadeau-Dostie	Configurable BISR Chain For Fast Repair Data Loading.	ITC	2022	DBLP DOI BibTeX RDF
29	Sabyasachee Banerjee	Experimental result of our BISR work.		2020	DOI RDF
29	Venkat Sundar Gadepalli, Hatice Gulcin Ozer, Ayse Selen Yilmaz, Maciej Pietrzak, Amy Webb	BISR-RNAseq: an efficient and scalable RNAseq analysis workflow with interactive report generation.	BMC Bioinform.	2019	DBLP DOI BibTeX RDF
29	Wei-Kai Cheng, Jian-Kai Chen, Shih-Hsu Huang	Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction.	ISOCC	2018	DBLP DOI BibTeX RDF
29	Tianjian Li, Yan Han, Xiaoyao Liang, Hsien-Hsin S. Lee, Li Jiang 0002	Fault clustering technique for 3D memory BISR.	DATE	2017	DBLP DOI BibTeX RDF
29	Chih-Sheng Hou, Jin-Fu Li 0001	High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
29	Madhuri Elsa Eapen, C. Pradeep, Anila Ann Varghese, Jisha M. Nair	Placement Strategies for Faulty Cells in Module Relocation Based BISR Approach.	IBICA	2015	DBLP DOI BibTeX RDF
29	Andrej Kincel, Marcel Baláz	Case study: BISR for a processor multiplier.	DDECS	2014	DBLP DOI BibTeX RDF
29	Gang Wang, Xu Wang, Xinke Chen, Shuangbai Xue	Test and Repair Flow for Shared BISR in Asynchronous Multi-processors.	ASYNC	2014	DBLP DOI BibTeX RDF
29	Georgios Zervakis 0001, Nikolaos Eftaxiopoulos-Sarris, Kostas Tsoumanis, Nicholas Axelos, Kiamal Z. Pekmestzi	A segmentation-based BISR scheme.	ASP-DAC	2014	DBLP DOI BibTeX RDF
29	Maddu Karunaratne, Bejoy Oomann	An Optimal Memory BISR Implementation.	J. Comput.	2013	DBLP BibTeX RDF
29	Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin	3D-IC BISR for stacked memories using cross-die spares.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
29	Kun-Chih Chen, Shu-Yen Lin, Wen-Chung Shen, An-Yeu Wu	A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks.	Des. Autom. Embed. Syst.	2011	DBLP DOI BibTeX RDF
29	Shyue-Kung Lu, Chun-Lin Yang, Yuang-Cheng Hsiao, Cheng-Wen Wu	Efficient BISR Techniques for Embedded Memories Considering Cluster Faults.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
29	Kiamal Z. Pekmestzi, Nicholas Axelos, Isidoros Sideris, Nikos K. Moshopoulos	A BISR Architecture for Embedded Memories.	IOLTS	2008	DBLP DOI BibTeX RDF
29	Chun-Lin Yang, Yuang-Cheng Hsiao, Shyue-Kung Lu	Efficient BISR Techniques for Embedded Memories Considering Cluster Faults.	PRDC	2007	DBLP DOI BibTeX RDF
29	Shyue-Kung Lu, Chun-Lin Yang, Han-Wen Lin	Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy.	ACIS-ICIS	2006	DBLP DOI BibTeX RDF
29	Li-Ming Denq, Tzu-chiang Wang, Cheng-Wen Wu	An Enhanced SRAM BISR Design with Reduced Timing Penalty.	ATS	2006	DBLP DOI BibTeX RDF
29	Gustavo Neuberger, Fernanda Lima Kastensmidt, Ricardo Reis 0001	TOC-BISR: A Self-Repair Scheme for Memories in Embedded Systems.	IESS	2005	DBLP DOI BibTeX RDF
29	Michael Nicolaidis, Slimane Boutobza, Nadir Achouri, R. D. Shawn Blanton, Julie Segal, David Y. Lepejian, Ben Chu, Tony Singh, Harvey Berman	Designing and Implementing Efficient BISR Techniques for Embedded RAMs.	LATW	2001	DBLP BibTeX RDF
29	Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada	Test cost reduction by at-speed BISR for embedded DRAMs.	ITC	2001	DBLP DOI BibTeX RDF
29	Inki Hong, Miodrag Potkonjak, Ramesh Karri	Heterogeneous BISR-approach using System Level Synthesis Flexibility.	ASP-DAC	1998	DBLP DOI BibTeX RDF
29	Miodrag Potkonjak, Lisa M. Guerra, Jan M. Rabaey	Heterogeneous BISR techniques for yield and reliability enhancement using high level synthesis transformations.	ASAP	1993	DBLP DOI BibTeX RDF
24	André K. Nieuwland, Richard P. Kleihorst	IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	IC cost, IC production, fault tolerant, redundancy, yield, soft error, on-line test, defect density, SEU, SER, BISR
24	Kanad Chakraborty, Anurag Gupta, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder	A Physical Design Tool for Built-in Self-Repairable Static RAMs.	DATE	1999	DBLP DOI BibTeX RDF	Built-in, (BISR), reliability, yield, self-repair
17	Uthman Alsaiari, Resve A. Saleh	Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits.	ISQED	2008	DBLP DOI BibTeX RDF	Partitioning, Redundancy, Yield, Flip-Flop
17	R. Chandramouli	Managing Test and Repair of Embedded Memory Subsystem in SoC.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
17	Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu	On Test and Diagnostics of Flash Memories.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
17	Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor	The State-of-Art and Future Trends in Testing Embedded Memories.	MTDT	2004	DBLP DOI BibTeX RDF
17	Michael Nicolaidis, Nadir Achouri, Lorena Anghel	A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies.	VTS	2004	DBLP DOI BibTeX RDF	ECC codes, word repair, nanotechnologies, memory repair, high defect densities
17	Liviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto	Towards Microagent based DBIST/DBISR.	ITC	2004	DBLP DOI BibTeX RDF
17	Robert C. Aitken	A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories.	ITC	2004	DBLP DOI BibTeX RDF
17	Liviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto	Agent Based DBIST/DBISR And Its Web/Wireless Management.	ITC	2003	DBLP DOI BibTeX RDF
17	Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu	A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.	MTDT	2002	DBLP DOI BibTeX RDF	simulation, memory testing, embedded memory, redundancy analysis, memory repair
17	Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu	A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories.	IOLTW	2002	DBLP DOI BibTeX RDF	simulation, memory testing, embedded memory, redundancy analysis, memory repair
17	Kanad Chakraborty, Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder, Anurag Gupta	A physical design tool for built-in self-repairable RAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
17	Pinaki Mazumder, Jih-Shyr Yih	A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF