Search results for "Booth"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
122	Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy	A novel covalent redundant binary Booth encoder.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
84	Justin Hensley, Anselmo Lastra, Montek Singh	A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier.	ASYNC	2005	DBLP DOI BibTeX RDF
84	Chung Nan Lyu, David W. Matula	Redundant Binary Booth Recoding.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF
84	Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija	Energy efficient implementation of parallel CMOS multipliers with improved compressors.	ISLPED	2010	DBLP DOI BibTeX RDF	arithmetic and logic structures, VLSI, low-power design, high- speed arithmetic, booth encoding
77	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis	C-Testable modified-Booth multipliers.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model
71	Min-An Song, Lan-Da Van, Chih-Chyau Yang, Shih-Chieh Chiu, Sy-Yen Kuo	A framework for the design of error-aware power-efficient fixed-width Booth multipliers.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
71	Justin Hensley, Anselmo Lastra, Montek Singh	An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices.	ICCD	2004	DBLP DOI BibTeX RDF
71	Hwang-Cherng Chow, I-Chyn Wey	A 3.3 V 1 GHz high speed pipelined Booth multiplier.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
71	Li-Hsun Chen, Oscal T.-C. Chen	A low-complexity and high-speed Booth-algorithm FIR architecture.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
71	T. Sansaloni, Javier Valls, Keshab K. Parhi	Digit-Serial Complex-Number Multipliers on FPGAs.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	complex-number multipliers, digit-serial arithmetic, FPGA, Booth recoding
65	Wen-Chang Yeh, Chein-Wei Jen	High-Speed Booth Encoded Parallel Multiplier Design.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Final adder, multiple-level conditional-sum adder and parallel multiplier, Booth encoding
65	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Effective Built-In Self-Test for Booth Multipliers.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF	Booth multipliers, Built-In Self Test, design for testability, data paths
58	Hong-An Huang, Yen-Chin Liao, Hsie-Chia Chang	A self-compensation fixed-width booth multiplier and its 128-point FFT applications.	ISCAS	2006	DBLP DOI BibTeX RDF
58	Hanho Lee	Reconfigurable Power-Aware Scalable Booth Multiplier.	KES (1)	2005	DBLP DOI BibTeX RDF
58	Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.	Improved-Booth encoding for low-power multipliers.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
52	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Modified Booth Modulo 2n-1 Multipliers.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Mersenne arithmetic, one's complement arithmetic, Booth multipliers, VLSI design, Residue Number System
52	Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-Seog Choi	54x54-bit radix-4 multiplier based on modified booth algorithm.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	compressor, adder, multiplier, booth encoder, wallace tree
52	Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou	Low Power Dissipation in BIST Schemes for Modified Booth Multipliers.	DFT	1999	DBLP DOI BibTeX RDF	Modified Booth Multipliers, Low Power, Built In Self Test, VLSI Testing
52	Michael Nicolaidis, Ricardo de Oliveira Duarte	Design of Fault-Secure Parity-Prediction Booth Multipliers.	DATE	1998	DBLP DOI BibTeX RDF	Booth multipliers, Self-checking circuits
52	Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu	Design of C-Testable Multipliers Based on the Modified Booth Algorithm.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	modified Booth Algorithm, c-testable design, design for testability, multiplier, exhaustive testing, cell fault model
52	S. M. Aziz	A C-testable modified Booth's array multiplier.	VLSI Design	1995	DBLP DOI BibTeX RDF	C-testable multiplier, modified Booth algorithm, gate-level design, parallel processing, logic testing, integrated circuit testing, digital arithmetic, stuck-at faults, CMOS logic circuits, multiplying circuits, logic arrays, array multiplier, parallel multiplier
52	D. V. Poornaiah, P. V. Ananda Mohan	Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron
45	Hsing-Chung Liang, Pao-Hsin Huang, Yan-Fei Tang	Testing Transition Delay Faults in Modified Booth Multipliers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
45	Rizwan Mudassir, Mohab Anis, Javid Jaffari	Switching activity reduction in low power Booth multiplier.	ISCAS	2008	DBLP DOI BibTeX RDF
45	Young Eun Kim, J. O. Yoon, K. J. Cho, Jin-Gyun Chung, S. I. Cho, S. S. Choi	Efficient design of modified Booth multipliers for predetermined coefficients.	ISCAS	2006	DBLP DOI BibTeX RDF
45	Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José Monteiro 0001, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis	A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
45	Alok A. Katkar, James E. Stine	Modified booth truncated multipliers.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	VLSI, arithmetic
45	Hwang-Cherng Chow, I-Chyn Wey	A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
45	Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou	Sub-word and reduced-width Booth multipliers for DSP applications.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
45	Shugang Wei, Shuangching Chen, Kensuke Shimizu	Fast modular multiplication using Booth recoding based on signed-digit number arithmetic.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
45	Raj S. Katti	A modified Booth algorithm for high radix fixed-point multiplication.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
45	Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man	Design of a C-testable booth multiplier using a realistic fault model.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	test generation, design for testability, fault modelling, Array multipliers, C-testability
45	Dimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou	A high-speed radix-4 multiplexer-based array multiplier.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	modified booth, multiplexer-based, radix-4 multiplier, array multiplier
45	Peter-Michael Seidel, Lee D. McFearin, David W. Matula	Secondary Radix Recodings for Higher Radix Multipliers.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	recoding, high radix, digit set, mixed radix representation, partial product reduction, Booth recoding, Binary multiplication
45	Eric M. Schwarz, Robert M. Averill III, Leon J. Sigal	A Radix-8 CMOS S/390 Multiplier.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	Booth algorithm, computer arithmetic, multiplication, multiplier, floating-point unit
45	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Design tradeoffs in high speed multipliers and FIR filters.	VLSI Design	1996	DBLP DOI BibTeX RDF	high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
39	Seokho Lee, Youngmin Kim	Booth Fusion: Efficient Bit Fusion Multiplier with Booth Encoding.	ISOCC	2020	DBLP DOI BibTeX RDF
39	Hyunpil Kim, Sangook Moon, Yong-Surk Lee	Radix-16 Booth multiplier using novel weighted 2-stage Booth algorithm.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
39	Wolfgang J. Paul, Peter-Michael Seidel	To Booth or not to Booth.	Integr.	2002	DBLP DOI BibTeX RDF
39	Louis P. Rubinfield	A Proof of the Modified Booth's Algorithm for Multiplication.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Modified Booth's algorithm, multiplicand, multiplier, partial product
39	Jung-Yup Kang, Jean-Luc Gaudiot	A Simple High-Speed Multiplier Design.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Booth, modified Booth, Multiplier, partial products
38	Peter Heinzmann, Lothar Müller, Stéphane Racine, Ljiljana Vukelja	The Fototeddy Strategy - Web Site Attraction Through Physical Interaction.	ENTER	2007	DBLP DOI BibTeX RDF	web site promotion, human computer interaction, user experience, gesture control
38	Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	A New Pipelined Array Architecture for Signed Multiplication.	SBCCI	2003	DBLP DOI BibTeX RDF
38	Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	A New Architecture for Signed Radix-2m Pure Array Multipliers.	ICCD	2002	DBLP DOI BibTeX RDF
38	Peter-Michael Seidel, Lee D. McFearin, David W. Matula	Binary Multiplication Radix-32 and Radix-256.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
38	Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian	Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers.	VTS	2001	DBLP DOI BibTeX RDF
38	Wen-Lian Hsu	PC-Trees vs. PQ-Trees.	COCOON	2001	DBLP DOI BibTeX RDF
38	Tim Courtney, Richard H. Turner, Roger F. Woods	Multiplexer Based Reconfiguration for Virtex Multipliers.	FPL	2000	DBLP DOI BibTeX RDF
38	Joe Booth, Jackson Booth	Marathon Environments: Multi-Agent Continuous Control Benchmarks in a Modern Video Game Engine.	CoRR	2019	DBLP BibTeX RDF
38	Larry Booth, Elizabeth Vidal de Garcia, Vickie Booth, Eveling G. Castro Gutierrez	Going Global: A Faculty Connection between Peru and the United States.	AMCIS	2010	DBLP BibTeX RDF
38	David Booth, Stephane Booth	On the mathematics behind the entropy diversification measure in strategic management.	Int. J. Math. Oper. Res.	2009	DBLP DOI BibTeX RDF
38	Kam Fui Lau, Art Gowan, Fred Hartfield, Vickie Booth, Larry Booth, Wayne Summers	The Georgia webBSIT: profile of an online student.	SIGITE Conference	2009	DBLP DOI BibTeX RDF	e-learning, online learning, distance education
38	Kam Fui Lau, Han Reichgelt, Vickie Booth, Larry Booth, Art Gowan	The Georgia WebBSIT: an innovative collaborative online baccalaureate degree in information technology.	SIGITE Conference	2008	DBLP DOI BibTeX RDF	e-learning, online learning, distance education
32	Chiou-Yng Lee, Yu-Hsin Chiu, Che Wun Chiou	New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm.	APCCAS	2006	DBLP DOI BibTeX RDF
32	Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel	New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
32	Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury	An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm.	ASYNC	2004	DBLP DOI BibTeX RDF
32	Jin-Hua Hong, Cheng-Wen Wu	Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
32	Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu	Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division
32	Shugang Wei, Kensuke Shimizu	Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
32	Kiwon Choi, Minkyu Song	Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
32	Michael Nicolaidis, Ricardo de Oliveira Duarte	Fault-Secure Parity Prediction Booth Multipliers.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
32	Kazue Sako, Joe Kilian	Receipt-Free Mix-Type Voting Scheme - A Practical Solution to the Implementation of a Voting Booth.	EUROCRYPT	1995	DBLP DOI BibTeX RDF
32	Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.	Modified Booth algorithm for high radix fixed-point multiplication.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
32	Jalil Fadavi-Ardekani	M×N Booth encoded multiplier generator using optimized Wallace trees.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
32	Bonseok Koo, Dongwook Lee, Gwonho Ryu, Taejoo Chang, Sangjin Lee 0002	High-Speed RSA Crypto-processor with Radix-4 Modular Multiplication and Chinese Remainder Theorem.	ICISC	2006	DBLP DOI BibTeX RDF	Booth’s algorithm, RSA, Chinese Remainder Theorem, Montgomery multiplication, Carry Save Adder
32	Yijun Liu, Stephen B. Furber	The design of a low power asynchronous multiplier.	ISLPED	2004	DBLP DOI BibTeX RDF	Booth's algorithm, low power, benchmark, multiplier, asynchronous logic
32	Wieland Fischer, Jean-Pierre Seifert	High-Speed Modular Multiplication.	CT-RSA	2004	DBLP DOI BibTeX RDF	Sedlaks algorithm, Computer arithmetic, Modular multiplication, Implementation issues, Booth recoding
32	Wieland Fischer, Jean-Pierre Seifert	Unfolded Modular Multiplication.	ISAAC	2003	DBLP DOI BibTeX RDF	Sedlaks algorithm, Computer arithmetic, Modular multiplication, Implementation issues, Booth recoding
32	Geoff Knagge, David Garrett, Sivarama Venkatesan, Chris Nicol	Matrix datapath architecture for an iterative 4x4 MIMO noise whitening algorithm.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	matrix multipliction, noise whitening, MIMO, booth recoding
32	Michael J. Schulte, James E. Stine	Symmetric Bipartite Tables for Accurate Function Approximation.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	approximations, computer arithmetic, error analysis, table lookup, Elementary functions, Taylor series, symmetric, bipartite, Booth encoding, accurate
32	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita	Power analysis and low-power scheduling techniques for embedded DSP software.	ISSS	1995	DBLP DOI BibTeX RDF	circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor
32	Menghui Zheng, Alexander Albicki	Low power and high speed multiplication design through mixed number representations.	ICCD	1995	DBLP DOI BibTeX RDF	high speed multiplication, mixed number representations, low power multiplication, reduced switching, Sign-Magnitude, Redundant Binary adder, Booth decoder, Carry-Propagation-Free, digital arithmetic, VLSI architecture, redundant number systems, Partial Products
32	Suthikshn Kumar, Kevin E. Forward, Marimuthu Palaniswami	A fast-multiplier generator for FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	fast-multiplier generator, variable word length multipliers, Booth encoded optimized Wallace tree architecture, field programmable gate arrays, FPGAs, parallel architectures, artificial neural networks, multiplying circuits, FPGA architecture, neural chips
32	Richard Booth 0001, Thomas Andreas Meyer	On the Dynamics of Total Preorders: Revising Abstract Interval Orders.	ECSQARU	2007	DBLP DOI BibTeX RDF
26	Minhyeok Shin, Hanho Lee	A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications.	ISCAS	2008	DBLP DOI BibTeX RDF
26	E. Vincent Cross II, Yolanda McMillian, Priyanka Gupta, Philicity Williams, Kathryn Nobles, Juan E. Gilbert	Prime III: a user centered voting system.	CHI Extended Abstracts	2007	DBLP DOI BibTeX RDF
26	Cecilia Katzeff, Vanessa Ware	Video storytelling as mediation of organizational learning.	NordiCHI	2006	DBLP DOI BibTeX RDF	music festival, volunteer work, video, storytelling, communities of practice, workplace learning
26	Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	Design of a radix-2m hybrid array multiplier using carry save adder format.	SBCCI	2005	DBLP DOI BibTeX RDF	hybrid multiplier, low power, carry save adder
26	Li-Hsun Chen, Oscal T.-C. Chen, Teng-Yi Wang, Yung-Cheng Ma	A multiplication-accumulation computation unit with optimized compressors and minimized switching activities.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
26	Li-Hsun Chen, Oscal T.-C. Chen	A hardware-efficient FIR architecture with input-data and tap folding.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
26	Oscal T.-C. Chen, Sandy Wang, Yi-Wen Wu	Minimization of switching activities of partial products for designing low-power multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
26	David W. Matula, Alex Fit-Florea	Prescaled Integer Division.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
26	Masayuki Abe, Koutarou Suzuki	Receipt-Free Sealed-Bid Auction.	ISC	2002	DBLP DOI BibTeX RDF	bid-rigging, receipt-free, chameleon bit-commitment, Sealed-bid auction
26	Nan-Ying Shen, Oscal T.-C. Chen	Low-power multipliers by minimizing switching activities of partial products.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
26	Johann Großschädl	A unified radix-4 partial product generator for integers and binary polynomials.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
26	Oscal T.-C. Chen, Wei-Lung Liu	An FIR processor with programmable dynamic data ranges.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
26	Stuart F. Oberman, Hesham A. Al-Twaijry, Michael J. Flynn	The SNAP Project: Design of Floating Point Arithmetic Unit.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	performance-area tradeoffs, computer arithmetic, multiplication, division, Addition, floating point unit
20	Srikant Kumar Beura, Sudeshna Manjari Mahanta, Bishnulatpam Pushpa Devi, Prabir Saha	Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication.	Integr.	2024	DBLP DOI BibTeX RDF
20	Srikanth Immareddy, Arunmetha Sundaramoorthy, Aravindhan Alagarsamy	Design and implementation of hybrid (radix-8 Booth and TRAM) approximate multiplier using 15-4 approximate compressors for image processing application.	J. Real Time Image Process.	2024	DBLP DOI BibTeX RDF
20	Muhammad Hamis Haider, Hao Zhang 0041, Seok-Bum Ko	Decoder Reduction Approximation Scheme for Booth Multipliers.	IEEE Trans. Computers	2024	DBLP DOI BibTeX RDF
20	Xinhui Kang, Shin'ya Nagasawa	Integrating evaluation grid method and support vector regression for automobile trade booth design.	J. Intell. Fuzzy Syst.	2023	DBLP DOI BibTeX RDF
20	Yongxia Sheng, Huaguo Liang, Bao Fang, Cuiyun Jiang, Zhengfeng Huang, Maoxiang Yi, Yingchun Lu	Design of approximate Booth multipliers based on error compensation.	Integr.	2023	DBLP DOI BibTeX RDF
20	Gunho Park, Jaeha Kung, Youngjoo Lee	Simplified Compressor and Encoder Designs for Low-Cost Approximate Radix-4 Booth Multiplier.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
20	Quan Cheng, Liuyao Dai, Mingqiang Huang, Ao Shen, Wei Mao 0002, Masanori Hashimoto, Hao Yu 0001	A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
20	Muhammad Hamis Haider, Seok-Bum Ko	Booth Encoding-Based Energy Efficient Multipliers for Deep Learning Systems.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
20	Basant Kumar Mohanty	Efficient Approximate Multiplier Design Based on Hybrid Higher Radix Booth Encoding.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2023	DBLP DOI BibTeX RDF
20	Michael Madden 0003, Dan Szafaran, Philomena Gray, Justin Pelletier, Ted Selker	A Canary in the Voting Booth: Attacks on a Virtual Voting Machine.	ICDF2C (1)	2023	DBLP DOI BibTeX RDF
20	Zainab Aizaz, Kavita Khare, Aizaz Tirmizi	FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning Applications.	FCCM	2023	DBLP DOI BibTeX RDF
20	Keshav Thosar, Hargobind Singh, Sreejit Chatterjee, Dayanand Ambawade	Blockchain-based Booth-less Tolling System using GPS and Image Processing.	AIIoT	2023	DBLP DOI BibTeX RDF
20	Eunice Gabrielle A. Reyes, Gerome Kaye M. Cangco, Shiela Mae C. Ilagan, Hazel P. Pacunayen, Jeunise A. Piamonte, Josephine D. German	An Application of Queueing Theory on the Ticketing Booth of Light Rail Transit 1 (LRT-1) Central Station.	MSIE	2023	DBLP DOI BibTeX RDF