Results
Found 12 publication records. Showing 12 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
93 | Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel |
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders. |
ASYNC |
1997 |
DBLP DOI BibTeX RDF |
completion detection, Brent-Kung, Carry-Bypass, asynchronous, adders, hazards, high-performance design |
66 | Zhiyu Liu, Volkan Kursun |
Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
66 | Zhiyu Liu, Volkan Kursun |
Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
Multi-threshold voltage CMOS, gated power, gated ground, sleep switch, subthreshold leakage, charge recycling |
60 | Matthew M. Ziegler, Mircea R. Stan |
A Unified Design Space for Regular Parallel Prefix Adders. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
Kogge-Stone adder, Han-Carlson adder, Brent-Kung adder, parallel prefix adder |
56 | A. Niyas Ahamed, M. Madheswaran |
Hybrid Brent Kung Adder with Modified Sum Generator for Energy Efficient Applications. |
J. Circuits Syst. Comput. |
2023 |
DBLP DOI BibTeX RDF |
|
56 | Aruru Sai Kumar, U. Siddhesh, N. Sai Kiran, K. Bhavitha |
Design of High Speed 8-bit Vedic Multiplier using Brent Kung Adders. |
ICCCNT |
2022 |
DBLP DOI BibTeX RDF |
|
33 | Sabyasachi Das, Sunil P. Khatri |
A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Christopher Umans |
Fast polynomial factorization and modular composition in small characteristic. |
STOC |
2008 |
DBLP DOI BibTeX RDF |
modular composition, multipoint evaluation, polynomial factorization |
33 | Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner |
Variable delay ripple carry adder with carry chain interrupt detection. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Scott Hauck, Matthew M. Hosler, Thomas W. Fry |
High-performance carry chains for FPGA's. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Scott Hauck, Matthew M. Hosler, Thomas W. Fry |
High-Performance Carry Chains for FPGAs. |
FPGA |
1998 |
DBLP DOI BibTeX RDF |
|
33 | Tudor Jebelean |
Systolic Algorithms for Long Integer GCD Computation. |
CONPAR |
1994 |
DBLP DOI BibTeX RDF |
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