Search results for "Built-In-Self-Repair"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
89	Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow	A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.	ITC	2003	DBLP DOI BibTeX RDF	built-in redundancy-analysis, built-in self-test, memory testing, semiconductor memory, built-in self-repair
75	Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu	Economic Aspects of Memory Built-in Self-Repair.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	BIRA, BIST, yield, overhead, economic models, BISR, redundancy analysis, built-in self-repair
70	Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee 0001	At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories.	VLSI Design	2004	DBLP DOI BibTeX RDF
66	Chih-Sheng Hou, Jin-Fu Li 0001, Che-Wei Chou	Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs.	DELTA	2010	DBLP DOI BibTeX RDF	test, test scheduling, repair, RAM, built-in self-repair
63	Rita Zappa, Carolina Selva, Danilo Rimondi, Cosimo Torelli, M. Crestan, Giovanni Mastrodomenico, Lara Albani	Micro Programmable Built-In Self Repair for SRAMs.	MTDT	2004	DBLP DOI BibTeX RDF
63	Pinaki Mazumder, Jih-Shyr Yih	A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
61	Michael Nicolaidis, Nadir Achouri, Slimane Boutobza	Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair.	DATE	2003	DBLP DOI BibTeX RDF
59	Michael Nicolaidis, Nadir Achouri, Lorena Anghel	A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies.	VTS	2004	DBLP DOI BibTeX RDF	ECC codes, word repair, nanotechnologies, memory repair, high defect densities
57	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Optimal Spare Utilization in Repairable and Reliable Memory Cores.	MTDT	2003	DBLP DOI BibTeX RDF	Embedded Memory Repair and Reliability, Fault-Tolerant Memory Core, System-on-chip, Yield, Built-In-Self-Repair
56	Shyue-Kung Lu	A Novel Built-In Self-Repair Approach for Embedded RAMs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	divided word line, fault tolerance, redundancy, low power design, embedded memory
55	Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu	A Built-In Self-Repair Scheme for NOR-Type Flash Memory.	VTS	2006	DBLP DOI BibTeX RDF
53	Kanad Chakraborty	Testing and Reliability Techniques for High-Bandwidth Embedded RAMs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	multiport RAM, BIST (built-in self-test), BISR (built-in self-repair), column-multiplexed addressing, fault tolerance, reliability, bandwidth
53	Da-Ming Chang, Jin-Fu Li 0001, Yu-Jen Huang	A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Built-in self-repair (BISR), Built-in redundancy-analysis (BIRA), Two-level redundancy, Random access memory, System-on-chip (SOC)
50	Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu	A built-in self-repair design for RAMs with 2-D redundancy.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
50	Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang	Fail Pattern Identification for Memory Built-In Self-Repair.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
48	Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu	Raisin: Redundancy Analysis Algorithm Simulation.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	repair rate, BIRA, Raisin, yield, BISR, redundancy analysis, algorithm simulation
48	Michael Nicolaidis, Nadir Achouri, Slimane Boutobza	Dynamic Data-bit Memory Built-In Self- Repair.	ICCAD	2003	DBLP DOI BibTeX RDF
46	R. Chandramouli	Managing Test and Repair of Embedded Memory Subsystem in SoC.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
45	Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li 0001, Alex Pao, Kevin Chiu, Eliot Chen	A Built-In Self-Repair Scheme for Multiport RAMs.	VTS	2007	DBLP DOI BibTeX RDF
45	Michael Nicolaidis, Nadir Achouri, Lorena Anghel	Memory Built-In Self-Repair for Nanotechnologies.	IOLTS	2003	DBLP DOI BibTeX RDF
43	S. Habermann, René Kothe, Heinrich Theodor Vierhaus	Built-in Self Repair by Reconfiguration of FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
43	Michael Nicolaidis, Nadir Achouri, Lorena Anghel	A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities.	DFT	2003	DBLP DOI BibTeX RDF
39	Yu-Chih Tsai, Wen-Chien Ting, Chia-Chun Wang, Chia-Cheng Chang, Ren-Shuo Liu	Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory.	DATE	2023	DBLP DOI BibTeX RDF
36	Inki Hong, Miodrag Potkonjak, Ramesh Karri	A heterogeneous built-in self-repair approach using system-level synthesis flexibility.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
36	Lorena Anghel, Nadir Achouri, Michael Nicolaidis	Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologie.	PRDC	2004	DBLP DOI BibTeX RDF
36	Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu	A Processor-Based Built-In Self-Repair Design for Embedded Memories.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
35	Tsu-Wei Tseng, Jin-Fu Li 0001, Da-Ming Chang	A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap.	DATE	2006	DBLP DOI BibTeX RDF
32	Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi	Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems.	NCA	2003	DBLP DOI BibTeX RDF	Built-in-self-repair (BISR), Field Reconfiguration, HW/SW Co-reliability, Reliability Assurance, Reliability, High performance computing, Yield, Massively parallel computing, Fault-tolerant memory, Modular Redundancy
32	Chih-Hsien Hsu, Shyue-Kung Lu, Sy-Yen Kuo	Novel Fault-Tolerant Techniques for High Capacity RAMs.	PRDC	2001	DBLP DOI BibTeX RDF	divided bit-line, divided word-line, fault tolerance and redundancy, built-in self-repair
30	Michael Nicolaidis, Lorena Anghel, Nadir Achouri	Memory Defect Tolerance Architectures for Nanotechnologies.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	word repair, nanotechnologies, BISR, memory repair, high defect densities
30	Liviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto	Agent Based DBIST/DBISR And Its Web/Wireless Management.	ITC	2003	DBLP DOI BibTeX RDF
28	Kanad Chakraborty, Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder, Anurag Gupta	A physical design tool for built-in self-repairable RAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
28	Uthman Alsaiari, Resve A. Saleh	Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits.	ISQED	2008	DBLP DOI BibTeX RDF	Partitioning, Redundancy, Yield, Flip-Flop
25	Chao-Da Huang, Jin-Fu Li 0001, Tsu-Wei Tseng	ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
25	Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li 0001	A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy.	DFT	2006	DBLP DOI BibTeX RDF
24	Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya	On Managing Test-Time, Power, and Layer Assignment in 3D SoCs with Built-In-Self-Repair Modules.	VLSID	2024	DBLP DOI BibTeX RDF
24	Youngkwang Lee, Donghyun Han, Sungho Kang 0001	TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
24	Shyue-Kung Lu, Xin Dong	Integrated Progressive Built-In Self-Repair (IPBISR) Techniques for NAND Flash Memory.	ITC-Asia	2023	DBLP DOI BibTeX RDF
24	Shyue-Kung Lu, Shi-Chun Tseng, Kohei Miyase	Fine-Grained Built-In Self-Repair Techniques for NAND Flash Memories.	ITC	2022	DBLP DOI BibTeX RDF
24	Hayoung Lee, Hyunggoy Oh, Sungho Kang 0001	On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug.	IEEE Access	2021	DBLP DOI BibTeX RDF
24	Tianming Ni, Hao Chang, Yao Yao, Xueyun Li, Zhengfeng Huang	A Novel Built-In Self-Repair Scheme for 3D Memory.	IEEE Access	2019	DBLP DOI BibTeX RDF
24	Aditya Kumar Singh Pundir	Novel modified memory built in self-repair (MMBISR) for SRAM using hybrid redundancy-analysis technique.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
24	Keewon Cho, Young-Woo Lee, Sungyoul Seo, Sungho Kang	An efficient built-in self-repair scheme for area reduction.	ISOCC	2017	DBLP DOI BibTeX RDF
24	Shyue-Kung Lu, Cheng-Ju Tsai, Masaki Hashizume	Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
24	Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang	Optimized Built-In Self-Repair for Multiple Memories.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
24	Itsuo Takanami, Tadayoshi Horita, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno	A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement.	Trans. Comput. Sci.	2016	DBLP DOI BibTeX RDF
24	Stefan Kristofík, Marcel Baláz	Built-in self-repair architecture generator for digital cores.	DDECS	2016	DBLP DOI BibTeX RDF
24	Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li 0001, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou	A built-in self-repair scheme for DRAMs with spare rows, columns, and bits.	ITC	2016	DBLP DOI BibTeX RDF
24	Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang	A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories.	IEEE Trans. Reliab.	2015	DBLP DOI BibTeX RDF
24	Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng	General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
24	Shyue-Kung Lu, Hao-Wei Lin, Masaki Hashizume	An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories.	ASICON	2015	DBLP DOI BibTeX RDF
24	Marcel Baláz, Stefan Kristofík, Mária Fischerová	Generic built-in self-repair architectures for SoC logic cores.	DDECS	2014	DBLP DOI BibTeX RDF
24	Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng	On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs.	ETS	2014	DBLP DOI BibTeX RDF
24	Che-Wei Chou, Yu-Jen Huang, Jin-Fu Li 0001	A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
24	Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar	Built-in Self-Repair in a 3D die stack using programmable logic.	DFTS	2013	DBLP DOI BibTeX RDF
24	Caleb Serafy, Ankur Srivastava 0001	Online TSV health monitoring and built-in self-repair to overcome aging.	DFTS	2013	DBLP DOI BibTeX RDF
24	Chih-Sheng Hou, Jin-Fu Li 0001	Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs.	VTS	2013	DBLP DOI BibTeX RDF
24	Yu-Jen Huang, Jin-Fu Li 0001	Built-In Self-Repair Scheme for the TSVs in 3-D ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2012	DBLP DOI BibTeX RDF
24	Shyue-Kung Lu, Zhen-Yu Wang, Yi-Ming Tsai, Jiann-Liang Chen	Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2012	DBLP DOI BibTeX RDF
24	Roland Dobai, Marcel Baláz, Mária Fischerová	Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC Cores.	DSD	2012	DBLP DOI BibTeX RDF
24	Michael Nicolaidis, Vladimir Pasca, Lorena Anghel	Through-silicon-via built-in self-repair for aggressive 3D integration.	IOLTS	2012	DBLP DOI BibTeX RDF
24	Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen 0053, Ching-Nen Peng, Min-Jer Wang	A memory yield improvement scheme combining built-in self-repair and error correction codes.	ITC	2012	DBLP DOI BibTeX RDF
24	Mincent Lee, Li-Ming Denq, Cheng-Wen Wu	A Memory Built-In Self-Repair Scheme Based on Configurable Spares.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
24	Chih-Sheng Hou, Jin-Fu Li 0001, Tsu-Wei Tseng	Memory Built-in Self-Repair Planning Framework for RAMs in SoCs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
24	Tobias Koal, Heinrich Theodor Vierhaus	Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair.	DDECS	2011	DBLP DOI BibTeX RDF
24	Xiaodong Wang, Dilip P. Vasudevan, Hsien-Hsin S. Lee	Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing.	3DIC	2011	DBLP DOI BibTeX RDF
24	Michael Nicolaidis, Vladimir Pasca, Lorena Anghel	I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems.	ETS	2011	DBLP DOI BibTeX RDF
24	Tobias Koal, Daniel Scheit, Mario Schölzel, Heinrich Theodor Vierhaus	On the Feasibility of Built-In Self Repair for Logic Circuits.	DFT	2011	DBLP DOI BibTeX RDF
24	Daniel Scheit	Fault-tolerant integrated interconnections based on built-in self-repair and codes.		2011	RDF
24	Tsu-Wei Tseng, Jin-Fu Li 0001, Chih-Chiang Hsu	ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
24	Tsu-Wei Tseng, Yu-Jen Huang, Jin-Fu Li 0001	DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
24	Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu	Built-In Self-Repair Schemes for Flash Memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
24	Michael Nicolaidis, Vladimir Pasca, Lorena Anghel	Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems.	IOLTS	2010	DBLP DOI BibTeX RDF
24	Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li 0001	Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost.	VTS	2010	DBLP DOI BibTeX RDF
24	Zhen-Yu Wang, Yi-Ming Tsai, Shyue-Kung Lu	Built-In Self-Repair Techniques for Heterogeneous Memory Cores.	PRDC	2009	DBLP DOI BibTeX RDF
24	Tsu-Wei Tseng, Jin-Fu Li 0001	A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs.	ITC	2008	DBLP DOI BibTeX RDF
24	Pawel Pawlowski, Adam Dabrowski, Mario Schölzel	Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair Facility via Variable Accuracy Arithmetic.	DDECS	2007	DBLP DOI BibTeX RDF
24	Tomokazu Yoneda, Yuusuke Fukuda, Hideo Fujiwara	Test Scheduling for Memory Cores with Built-In Self-Repair.	ATS	2007	DBLP DOI BibTeX RDF
24	Swapnil Bahl	A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy Schema.	DFT	2007	DBLP DOI BibTeX RDF
24	Tsu-Wei Tseng, Jin-Fu Li 0001, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen	A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs.	ITC	2006	DBLP DOI BibTeX RDF
24	Jihyun Lee, Young-Jun Lee, Yong-Bin Kim	SRAM word-oriented redundancy methodology using built in self-repair.	SoCC	2004	DBLP DOI BibTeX RDF
24	Jun Ohtani, Tukasa Ooishi, Tomoya Kawagoe, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka	A shared built-in self-repair analysis for multiple embedded memories.	CICC	2001	DBLP DOI BibTeX RDF
24	Shyue-Kung Lu, Chih-Hsien Hsu	Built-In self-repair for divided word line memory.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
24	Volker Schöber, Steffen Paul, Olivier Picot	Memory built-in self-repair using redundant words.	ITC	2001	DBLP DOI BibTeX RDF
24	Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka	A built-in self-repair analyzer (CRESTA) for embedded DRAMs.	ITC	2000	DBLP DOI BibTeX RDF
24	Ilyoung Kim, Yervant Zorian, Goh Komoriya, Hai Pham, Frank P. Higgins, Jim L. Lewandowski	Built in self repair for embedded high density SRAM.	ITC	1998	DBLP DOI BibTeX RDF
24	Pinaki Mazumder, Jih-Shyr Yih	Restructuring of square processor arrays by built-in self-repair circuit.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
24	Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey	High Level Synthesis Techniques for Efficient Built-In-Self Repair.	DFT	1993	DBLP BibTeX RDF
24	Pinaki Mazumder, Jih-Shyr Yih	A novel built-in self-repair approach to VLSI memory yield enhancement.	ITC	1990	DBLP DOI BibTeX RDF
24	Jih-Shyr Yih	Built-in self-repair of embedded VLSI arrays by electronic neural nets.		1990	RDF
24	Pinaki Mazumder, Jih-Shyr Yih	Neural computing for built-in self-repair of embedded memory arrays.	FTCS	1989	DBLP DOI BibTeX RDF
23	Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor	The State-of-Art and Future Trends in Testing Embedded Memories.	MTDT	2004	DBLP DOI BibTeX RDF
23	Liviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto	Towards Microagent based DBIST/DBISR.	ITC	2004	DBLP DOI BibTeX RDF
23	Liviu Miclea, Szilárd Enyedi, Alfredo Benso	Itelligent Agents and BIST/BISR - Working Together in Distributed Systems.	ITC	2002	DBLP DOI BibTeX RDF	distributed systems BIST, distributed BISR, Intelligent agent, self-repair, embedded testing, high-level testing
23	Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone	Design and Analysis of Self-Repairable MEMS Accelerometer.	DFT	2005	DBLP DOI BibTeX RDF
21	Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu	A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.	MTDT	2002	DBLP DOI BibTeX RDF	simulation, memory testing, embedded memory, redundancy analysis, memory repair
21	Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu	A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories.	IOLTW	2002	DBLP DOI BibTeX RDF	simulation, memory testing, embedded memory, redundancy analysis, memory repair
21	Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus	A scheme of logic self repair including local interconnects.	DDECS	2009	DBLP DOI BibTeX RDF
19	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems.	DFT	2002	DBLP DOI BibTeX RDF
17	Uthman Alsaiari, Resve A. Saleh	Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy.	ISQED	2007	DBLP DOI BibTeX RDF