Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
121 | A. B. M. Harun-ur Rashid, Mazuhidul Karim, Syed Mahfuzul Aziz |
Testing complementary pass-transistor logic circuits. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
104 | Simon Kramer 0001 |
Logical concepts in cryptography. |
SIGACT News |
2007 |
DBLP DOI BibTeX RDF |
applied formal logic, information security |
104 | Masahide Nakamura, Pattara Leelaprute, Ken-ichi Matsumoto, Tohru Kikuno |
Semantic Warnings and Feature Interaction in Call Processing Language on Internet Telephony. |
SAINT |
2003 |
DBLP DOI BibTeX RDF |
|
87 | Leon Bobrowski |
Ranked Modelling with Feature Selection Based on the CPL Criterion Functions. |
MLDM |
2005 |
DBLP DOI BibTeX RDF |
Ranked linear models, convex and piecewise linear (CPL) criterion functions, linear separability of data sets, feature selection |
79 | Leon Bobrowski |
CPLClustering with Feature Costs. |
ICDM |
2008 |
DBLP DOI BibTeX RDF |
convex and piecewise linear (CPL) criterion functions, linear dependence of feature vectors, feature selection |
69 | Saswat Anand, Wei-Ngan Chin, Siau-Cheng Khoo |
Charting Patterns on Price History. |
ICFP |
2001 |
DBLP DOI BibTeX RDF |
Haskell |
61 | Issam S. Abu-Khater, Abdellatif Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan |
Circuit/architecture for low-power high-performance 32-bit adder. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
conditional sum architecture, CPL-like logic implementation, power supply voltage, minimum size, optimized speed, 1 to 3.3 V, logic design, CMOS, integrated circuit design, adders, adder, CMOS logic circuits, circuit optimisation, 32 bit |
60 | Santi Phithakkitnukoon, Ram Dantu |
CPL: Enhancing Mobile Phone Functionality by Call Predicted List. |
OTM Workshops |
2008 |
DBLP DOI BibTeX RDF |
Call prediction, Mobile phone, Context-aware computing |
60 | Yuanzhong Wan, Maitham Shams |
Delay modeling of CMOS/CPL logic circuits. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Leon Bobrowski |
Ranked linear models and sequential patterns recognition. |
Pattern Anal. Appl. |
2009 |
DBLP DOI BibTeX RDF |
Ranked linear transformations, Convex and piecewise linear (CPL) criterion functions, Linear separability of data sets, Feature selection, Sequential patterns |
43 | Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy 0001 |
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
DSM leakage control and scaling trends, dual supply ALU design, low power techniques |
35 | Maja Loncar, Fredrik Rusek |
On Reduced-Complexity Equalization Based on Ungerboeck and Forney Observation Models. |
IEEE Trans. Signal Process. |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Leon Bobrowski, Magdalena Topczewska |
Induction of Similarity Measures for Case Based Reasoning Through Separable Data Transformations. |
Case-Based Reasoning on Images and Signals |
2008 |
DBLP DOI BibTeX RDF |
|
35 | B. John Oommen, Govindachari Raghunath, Benjamin Kuipers |
On How to Learn from a Stochastic Teacher or a Stochastic Compulsive Liar of Unknown Identity. |
Australian Conference on Artificial Intelligence |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Abdoul Rjoub, M. Alrousan, Omar M. Al-Jarrah, Odysseas G. Koufopavlou |
Multi-level low swing voltage values for low power design applications. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Roger Hartley, Heather Pfeiffer |
Visual Representation of Procedural Knowledge. |
VL |
2000 |
DBLP DOI BibTeX RDF |
|
35 | Abdoul Rjoub, Odysseas G. Koufopavlou |
Low voltage swing gates for low power consumption. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
35 | Hartmut Liefke, Susan B. Davidson |
Specifying Updates in Biomedical Databases. |
SSDBM |
1999 |
DBLP DOI BibTeX RDF |
complex value databases, optimization, object-oriented databases, updates, rewriting, biological databases |
35 | David Harel, Eli Singerman |
Computation Paths Logic: An Expressive, yet Elementary, Process Logic (abridged version). |
ICALP |
1997 |
DBLP DOI BibTeX RDF |
|
28 | Olivier Danvy, J. Michael Spivey |
On Barron and Strachey's cartesian product function. |
ICFP |
2007 |
DBLP DOI BibTeX RDF |
CPL |
28 | Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao |
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
CPL, conditional sum adder, low-threshold voltage, differential-end, VLSI design, low-voltage |
27 | Leon Bobrowski, Ralph C. Huntsinger |
Exploring the linearity of models on the basis of ranked data. |
SCSC |
2007 |
DBLP BibTeX RDF |
convex and piecewise linear (CPL) criterion functions, multiparameter optimization, ranked relations, linear transformations, linear separability |
25 | Md. Imran Kalim, Ahmad Ali |
Maximum Sensitivity Constrained Graphical Controller Tuning for a DC-DC Boost Converter Loaded With a CPL. |
IEEE Trans. Ind. Electron. |
2024 |
DBLP DOI BibTeX RDF |
|
25 | Lanfeng Zhong, Xin Liao, Shaoting Zhang 0001, Xiaofan Zhang, Guotai Wang |
VLM-CPL: Consensus Pseudo Labels from Vision-Language Models for Human Annotation-Free Pathological Image Classification. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
25 | Zihao He, Jonathan May, Kristina Lerman |
CPL-NoViD: Context-Aware Prompt-based Learning for Norm Violation Detection in Online Communities. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Andrew Rouditchenko, Ronan Collobert, Tatiana Likhomanenko |
AV-CPL: Continuous Pseudo-Labeling for Audio-Visual Speech Recognition. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Federico Martin Serra, W. Gil-Gonzalez, Oscar D. Montoya, Jesús C. Hernández |
Voltage Regulation in a Buck Converter for an Unknown CPL: An Extended Feedback Control Design. |
LASCAS |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Hussain Sarwar Khan, Kimmo Kauhaniemi |
FPGA Validated Advanced Learning-Based Voltage Control of DC/DC Converter Feeding CPL in DC Microgrid Applications. |
ISIE |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Xuehai He, Diji Yang, Weixi Feng, Tsu-Jui Fu, Arjun R. Akula, Varun Jampani, Pradyumna Narayana, Sugato Basu, William Yang Wang, Xin Eric Wang |
CPL: Counterfactual Prompt Learning for Vision and Language Models. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Xuehai He, Diji Yang, Weixi Feng, Tsu-Jui Fu, Arjun R. Akula, Varun Jampani, Pradyumna Narayana, Sugato Basu, William Yang Wang, Xin Wang 0061 |
CPL: Counterfactual Prompt Learning for Vision and Language Models. |
EMNLP |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Abdelali El Aroudi, Mohammed S. Al-Numay, Reham Haroun, Guidong Zhang |
Analytical Determination of Fast-Scale Instability Boundaries for Current Mode Controlled DC-DC Converters With CPL and Closed Voltage Loop. |
IEEE J. Emerg. Sel. Topics Circuits Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Milad Andalibi, Mojtaba Hajihosseini, Meysam Gheisarnejad, Mohammad Hassan Khooban, Jalil Boudjadar |
A Novel Method for Stabilizing Buck-Boost Converters with CPL using Model Prediction Control. |
ICIT |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Edward Ronald Smith, D. J. Trevelyan, Eduardo Ramos Fernandez, Adnan Sufian, Catherine O'Sullivan, Daniele Dini |
CPL library - A minimal framework for coupled particle and continuum simulation. |
Comput. Phys. Commun. |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Cheonghwan Hur, Bunyodbek Ibrokhimov, Sanggil Kang |
N3-CPL: Neuroplasticity-based neuromorphic network cell proliferation learning. |
Neurocomputing |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Taosha Fan, Hanlin Wang, Michael Rubenstein, Todd D. Murphey |
CPL-SLAM: Efficient and Certifiably Correct Planar Graph-Based SLAM Using the Complex Number Representation. |
IEEE Trans. Robotics |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Paolo Luchini |
Introducing CPL. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
25 | Taosha Fan, Hanlin Wang, Michael Rubenstein, Todd D. Murphey |
CPL-SLAM: Efficient and Certifiably Correct Planar Graph-Based SLAM Using the Complex Number Representation. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
25 | Hamed Farsizadeh, Meysam Gheisarnejad, Mahdi Mosayebi, Mehdi Rafiei, Mohammad Hassan Khooban |
An Intelligent and Fast Controller for DC/DC Converter Feeding CPL in a DC Microgrid. |
IEEE Trans. Circuits Syst. II Express Briefs |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Kevin Eduardo Lucas Marcillo, Douglas A. Plaza-Guingla, Walter Barra Junior, Renan Landau Paiva de Medeiros, Erick Melo Rocha, David Alejandro Vaca Benavides, Sara Judith Rios Orellana, Efren Vinicio Herrera Muentes |
Novel Robust Methodology for Controller Design Aiming to Ensure DC Microgrid Stability Under CPL Power Variation. |
IEEE Access |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Wei Jin, Yuping Lu, Tao Huang |
Improved Blocking Scheme for CPL Current Protection in Wind Farms Using the Amplitude Ratio and Phase Difference. |
IEEE Access |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Nengjun Zhu, Jian Cao 0001 |
CPL: A Combined Framework of Pointwise Prediction and Learning to Rank for top-N Recommendations with Implicit Feedback. |
WISE |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Aleksandra Grzelak, Dorota Leszczynska-Jasion |
Automatic proof generation in an axiomatic system for $$\mathsf{CPL}$$ by means of the method of Socratic proofs. |
Log. J. IGPL |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Wei He 0001, Carlos Abraham Soriano-Rangel, Romeo Ortega, Alessandro Astolfi, Fernando Mancilla-David, Shihua Li 0001 |
DC-DC Buck-Boost Converters with Unknown CPL: An Adaptive PBC. |
ACC |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Sergey Budkov, Kseniya Buraya, Andrey Filchenkov, Ivan Smetannikov, Antonina Puchkovskaia |
RICH-CPL: Fact Extraction from Wikipedia-sized Corpora for Morphologically Rich Languages. |
FRUCT |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Kuen-Suan Chen, Kung-Jeng Wang, Tsang-Chuan Chang |
A novel approach to deriving the lower confidence limit of indices Cpu, Cpl, and Cpk in assessing process capability. |
Int. J. Prod. Res. |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Tadeusz Litak, Dirk Pattinson, Katsuhiko Sano, Lutz Schröder |
Model Theory and Proof Theory of CPL. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
25 | Oliver Bracevac, Sebastian Erdweg, Guido Salvaneschi, Mira Mezini |
CPL: A Core Language for Cloud Computing - Technical Report. |
CoRR |
2016 |
DBLP BibTeX RDF |
|
25 | Oliver Bracevac, Sebastian Erdweg, Guido Salvaneschi, Mira Mezini |
CPL: a core language for cloud computing. |
MODULARITY |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Tanguy Ropitault |
Routage et performances dans les réseaux CPL pour le Smart Grid. (Routing and performance for the Smart Grid). |
|
2015 |
RDF |
|
25 | Hedong Yang, Lijie Wen, Jianmin Wang 0001, Raymond K. Wong 0001 |
CPL+: An improved approach for evaluating the local completeness of event logs. |
Inf. Process. Lett. |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Qiguo Dai, Mao-Zu Guo 0001, Xiao-Yan Liu, Zhixia Teng, Chunyu Wang |
CPL: Detecting Protein Complexes by Propagating Labels on Protein-Protein Interaction Network. |
J. Comput. Sci. Technol. |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Leon Bobrowski |
Discovering Main Vertexical Planes in a Multivariate Data Space by Using CPL Functions. |
ICDM |
2014 |
DBLP DOI BibTeX RDF |
|
25 | David Hartley |
CPL: Failed Venture or Noble Ancestor? |
IEEE Ann. Hist. Comput. |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Martin Richards |
How BCPL Evolved from CPL. |
Comput. J. |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Manoj Sharma, Arti Noor |
CPL-Adiabatic Gated logic (CPLAG) XOR gate. |
ICACCI |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Leon Bobrowski |
CPL Criterion Functions and Learning Algorithms Linked to the Linear Separability Concept. |
EANN (1) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | De-Shuang Huang, Wen Jiang |
A General CPL-AdS Methodology for Fixing Dynamic Parameters in Dual Environments. |
IEEE Trans. Syst. Man Cybern. Part B |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Mingoo Seok |
Performance and energy-efficiency improvement through modified CPL in organic transistor integrated circuits. |
ISLPED |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Rehan Hashmat |
Characterization and Modeling of the Channel and Noise for Indoor MIMO PLC Networks. (Caractérisation et modélisation du canal et du bruit pour les réseaux CPL MIMO domestiques). |
|
2012 |
RDF |
|
25 | Leon Bobrowski |
CPL Clustering Based on Linear Dependencies. |
Simul. Notes Eur. |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Abdoul Rjoub, Al-Mamoon Al-Othman |
The Influence of the Nanometer Technology on Performance of CPL Full Adders. |
J. Comput. |
2010 |
DBLP BibTeX RDF |
|
25 | Jianping Hu, Binbin Liu |
Energy Efficient Medium-Voltage Circuits Based on Adiabatic CPL. |
ISIA |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Leon Bobrowski |
Selection of High Risk Patients with Ranked Models Based on the CPL Criterion Functions. |
ICDM |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Lixiang Wang, Jiuyun Xu, Stephan Reiff-Marganiec |
Online Detection of Feature Interactions of CPL Services. |
ICFI |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Yiqun Xu, Luigi Logrippo, Jacques Sincennes |
Detecting feature interactions in CPL. |
J. Netw. Comput. Appl. |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Nicolas Gorse, Luigi Logrippo, Jacques Sincennes |
Detecting feature interaction in CPL. |
Softw. Syst. Model. |
2006 |
DBLP DOI BibTeX RDF |
Telephony software, Detection method, Feature interaction, Formal techniques |
25 | Dongmei Jiang, Ramiro Liscano, Luigi Logrippo |
Personalization of internet telephony services for presence with SIP and extended CPL. |
Comput. Commun. |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Jonathan Lennox, Xiaotao Wu, Henning Schulzrinne |
Call Processing Language (CPL): A Language for User Control of Internet Telephony Services. |
RFC |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Wen Lea Pearn, Ming-Hung Shu |
An algorithm for calculating the lower confidence bounds of CPU and CPL with application to low-drop-out linear regulators. |
Microelectron. Reliab. |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Wen Lea Pearn, Ming-Hung Shu |
Erratum to "An algorithm for calculating the lower confidence bounds of CPU and CPL with application to low-drop-out linear regulators" [Microelectronics Reliability 2003;43: 495-502]. |
Microelectron. Reliab. |
2003 |
DBLP DOI BibTeX RDF |
|
25 | José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas |
Practical low-cost CPL implementations threshold logic functions. |
ACM Great Lakes Symposium on VLSI |
2001 |
DBLP DOI BibTeX RDF |
|
25 | David Hartley |
Cambridge and CPL in the 1960s. |
High. Order Symb. Comput. |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Martin Richards |
Christopher Strachey and the Cambridge CPL Compiler. |
High. Order Symb. Comput. |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Abdoul Rjoub, Odysseas G. Koufopavlou |
Multiple low swing voltage values for CPL, CVSL and domino logic families. |
ICECS |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Mihai Munteanu, Peter A. Ivey, Nicholas Luke Seed, Marios Psilogeorgopoulos, Neil Powell, Istvan Bogdan |
Single Ended Pass-Transistor Logic - A Comparison with CMOS and CPL. |
VLSI |
1999 |
DBLP BibTeX RDF |
|
25 | Eyal Mozes |
CPL: a tool for planning with multiple considerations. |
|
1993 |
RDF |
|
25 | Peter Lundén |
Sound-Models: The Representation of Knowledge about Sound-Synthesis in the CPL Environment. |
ICMC |
1991 |
DBLP BibTeX RDF |
|
25 | David W. Barron, John N. Buxton, David F. Hartley, Eric Nixon, Christopher S. Strachey |
The Main Features of CPL. |
Comput. J. |
1963 |
DBLP DOI BibTeX RDF |
|
17 | João P. Papa, Alexandre X. Falcão |
A Learning Algorithm for the Optimum-Path Forest Classifier. |
GbRPR |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Sundeepkumar Agarwal, Pavankumar V. K., Yokesh R. |
Energy-Efficient, High Performance Circuits for Arithmetic Units. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Riccardo Pucella |
Introduction. |
SIGACT News |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Mandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija |
Logic Style Comparison for Ultra Low Power Operation in 65nm Technology. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Tarashankar Rudra, David Tien, Terry Bossomaier |
Spoken Communication with Computer Game Characters. |
ICITA (1) |
2005 |
DBLP DOI BibTeX RDF |
pidgin, XML, Games |
17 | Leon Bobrowski |
Linear Ranked Regression - Designing Principles. |
CORES |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Yuanzhong Wan, Maitham Shams |
Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Leon Bobrowski, Tomasz Lukaszuk |
Selection of the Linearly Separable Feature Subsets. |
ICAISC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy 0001 |
Low-power carry-select adder using adaptive supply voltage based on input vector patterns. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
adaptive supply voltage, low power adder, carry-select adder |
17 | Pattara Leelaprute, Masahide Nakamura, Ken-ichi Matsumoto, Tohru Kikuno |
Evaluating Semantic Warnings in VoIP Programmable Services with Open Source Environment. |
APSEC |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Abhijit S. Pandya, Ankur Agarwal, Pyeoung Kee Kim |
Low Power Design of the Neuroprocessor. |
KES |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Massimo Alioto, Gaetano Palumbo |
Analysis and comparison on full adder block in submicron technology. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Viji Srinivasan, David M. Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma |
Optimizing pipelines for power and performance. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Kenneth J. Turner |
Modelling SIP Services Using CRESS. |
FORTE |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Natalia Kazakova, Raymond J. Sung, Nelson G. Durdle, Martin Margala, Julien Lamoureux |
Fast and low-power inner product processor. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Limsoon Wong |
The functional guts of the Kleisli query system. |
ICFP |
2000 |
DBLP DOI BibTeX RDF |
|
17 | David Zhang 0001, Mohamed I. Elmasry |
VLSI compressor design with applications to digital neural networks. |
IEEE Trans. Very Large Scale Integr. Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Uming Ko, T. Balsara, Wai Lee |
Low-power design techniques for high-performance CMOS adders. |
IEEE Trans. Very Large Scale Integr. Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Debabrata Ghosh, S. K. Nandy 0001 |
Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. |
IEEE Trans. Very Large Scale Integr. Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Sanjay Rekhi, J. Donald Trotter |
HAL: heuristic algorithms for layout synthesis. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area |