Search results for "CPLD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
127	Valeri Solovjev	Refined CPLD Macrocell Architecture for the Effective FSM Implementation.	EUROMICRO	1999	DBLP DOI BibTeX RDF
83	Jae-Jin Kim, Hi-Seok Kim, Chi-Ho Lin	A new techology mapping for CPLD under the time constraint.	ASP-DAC	2001	DBLP DOI BibTeX RDF	feasible cluster, number of multi-level, technology mapping for CPLD, time constraint
83	Bernardo Kastrup, Arjan Bink, Jan Hoogerbrugge	ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator.	FCCM	1999	DBLP DOI BibTeX RDF	XPLA, compilers, static-analysis, computer-architecture, reconfigurable-computing, compiler-optimizations, hardware-acceleration, programmable-logic, CPLD, custom-instructions
77	Shi Yu Yan, Ji Zhou Li	Research on the DDS' CPLD Control to Generate Special Band Signal.	BMEI (2)	2008	DBLP DOI BibTeX RDF
74	Nikolay Kostadinov, Anelia Ivanova	A VHDL training model of a processor.	CompSysTech	2007	DBLP DOI BibTeX RDF	CPLD implementation, VHDL model, processor, instruction set
66	Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang	Performance-driven mapping for CPLD architectures.	FPGA	2001	DBLP DOI BibTeX RDF	PLA-style logic cells, FPGA, technology mapping, CPLD, delay optimization
66	Yasumasa Hayashi, Takashi Matsubara 0002, Yoshiaki Koga	Implementation and evaluation for dependable bus control using CPLD.	PRDC	2000	DBLP DOI BibTeX RDF	phase control, dependable bus control, bus systems, dependable bus operations, bus phase control, reliability, dependability, sequential circuits, system buses, CPLD, asynchronous sequential logic, asynchronous sequential circuit
60	Faizal Arya Samman, Eniman Y. Syamsuddin	Programmable fuzzy logic controller circuit on CPLD chip.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
57	Pai-Shan Pa, C. M. Wu	The New Design of Digital Servo Robot Controller.	ICIRA (2)	2008	DBLP DOI BibTeX RDF	Servo, Robot, Toy, CPLD, PWM, Single Chip
57	Mark Holland, Scott Hauck	Improving performance and robustness of domain-specific CPLDs.	FPGA	2006	DBLP DOI BibTeX RDF	computer-aided design, system-on-a-chip, reconfigurable logic, CPLD, sparse crossbar
51	Chun-Chieh Wang, Juhng-Perng Su	Fuzzy Gain Scheduled Integral Control and Its Application to a Hovercraft Vessel with Uncertainties.	ICICIC (1)	2006	DBLP DOI BibTeX RDF
51	Zhifeng Diao, Dongxu Shen, Victor O. K. Li	A channel-condition and packet-length dependent scheduler in wireless OFDM systems.	VTC Fall (2)	2004	DBLP DOI BibTeX RDF
49	Gerhard Grießnig, Roland Mader, Christian Steger, Reinhold Weiss	Design and Implementation of Safety Functions on a Novel CPLD-Based Fail-Safe System Architecture.	ECBS	2010	DBLP DOI BibTeX RDF	safety-critical embedded system, fail-safe system, safety function, safety, CPLD, IEC 61508
43	Junmei Zhang, Wenbin Li 0004, Chao Sa, Deming Wang, Dongxu Cui	CPLD-based optimal control for wireless remote control pruning machine.	CSCWD	2009	DBLP DOI BibTeX RDF
43	Junmei Zhang, Wenbin Li 0004, Chao Sa, Deming Wang, Patrick S. K. Chua, F. L. Tan	Development of a CPLD Based Wireless Remote Control System of Pruning Machine for Plantation Forest.	CSCWD	2007	DBLP DOI BibTeX RDF
43	Dariusz Kania	Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition.	EUROMICRO	1999	DBLP DOI BibTeX RDF
40	Dimitrios Lymberopoulos, Nissanka Bodhi Priyantha, Feng Zhao 0001	mPlatform: a reconfigurable architecture and efficient data sharing mechanism for modular sensor nodes.	IPSN	2007	DBLP DOI BibTeX RDF	high speed data bus, reconfigurable sensor node, CPLD, modular architecture
34	Mark Holland, Scott Hauck	Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
34	Dariusz Kania	A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	logic synthesis, technology mapping, CPLDs
34	Dariusz Kania, Józef Kulisz, Adam Milik	A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs.	DSD	2005	DBLP DOI BibTeX RDF
34	Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic	Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices.	FPL	2002	DBLP DOI BibTeX RDF
34	K. K. Lee, D. F. Wong 0001	LRoute: a delay minimal router for hierarchical CPLDs.	FPGA	2001	DBLP DOI BibTeX RDF	complex programmable logic devices, routing, hierarchical model, Lagrangian relaxation
34	Francisco Ibarra Picó, Sergio Cuenca-Asensi	An Associative Neural Network and Its Special Purpose Pipeline Architecture in Image Analysis.	IWANN (2)	1999	DBLP DOI BibTeX RDF	Topics Computer vision, real-time quality control, neural nets, texture recognition
34	James O. Hamblen, Gregory E. Ruhl	Using the Altera UP-1 Board for Prototyping and VGA Video Display Generation.	MSE	1999	DBLP DOI BibTeX RDF
34	Valeri Solovjev, Mariusz Chyzy	The Universal Algorithm for Fitting Targeted to Complex Programmable Logic Devices.	EUROMICRO	1999	DBLP DOI BibTeX RDF
26	Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski	Design of CPLD-based mealy FSMs with counters.	MOCAST	2018	DBLP DOI BibTeX RDF
26	Hong Chen, Zhifan Du, Xin Liu, Yu Meng	A New Method for Observing the Bifurcation of a Nonlinear System Based on CPLD.	J. Inf. Hiding Multim. Signal Process.	2017	DBLP BibTeX RDF
26	Shaowei Li, Shengzheng Wang	Design Method for Ship Handling Simulator Based On CPLD.	ICNCC	2017	DBLP DOI BibTeX RDF
26	Alexander Barkalov 0001, Larysa Titarenko, Jacek Bieganowski	Code sharing in CPLD-based Moore FSMs.	MOCAST	2017	DBLP DOI BibTeX RDF
26	Fabao Yan, Yan-Rui Su, Jian-Xin Liu	The Method of Real-Time Data Weighting Operations of CPLD/FPGA in Measurement Systems.	J. Commun.	2015	DBLP DOI BibTeX RDF
26	Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski	Hardware Reduction in CPLD-Based Moore FSM.	J. Circuits Syst. Comput.	2014	DBLP DOI BibTeX RDF
26	Alexander Barkalov 0001, Larysa Titarenko, Lukasz Smolinski	Hardware reduction for compositional microprogram control unit dedicated for CPLD systems.	EWDTS	2013	DBLP DOI BibTeX RDF
26	Chien-Nan Lee	An intelligent sprinkler based on CPLD.	ICMLC	2013	DBLP DOI BibTeX RDF
26	Javier García-Zubía, Ignacio Angulo, Pablo Orduña, Unai Hernández, Diego López-de-Ipiña, Luis Rodriguez, Olga Dziabenko, Verónica Canivell	WebLab-Deusto-CPLD: A Practical Experience.	Int. J. Online Eng.	2012	DBLP DOI BibTeX RDF
26	Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski	Synthesis of control unit with refined state encoding for CPLD devices.	EWDTS	2011	DBLP DOI BibTeX RDF
26	Ziga Matjasec, Denis Donlagic	An optical signal processing device for white-light interferometry, based on CPLD.	MIPRO	2011	DBLP BibTeX RDF
26	Traian Tulbure	A Dynamic Reconfigurable CPLD Architecture for Structured ASIC Technology.	ARC	2011	DBLP DOI BibTeX RDF
26	Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski	Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD.	EWDTS	2010	DBLP DOI BibTeX RDF
26	Yang Yang, Yanqing Zhao	Application of CPLD in Pulse Power for EDM.	CCTA (4)	2010	DBLP DOI BibTeX RDF
26	Xinlei Li, Gang Liu, Mingming Guo, Yin Liu, Fei Yang	A Circuit Module and CPLD Laser Ground Controller Based on RS485.	CCTA (3)	2010	DBLP DOI BibTeX RDF
26	Jianjun Ding, Xihua Wang, Chao Sun	The Application of CPLD and ARM in Food Safety Testing Data Fusion.	CCTA (3)	2010	DBLP DOI BibTeX RDF
26	S. Raveendran, P. Talwai, T. Khan, R. Balasubramanian, K. Agilandaeswari	Design of IOIM for VME bus based CPU using CPLD for nuclear power plants.	ICWET	2010	DBLP DOI BibTeX RDF
26	Sid-Ahmed Benali Senouci	Physical Synthesis for CPLD Architectures.	CIIA	2009	DBLP BibTeX RDF
26	Gerhard Grießnig, Roland Mader, Christian Steger, Reinhold Weiss	Fault insertion testing of a novel CPLD-based fail-safe system.	DATE	2009	DBLP DOI BibTeX RDF
26	Robert Czerwinski, Dariusz Kania	CPLD-oriented Synthesis of Finite State Machines.	DSD	2009	DBLP DOI BibTeX RDF
26	Joydeb Roy Choudhury, Tribeni Prasad Banerjee, A. Nathvani, Rangeen Basu Roy Chowdhury, A. K. Bhattacharya	Design Methodology Internal Sub State Observer using CPLD.	NaBIC	2009	DBLP DOI BibTeX RDF
26	Ketan J. Raut, Pankaj Bande, Manish M. Patil	A Novel Prototype for Obstacle Detection and Relative Speed Control of an Automotive Using CPLD.	ICETET	2008	DBLP DOI BibTeX RDF
26	Jyung Hyun Lee, Yeon Kwan Moon, YoungHo Yoon, Hee Joon Park, Chul-Ho Won, Hyun-Chul Choi, Jin-Ho Cho	CPLD Based Bi-Directional Wireless Capsule Endoscopes.	IEICE Trans. Inf. Syst.	2007	DBLP DOI BibTeX RDF
26	Choong-Mo Youn	Digital Sequence CPLD Technology Mapping Algorithm.	J. Inform. and Commun. Convergence Engineering	2007	DBLP BibTeX RDF
26	Choong-Mo Youn, Jae-Jin Kim	A CLB-based CPLD Low-power Technology Mapping Algorithm considered a Trade-off.	J. Inform. and Commun. Convergence Engineering	2007	DBLP BibTeX RDF
26	Dariusz Kania, Józef Kulisz	Logic synthesis for PAL-based CPLD-s based on two-stage decomposition.	J. Syst. Softw.	2007	DBLP DOI BibTeX RDF
26	Jyung Hyun Lee, Yeon Kwan Moon, Sang Hyo Woo, Chang Wook Kim, Hee Joon Park, Jong Sik Jin, Chul-Ho Won, Hyun-Chul Choi, Yoon Nyun Kim, Jin-Ho Cho	Design & Implementation of CPLD Controller for Bi-directional VGA Capsule Endoscop.	BIOCOMP	2007	DBLP BibTeX RDF
26	Zhifeng Diao, Dongxu Shen, Victor O. K. Li	CPLD-PGPS scheduler in wireless OFDM systems.	IEEE Trans. Wirel. Commun.	2006	DBLP DOI BibTeX RDF
26	Eftichios Koutroulis 0001, Apostolos Dollas, Kostas Kalaitzakis	High-frequency pulse width modulation implementation using FPGA and CPLD ICs.	J. Syst. Archit.	2006	DBLP DOI BibTeX RDF
26	Chin-Wen Chuang, Liang-Cheng Shiu	CPLD based DIVSC of hydraulic position control systems.	Comput. Electr. Eng.	2004	DBLP DOI BibTeX RDF
26	Mile K. Stojcev, Goran Lj. Djordjevic, Tatjana R. Stankovic	Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
26	Zhifeng Diao, Dongxu Shen, Victor O. K. Li	CPLD-PGPS scheduling algorithm in wireless OFDM systems.	GLOBECOM	2004	DBLP DOI BibTeX RDF
26	Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis	MAX II: A low-cost, high-performance LUT-based CPLD.	CICC	2004	DBLP DOI BibTeX RDF
26	Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang	Performance-driven mapping for CPLD architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
26	Shih-Liang Chen, TingTing Hwang, C. L. Liu 0001	A technology mapping algorithm for CPLD architectures.	FPT	2002	DBLP DOI BibTeX RDF
26	Roberto Sepúlveda, Oscar Montiel, Patricia Melin	Fuzzy Control Embedded in a CPLD for Testing Batteries.	IC-AI	2002	DBLP BibTeX RDF
26	Wan-De Weng, Wen Pin Yang	The CPLD implementation of Viterbi algorithm in grand alliance ATSC systems.	IEEE Trans. Ind. Electron.	2001	DBLP DOI BibTeX RDF
26	Andrew Kennings, Haneef Mohammed, Joseph P. Skudlarek, Bing Tian	Cypress Delta39KTM. A memory-rich, high performance, scalable CPLD architecture.	CICC	2000	DBLP DOI BibTeX RDF
26	J. Living, Bashir M. Al-Hashimi	Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
26	Ali Benkhalil, Stanley S. Ipson, William Booth	A novel CPLD based implementation of a motion detection algorithm for surveillance applications.	CICC	1998	DBLP DOI BibTeX RDF
26	Stephen Dean Brown, Jonathan Rose	FPGA and CPLD Architectures: A Tutorial.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
23	Guochen An, Zhiyong Meng, Xiaojun Wang	Design of Grounding Resistance Measurement System Based on DSP.	APWCS	2010	DBLP DOI BibTeX RDF	grounding resistance, alien frequencies, DSP, CPLD, measuring method
23	Yinke Dou, Jianmin Qin, Xiaomin Chang	The Study of a Capacitance Sensor and its System Used in Measuring Ice Thickness, Sedimentation and Water Level of a Reservoir.	IFITA (3)	2009	DBLP DOI BibTeX RDF	Multi-electrode Capacitance, Ice thickness, water level, CPLD, Sedimentation
23	Hongli Tian, Shuo Shi, Jun Zhang, Hongdong Zhao	Controllable Arbitrary Integer Frequency Divider Based on VHDL.	JCAI	2009	DBLP DOI BibTeX RDF	50% duty cycle, frequency divider, FPGA, VHDL, CPLD
23	Jason Cong, Hui Huang 0001, Xin Yuan 0005	Technology mapping and architecture evalution for k/m-macrocell-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	FPGA, technology mapping, CPLD, PLD
23	Steve Ferrera, Nicholas P. Carter	A magnetoelectronic macrocell employing reconfigurable threshold logic.	FPGA	2004	DBLP DOI BibTeX RDF	PLA/CPLD, magnetoelectronic circuits, wired-and logic, threshold logic, lookup table, non-volatility
23	Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor	Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer
17	Liu Weiguang, Wang Wenqi, Cui Jiangtao	A New Scheme for Multisensor Image Fusion System.	IAS	2009	DBLP DOI BibTeX RDF
17	Yaohua Sun, Ting Zhu 0001, Ziguo Zhong, Tian He 0001	Energy profiling for mPlatform.	SenSys	2009	DBLP DOI BibTeX RDF	TwinStar, energy profiling, mPlatform, ultra-capacitor, energy harvesting
17	Gang Wang, Du Chen, Jian Chen, Jianliang Ma, Tianzhou Chen	A Performance Model for Run-Time Reconfigurable Hardware Accelerator.	APPT	2009	DBLP DOI BibTeX RDF
17	Jian-hua Qiao, Lin-sheng Li, Jinggang Zhang	Design of Rail Surface Crack-detecting System Based on Linear CCD Sensor.	ICNSC	2008	DBLP DOI BibTeX RDF
17	Falk Salewski, Stefan Kowalewski	Achieving Highly Reliable Embedded Software: An Empirical Evaluation of Different Approaches.	SAFECOMP	2007	DBLP DOI BibTeX RDF
17	Bharath Balaji Kannan, Khai D. T. Ngo	Digital Inverse Timing Generator with Wide Dynamic Range.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Jiazhong Xu, Bo You, Deli Jia, Dongjie Li	Motion Synchronization System of Filament Winding Machine.	ICICIC (1)	2006	DBLP DOI BibTeX RDF
17	Muhammad N. Marsono, M. Watheq El-Kharashi, Fayez Gebali	Binary LNS-based naive Bayes hardware classifier for spam control.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle	An automated, reconfigurable, low-power RFID tag.	DAC	2006	DBLP DOI BibTeX RDF
17	André DeHon	Design of programmable interconnect for sublithographic programmable logic arrays.	FPGA	2005	DBLP DOI BibTeX RDF	Manhattan mesh, sublithographic architecture, programmable logic arrays, nanowires, programmable interconnect
17	Mike Hutton	Architecture and CAD for FPGAs.	SBCCI	2004	DBLP DOI BibTeX RDF
17	Seyed Reza Abdollahi, Bertan Bakkaloglu, S. K. Hosseini	A Fully Digital Numerical-Controlled-Oscillator.	PATMOS	2003	DBLP DOI BibTeX RDF
17	Christian Siemers, Volker Winterstein	Modelling Programmable Logic Devices and Reconfigurable, Microprocessor-Related Architectures.	IPDPS	2003	DBLP DOI BibTeX RDF
17	Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang	Combinational circuit fault diagnosis using logic emulation.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
17	Songpol Ongwattanakul, Phaisit Chewputtanagul, David Jeff Jackson, Kenneth G. Ricks	Scalable giga-pixels/s binary image morphological operations.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
17	Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni	Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor.	FPL	2002	DBLP DOI BibTeX RDF
17	Cyprian Grassmann, Joachim K. Anlauf	RACER - A Rapid Prototyping Accelerator for Pulsed Neural Networks.	FCCM	2002	DBLP DOI BibTeX RDF
17	Seyed Reza Abdollahi, Sayfe Kiaei, Bertan Bakkaloglu, Seid Mehdi Fakhraie, R. Anvari, Seyed Ehsan Abdollahi	An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
17	Dariusz Kania	Decomposition-Based Synthesis and its Application in PAL-Oriented Technology Mapping.	EUROMICRO	2000	DBLP DOI BibTeX RDF
17	Deni Torres, J. Gonzalez, Manuel Guzman, L. Nuñez	A new bus assignment in a designed shared bus switch fabric.	ISCAS (1)	1999	DBLP DOI BibTeX RDF