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Searching for phrase Chip-multiprocessor (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1991-1999 (24) 2000-2001 (17) 2002-2003 (29) 2004 (22) 2005 (34) 2006 (65) 2007 (71) 2008 (70) 2009 (50) 2010 (37) 2011 (16) 2012-2013 (20) 2014-2015 (24) 2016-2018 (16) 2019-2021 (8)
Publication types (Num. hits)
article(109) incollection(1) inproceedings(387) phdthesis(6)
Venues (Conferences, Journals, ...)
MICRO(21) ISCA(18) ASPLOS(14) Conf. Computing Frontiers(14) IEEE Trans. Computers(14) ICCD(12) PACT(12) DATE(11) IPDPS(11) HPCA(10) CODES+ISSS(9) ISLPED(8) SIGARCH Comput. Archit. News(7) CASES(6) IEEE Micro(6) IEEE PACT(6) More (+10 of total 192)
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Found 503 publication records. Showing 503 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
53Satoshi Matsushita Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
51Michael Gschwind The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor. Search on Bibsonomy Int. J. Parallel Program. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF compute-transfer parallelism, multi-level application parallelism, Chip multiprocessor, Cell Broadband Engine, heterogeneous chip multiprocessor
50Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF secure mobile terminal, chip multiprocessor, linux
48Slo-Li Chu Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture. Search on Bibsonomy LCPC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Critical Block Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
45Sebastian Herbert, Diana Marculescu Characterizing chip-multiprocessor variability-tolerance. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF frequency islands, chip-multiprocessor, process variability
45Slo-Li Chu Toward to Utilize the Heterogeneous Multiple Processors of the Chip Multiprocessor Architecture. Search on Bibsonomy EUC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Swing Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
45Taeho Kgil, Shaun D'Souza, Ali G. Saidi, Nathan L. Binkert, Ronald G. Dreslinski, Trevor N. Mudge, Steven K. Reinhardt, Krisztián Flautner PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor. Search on Bibsonomy ASPLOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF 3D stacking technology, tier 1 server, web/file/streaming server, low power, chip multiprocessor, full-system simulation
45Lucian Codrescu, D. Scott Wills, James D. Meindl Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Thread speculation, multiscalar, parallelization, chip-multiprocessor, multithreading, value prediction
43Kyriakos Stavrou, Pedro Trancoso, Paraskevas Evripidou Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
42Xi Zhang 0008, Dongsheng Wang 0002, Yibo Xue, Haixia Wang 0001, Jinglei Wang A Novel Cache Organization for Tiled Chip Multiprocessor. Search on Bibsonomy APPT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Multi-level Directory, Chip Multiprocessor(CMP), Cache Organization, Tiled Architecture
42Magnus Jahre, Lasse Natvig A light-weight fairness mechanism for chip multiprocessor memory systems. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF dynamic miss handling architecture, miss status holding register, fairness, chip multiprocessor, interference, mechanism
42Hiroaki Inoue, Junji Sakai, Sunao Torii, Masato Edahiro FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Secure mobile terminal, chip multiprocessor, SELinux
42Yi-Neng Lin, Ying-Dar Lin, Yuan-Cheng Lai Thread Allocation in Chip Multiprocessor Based Multithreaded Network Processors. Search on Bibsonomy AINA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF thread allocation, simulation, modeling, Petri net, chip multiprocessor
42Li Yang 0001, Lu Peng 0001 SecCMP: a secure chip-multiprocessor architecture. Search on Bibsonomy ASID The full citation details ... 2006 DBLP  DOI  BibTeX  RDF security, fault-tolerance, encryption, chip-multiprocessor
42Peter G. Sassone, D. Scott Wills Scaling Up the Atlas Chip-Multiprocessor. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Dynamic multithreading, chip-multiprocessor, scaling
42Mladen Nikitovic, Mats Brorsson An adaptive chip-multiprocessor architecture for future mobile terminals. Search on Bibsonomy CASES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF chip-multiprocessor (CMP), power consumption, mobile terminals, energy-aware scheduling
41Ozcan Ozturk 0001, Guangyu Chen, Mahmut T. Kandemir Multi-compilation: capturing interactions among concurrently-executing applications. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF multi-compilation, compiler, chip multiprocessor
40Akira Yamawaki 0002, Masahiko Iwane Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor. Search on Bibsonomy ISPAN The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
40Sudeep Pasricha, Nikil D. Dutt, Fadi J. Kurdahi Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
39Masafumi Takahashi, Hiroyuki Takano, Emi Kaneko, Seigo Suzuki A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor. Search on Bibsonomy HPCA The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
37Raphael Fonte Boa, Dulcinéia Oliveira da Penha, Alexandre Marques Amaral, Márcio Oliveira Soares de Souza, Carlos Augusto Paiva da Silva Martins, Petr Yakovlevitch Ekel RCMP: A Reconfigurable Chip-Multiprocessor Architecture. Search on Bibsonomy ISPA Workshops The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
37Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Kenneth G. Wilson, Kunyung Chang The Case for a Single-Chip Multiprocessor. Search on Bibsonomy ASPLOS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
36Mainak Chaudhuri PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches. Search on Bibsonomy HPCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
34Vincent W. Freeh, Tyler K. Bletsch, Freeman L. Rawson III Scaling and Packing on a Chip Multiprocessor. Search on Bibsonomy IPDPS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Degui Feng, Guanjun Jiang, Tiefei Zhang, Wei Hu 0001, Tianzhou Chen, Mingteng Cao SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework. Search on Bibsonomy APPT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF synchronization, Chip multiprocessor, transactional memory, scratchpad memory
34Wan-Yu Lee, Iris Hui-Ru Jiang VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF chip-multiprocessor, process variation, monte carlo analysis
34Long Zheng 0001, Mianxiong Dong, Song Guo 0001, Minyi Guo, Li Li 0012 I-Cache Tag Reduction for Low Power Chip Multiprocessor. Search on Bibsonomy ISPA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF tag reduction, chip multiprocessor, energy saving
34Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003 Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF ia32, on-chip integration, chip multiprocessor, heterogeneous
34Christof Pitter Time-predictable memory arbitration for a Java chip-multiprocessor. Search on Bibsonomy JTRES The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Java, chip-multiprocessor, shared memory, worst-case execution time
34Venkata Krishnan, Josep Torrellas A Chip-Multiprocessor Architecture with Speculative Multithreading. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Chip-multiprocessor, speculative multithreading, data-dependence speculation, control speculation
33Mainak Chaudhuri Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF chip-multiprocessor, replacement policy, last-level cache
32Lucian Codrescu, D. Scott Wills Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
31Pedro Trancoso, Paraskevas Evripidou, Kyriakos Stavrou, Costas Kyriacou A Case for Chip Multiprocessors Based on the Data-Driven Multithreading Model. Search on Bibsonomy Int. J. Parallel Program. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF data-driven execution, parallel processing, Chip multiprocessor, multithreading
31Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi Designing On-Chip Network Based on Optimal Latency Criteria. Search on Bibsonomy ICESS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Philip Machanick Design principles for a virtual multiprocessor. Search on Bibsonomy SAICSIT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF chip multiprocessor, instruction-level parallelism
30Jugash Chandarlapati, Mainak Chaudhuri LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
30Haixia Wang 0001, Dongsheng Wang 0002, Peng Li 0031 Acceleration Techniques for Chip-Multiprocessor Simulator Debug. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Wenbin Yao, Dongsheng Wang 0002, Weimin Zheng A Fault-Tolerant Single-Chip Multiprocessor. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
30Magnus Ekman, Per Stenström Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores. Search on Bibsonomy ICPP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
29Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert 0001 GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications. Search on Bibsonomy ARCS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Mohamed M. Zahran On cache memory hierarchy for Chip-Multiprocessor. Search on Bibsonomy SIGARCH Comput. Archit. News The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
29Markus Rudack, Dirk Niggemeyer Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
29Lance Hammond, Mark Willey, Kunle Olukotun Data Speculation Support for a Chip Multiprocessor. Search on Bibsonomy ASPLOS The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
28Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Taylan Yemliha SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors. Search on Bibsonomy ICPADS (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF SPM (Scratch-Pad Memory), dynamic loop scheduling, parallelization, compiler, CMP (chip multiprocessor), data locality
28Michael Gschwind Chip multiprocessing and the cell broadband engine. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF compute-transfer parallelism (CTP), cell broadband engine, memory-level parallelism (MLP), chip multiprocessing, heterogeneous chip multiprocessor
28Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Ozcan Ozturk 0001, Mustafa Karaköy, Ugur Sezer Optimizing Array-Intensive Applications for On-Chip Multiprocessors. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF On-chip multiprocessor, adaptive loop parallelization, embedded systems, energy consumption, integer linear programming, constrained optimization
28Jaehyuk Huh 0001, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler A NUCA substrate for flexible CMP cache sharing. Search on Bibsonomy ICS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF cache sharing, non-uniform cache architecture, chip-multiprocessor
28Shuichi Sakai CMP on SoC: Architect's View. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF CMP (Chip Multiprocessor), I/O centric, SoC (System on Chip), parallel processing, dependability
28Venkata Krishnan, Josep Torrellas The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. Search on Bibsonomy IEEE PACT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF register communication, Chip-multiprocessor, speculative multithreading, data-dependence speculation
27Sudeep Pasricha, Nikil D. Dutt, Fadi J. Kurdahi Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
27Francisco J. Villa, Manuel E. Acacio, José M. García 0001 Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture. Search on Bibsonomy HPCC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Minoru Fujishima, Masahiro Shimura On-chip high-speed solver of inverse problems based on quantum-computing principle. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
27Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Viktor K. Prasanna Performance of On-Chip Multiprocessors for Vision Tasks. Search on Bibsonomy IPDPS Workshops The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
25Antonio Flores, Juan L. Aragón, Manuel E. Acacio Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. Search on Bibsonomy HiPC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Heterogeneus On-Chip Interconnection Network, Chip-Multiprocessor, Energy-Efficient Architectures, Parallel Scientific Applications
25Michela Becchi, Patrick Crowley Dynamic thread assignment on heterogeneous multiprocessor architectures. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF simulation, chip multiprocessor, heterogeneous architectures
24Takeshi Ogasawara Scalability limitations when running a Java web server on a chip multiprocessor. Search on Bibsonomy SYSTOR The full citation details ... 2010 DBLP  DOI  BibTeX  RDF performance, multi-cores, JVMs, web servers
24Martin Schoeberl, Peter P. Puschner, Raimund Kirner A Single-Path Chip-Multiprocessor System. Search on Bibsonomy SEUS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Hyunjin Kim, Hyejeong Hong, Hong-Sik Kim, Jin-Ho Ahn, Sungho Kang 0001 Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz Verification of chip multiprocessor memory systems using a relaxed scoreboard. Search on Bibsonomy MICRO The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Xin Jin 0003, Stephen B. Furber, John V. Woods Efficient modelling of spiking neural networks on a scalable chip multiprocessor. Search on Bibsonomy IJCNN The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity. Search on Bibsonomy IPDPS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Hisashige Ando, Nestoras Tzartzanis, William W. Walker A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Kyriakos Stavrou, Paraskevas Evripidou, Pedro Trancoso DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor. Search on Bibsonomy SAMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Weidong Shi, Hsien-Hsin S. Lee, Guofei Gu, Laura Falk, Trevor N. Mudge, Mrinmoy Ghosh An Intrusion-Tolerant and Self-Recoverable Network Service System Using A Security Enhanced Chip Multiprocessor. Search on Bibsonomy ICAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Intrusion-tolerant computing, survivable service, buffer overflow, self-healing, rootkits, chip multi processor
24Seongbeom Kim, Dhruba Chandra, Yan Solihin Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture. Search on Bibsonomy IEEE PACT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
24Chouki Aktouf A Complete Strategy for Testing an On-Chip Multiprocessor Architecture. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
24J. Robert Heath, Andrew Tan Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Real-time reconfigurable architecture, analytic functional modeling, real-time testing and functional/performance verification, design, FPGA prototyping
24Ryotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. Search on Bibsonomy EUROMICRO The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
23Hyungjun Kim, Boris Grot, Paul V. Gratz, Daniel A. Jiménez Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
23Francisco Triviño, José L. Sánchez 0002, Francisco J. Alfaro, José Flich Network-on-Chip virtualization in Chip-Multiprocessor Systems. Search on Bibsonomy J. Syst. Archit. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
23Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP). Search on Bibsonomy SBAC-PAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide Chip size and performance evaluations of shared cache for on-chip multiprocessor. Search on Bibsonomy Syst. Comput. Jpn. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
23Naraig Manjikian, Huang Jin, James Reed, Nathan Cordeiro Architecture and Implementation of Chip Multiprocessors: Custom Logic Components and Software for Rapid Prototyping. Search on Bibsonomy ICPP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
22Valentina Salapura Scaling up next generation supercomputers. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF scalability of systems, chip multiprocessors (cmp), multicore, coherence protocols, blue gene
21Jeffery A. Brown, Dean M. Tullsen The shared-thread multiprocessor. Search on Bibsonomy ICS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF chip multiprocessors, simultaneous multithreading
21Mirko Loghi, Massimo Poncino, Luca Benini Cache coherence tradeoffs in shared-memory MPSoCs. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF low power, multiprocessor, system-on-chip, Cache coherence
20Tilman Wolf, Mark A. Franklin Performance Models for Network Processor Design. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Network processor design, network processor benchmark, performance model, power optimization, design optimization
20Hangsheng Wang, Li-Shiuan Peh, Sharad Malik Power-driven Design of Router Microarchitectures in On-chip Networks. Search on Bibsonomy MICRO The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
19Kypros Constantinides, Onur Mutlu, Todd M. Austin Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. Search on Bibsonomy MICRO The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
19Mahmut T. Kandemir, Ozcan Ozturk 0001, Vijay Degalahal Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
19Juan Chen 0001, Yong Dong, Xuejun Yang, Dan Wu A Compiler-Directed Energy Saving Strategy for Parallelizing Applications in On-Chip Multiprocessors. Search on Bibsonomy ISPDC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
19Mahmut T. Kandemir, Wei Zhang 0002, Mustafa Karaköy Runtime Code Parallelization for On-Chip Multiprocessors. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
18Ahsan Shabbir, Akash Kumar 0001, Bart Mesman, Henk Corporaal Enabling MPSoC Design Space Exploration on FPGAs. Search on Bibsonomy IMTIC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGAs, MPSoC, FIFO, FSL
18Yurong Chen 0001, Ying Tan, Yimin Zhang 0002, Carole Dulong Performance Analysis of Two Parallel Game-Tree Search Applications. Search on Bibsonomy PARA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
18Martin Karlsson, Kevin E. Moore, Erik Hagersten, David A. Wood 0001 Memory System Behavior of Java-Based Middleware. Search on Bibsonomy HPCA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
18Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara Coarse-Grain Task Parallel Processing Using the OpenMP Backend of the OSCAR Multigrain Parallelizing Compiler. Search on Bibsonomy ISHPC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
17Xiaorui Wang, Kai Ma, Yefu Wang Adaptive Power Control with Online Model Estimation for Chip Multiprocessors. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF power capping, cache resizing, online model estimation, chip multiprocessor, Power control, feedback control
17Omer Khan, Sandip Kundu Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors. Search on Bibsonomy IEEE Trans. Dependable Secur. Comput. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF hard error detection, isolation and tolerance, Chip Multiprocessor (CMP), hardware/software codesign
17Taecheol Oh, Kiyeon Lee, Sangyeun Cho An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing. Search on Bibsonomy MASCOTS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF simulation, performance modeling, Chip multiprocessor (CMP), resource sharing
17Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström Implications of Merging Phases on Scalability of Multi-core Architectures. Search on Bibsonomy ICPP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF Redcution operations, Chip Multiprocessor, Amdahl's Law
17Omer Khan, Sandip Kundu Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2010 DBLP  DOI  BibTeX  RDF hard-error tolerance, virtualization, Chip multiprocessor (CMP), hardware/software codesign, hypervisor
17Hyunjin Lee, Sangyeun Cho, Bruce R. Childers PERFECTORY: A Fault-Tolerant Directory Memory Architecture. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2010 DBLP  DOI  BibTeX  RDF chip yield, lifetime reliability, Chip multiprocessor, cache coherence
17Antonio Flores, Juan L. Aragón, Manuel E. Acacio Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Tiled chip multiprocessor, heterogeneous on-chip interconnection network, cache coherence protocol, energy-efficient architectures, parallel scientific applications
17Harold Ishebabi, Christophe Bobda Heuristics for Flexible CMP Synthesis. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2010 DBLP  DOI  BibTeX  RDF chip multiprocessor systems, parallel programs, Reconfigurable computing
17Antonio Flores, Juan L. Aragón, Manuel E. Acacio Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects. Search on Bibsonomy PDP The full citation details ... 2010 DBLP  DOI  BibTeX  RDF tiled chip-multiprocessor, heterogeneous on-chip interconnection network, prefetching, energy-efficient architectures, parallel scientific applications
17Chao Wang 0058, Bin Xie 0002, Jiexiang Kang, Tianzhou Chen, Wei Hu 0001, Zhenwei Zheng On-Chip Operating System Design for NoC-Based CMP. Search on Bibsonomy CIT The full citation details ... 2010 DBLP  DOI  BibTeX  RDF operating system, network on chip, chip multiprocessor
17Dan Gibson, David A. Wood 0001 Forwardflow: a scalable core for power-constrained CMPs. Search on Bibsonomy ISCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF scalable core, chip multiprocessor (cmp), power
17Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz Understanding sources of inefficiency in general-purpose chips. Search on Bibsonomy ISCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance
17Muhammad Mukaram Khan, Javier Navaridas, Alexander D. Rast, Xin Jin 0003, Luis A. Plana, Mikel Luján, John V. Woods, José Miguel-Alonso, Steve B. Furber Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric. Search on Bibsonomy ISPDC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Multi-CMP Configuration, Neural Networks, Fault-tolerance, Embedded Systems, Chip Multiprocessor, Real-time Application, Massively Parallel Computing
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