Search results for "Complex-instruction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
34	Jack W. Davidson, Richard A. Vaughan	The Effect of Instruction Set Complexity on Program Size and Memory Performance.	ASPLOS	1987	DBLP DOI BibTeX RDF
26	David Ryan Koes, Seth Copen Goldstein	Near-optimal instruction selection on dags.	CGO	2008	DBLP DOI BibTeX RDF	instruction selection
23	Gabriel M. Silberman, Kemal Ebcioglu	An architectural framework for migration from CISC to higher performance platforms.	ICS	1992	DBLP DOI BibTeX RDF
23	Kevin J. McNeley, Veljko M. Milutinovic	Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer.	IEEE Micro	1987	DBLP DOI BibTeX RDF
22	Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster 0001	Extracting Speedup From C-Code With Poor Instruction-Level Parallelism.	IPDPS	2005	DBLP DOI BibTeX RDF
19	Siddharth Rele, Vipin Jain, Santosh Pande, J. Ramanujam	Compact and efficient code generation through program restructuringon limited memory embedded DSPs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
18	Anjali Mahajan, M. Sadique Ali	Superblock scheduling using genetic programming for embedded systems.	IEEE ICCI	2008	DBLP DOI BibTeX RDF
18	You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung	Customization of a CISC Processor Core for Low-Power Applications.	ICCD	1999	DBLP DOI BibTeX RDF	CISC-processor, Complex-instruction, ROM-compile, Low-power-design, Microcode
15	Kuo-Su Hsiao, Chung-Ho Chen	An efficient wakeup design for energy reduction in high-performance superscalar processors.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	issue window, wakeup logic, low power, high performance
14	Yuzhou Huang, Liangbin Xie, Xintao Wang, Ziyang Yuan, Xiaodong Cun, Yixiao Ge, Jiantao Zhou 0001, Chao Dong, Rui Huang, Ruimao Zhang, Ying Shan	SmartEdit: Exploring Complex Instruction-based Image Editing with Multimodal Large Language Models.	CoRR	2023	DBLP DOI BibTeX RDF
14	Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal	Automatic complex instruction identification for efficient application mapping onto ASIPs.	LASCAS	2014	DBLP DOI BibTeX RDF
14	Armita Peymandoust, Tajana Simunic, Giovanni De Micheli	Complex instruction and software library mapping for embedded software using symbolic algebra.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
14	David R. Stiles, Harold L. McFarland	Pipeline control for a single cycle VLSI implementation of a complex instruction set computer.	COMPCON	1989	DBLP DOI BibTeX RDF
14	Michael J. Flynn, Chad L. Mitchell, Johannes M. Mulder	And Now a Case for More Complex Instruction Sets.	Computer	1987	DBLP DOI BibTeX RDF
14	Richard L. Norton, Jacob A. Abraham	Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets	ISCA	1983	DBLP DOI BibTeX RDF
14	Pedro Furtado 0001, Henrique Madeira	Fault Injection Evaluation of Assigned Signatures in a RISC Processor.	EDCC	1996	DBLP DOI BibTeX RDF
11	Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster 0001	Reducing power while increasing performance with supercisc.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Low-power, synthesis, VLIW, predication, multicore architectures
11	Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami	Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
10	Partha Biswas, Nikil D. Dutt	Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction
10	Brian Slechta, David Crowe, Brian Fahs, Michael Fertig, Gregory A. Muthler, Justin Quek, Francesco Spadini, Sanjay J. Patel, Steven Lumetta	Dynamic Optimization of Micro-Operations.	HPCA	2003	DBLP DOI BibTeX RDF
10	Partha Biswas, Nikil D. Dutt	Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions.	CASES	2003	DBLP DOI BibTeX RDF	dependence conflict graph, heterogeneous-connectivity-based DSP, restricted data dependence graph, instruction set extensions, instruction set architecture, static single assignment
10	Uming Ko, Poras T. Balsara, Ashwini K. Nanda	Energy optimization of multilevel cache architectures for RISC and CISC processors.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
10	Shailesh Sutarwala, Pierre G. Paulin	Flexible modeling environment for embedded systems design.	CODES	1994	DBLP DOI BibTeX RDF
6	Todd A. Proebsting	BURS Automata Generation.	ACM Trans. Program. Lang. Syst.	1995	DBLP DOI BibTeX RDF	code-generator generator, dynamic programming, code generation, tree pattern matching
6	Yashwant K. Malaiya, Sheng Feng	Design of a testable RISC-to-CISC control architecture.	MICRO	1988	DBLP BibTeX RDF	RISC