Search results for "Coprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
144	Sirish A. Kondi, Yoginder S. Dandass	Scanning workstation memory for malicious codes using dedicated coprocessors.	ACM Southeast Regional Conference	2006	DBLP DOI BibTeX RDF	FPGA, intrusion detection, coprocessor, signature matching
92	Christian Mandl, Adolfo Fucci	A fast FPGA based coprocessor supporting hard real-time search.	EUROMICRO	1997	DBLP DOI BibTeX RDF	fast FPGA based coprocessor, hard real time search, dual port memories, programmable message driven multi port memories, sequential requests, data acquisition systems, hard real time requirements, DAC systems, coprocessor architectures, file descriptor table, implementation costs, TI DSP C40, hardware strategy, dual port memory, generic searching coprocessor, field programmable gate arrays, hardware implementation, computer systems, high throughput, searching strategy, design approach, DPMs
90	James T. Canning, Richard A. Miner	A Parallel Pipelined Data Flow Coprocessor.	ACM Conference on Computer Science	1989	DBLP DOI BibTeX RDF	IBM PC
87	Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis	Speedups in embedded systems with a high-performance coprocessor datapath.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	coprocessor datapath, synthesis, kernels, Performance improvements, design flow, chaining
87	Souichi Okada, Naoya Torii, Kouichi Itoh, Masahiko Takenaka	Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA.	CHES	2000	DBLP DOI BibTeX RDF	elliptic scalar multiplication over tex2html_wrap_inline100, IEEE P1363, Elliptic curve cryptography (ECC), multiplier, coprocessor, Koblitz curve
79	Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede	A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing.	DAC	2005	DBLP DOI BibTeX RDF	security IC, encryption, smart card, side-channel attack, differential power analysis, countermeasure
76	Chen-Yong Cher, Michael Gschwind	Cell GC: using the cell synergistic processor as a garbage collection coprocessor.	VEE	2008	DBLP DOI BibTeX RDF	BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
76	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path.	J. Supercomput.	2007	DBLP DOI BibTeX RDF	Coprocessor data-path, Template units, Performance, Synthesis, Kernels, Design flow, Chaining
76	Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Superscalar Coprocessor for High-Speed Curve-Based Cryptography.	CHES	2006	DBLP DOI BibTeX RDF	curve-based cryptography, HECC, ECC, instruction-level parallelism, scalar multiplication, Superscalar, coprocessor
76	Michael J. Schulte, Earl E. Swartzlander Jr.	Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	arithmetic algorithms, computer arithmetic, hardware, Interval arithmetic, precision, coprocessor, numerical computations
74	Chen Huang 0005, Frank Vahid	Transmuting coprocessors: dynamic loading of FPGA coprocessors.	DAC	2009	DBLP DOI BibTeX RDF	coprocessing, FPGAs, online algorithms, dynamic optimization, acceleration, runtime configuration
71	Seng Lin Shee, Sri Parameswaran, Newton Cheung	Novel architecture for loop acceleration: a case study.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	tightly coupled, architecture, ASIP, hardware/software partitioning, coprocessor, loop optimization, latency hiding, loop pipelining, loop acceleration
69	Chen Huang 0005, Frank Vahid	Server-side coprocessor updating for mobile devices with FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	coprocessing, fpgas, dynamic optimization, acceleration
69	Ernesto Martins, José Alberto Fonseca	Traffic Scheduling Coprocessor with Schedulability Analysis Capability.	DSD	2001	DBLP DOI BibTeX RDF
69	Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems	The spring scheduling coprocessor: a scheduling accelerator.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
66	Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis	Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	coprocessor data-path, template units, kernels, performance improvements, design flow, energy reductions, architectural synthesis
66	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	coprocessor data-path, synthesis, energy savings, performance improvements, design flow
66	Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede	Microcoded coprocessor for embedded secure biometric authentication systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	cryptographic biometrics, fingerprint verification., fuzzy vault scheme, microcoded coprocessor
66	Wieland Fischer, Jean-Pierre Seifert	Increasing the Bitlength of a Crypto-Coprocessor.	CHES	2002	DBLP DOI BibTeX RDF	Arithmetical coprocessor, Hardware/Software codesign, Modular multiplication, Hardware architecture
66	S. Ramanathan, S. K. Nandy 0001, V. Visvanathan	Reconfigurable Filter Coprocessor Architecture for DSP Applications.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF	reconfigurable coprocessors, filter coprocessor architecture, systolic architectures and digital signal processing, pipelined architectures, low-power architectures
66	Emeka Mosanya, Christof Teuscher, Héctor Fabio Restrepo, Patrick Galley, Eduardo Sanchez	CryptoBooster: A Reconfigurable and Modular Cryptographic Coprocessor.	CHES	1999	DBLP DOI BibTeX RDF	FPGA, Cryptography, Reconfiguration, Coprocessor, IDEA
66	Michael J. Schulte, Earl E. Swartzlander Jr.	A coprocessor for accurate and reliable numerical computations.	ICCD	1995	DBLP DOI BibTeX RDF	reliable numerical computations, direct hardware support, logic design, digital arithmetic, interval arithmetic, hardware design, coprocessors, coprocessor, numerical computations
66	Anders Kugler, Roger D. Hersch	A Scalable Halftoning Coprocessor Architecture.	ASAP	1995	DBLP DOI BibTeX RDF	parallel dithering, coprocessor architecture, Halftoning
63	Nathan Woods	Integrating FPGAs in high-performance computing: the architecture and implementation perspective.	FPGA	2007	DBLP DOI BibTeX RDF	compute acceleration, high-performance computinghigh-performance computing, reconfigurable computing, co-processor
63	Takashi Miyamori, Kunle Olukotun	A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications.	FCCM	1998	DBLP DOI BibTeX RDF
63	Emilio Luque, Joan Sorribes, Ana Ripoll	Tuning architecture at run-time.	MICRO	1987	DBLP DOI BibTeX RDF
63	Nalini K. Ratha, Anil K. Jain 0001, Diane T. Rover	FPGA-Based Coprocessor for Text String Extraction.	CAMP	2000	DBLP DOI BibTeX RDF	FPGA-based coprocessor, text string extraction, image morphology based algorithms, high-performance coprocessor, Splash 2, Sun hosts, VHDL behavioral modeling, SPARC station 20, design patterns, coprocessors, document understanding, visual effects
58	Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez	Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC.	FPL	2008	DBLP DOI BibTeX RDF
58	Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch	A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing.	SAMOS	2007	DBLP DOI BibTeX RDF
58	Ming-che Lai, Kui Dai, Lu Hong-yi, Zhiying Wang 0003	A Novel Data-Parallel Coprocessor for Multimedia Signal Processing.	ICME	2006	DBLP DOI BibTeX RDF
58	Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller 0006	Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics Experiment.	FPL	2004	DBLP DOI BibTeX RDF
58	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor.	FCCM	2004	DBLP DOI BibTeX RDF
58	Jens Hildebrandt, Dirk Timmermann	An FPFA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time Systems.	FPL	2000	DBLP DOI BibTeX RDF
55	Kyoung-Mook Lim, Seh-Woong Jeong, Yong-Chun Kim, Seung-Jae Jeong, Hong-Kyu Kim, Yang-Ho Kim, Bong-Young Chung, Hyung-Lae Roh, H. S. Yang	CalmRISCTM: A Low Power Microcontroller with Efficient Coprocessor Interface.	ICCD	1999	DBLP DOI BibTeX RDF	low-power, microcontroller, coprocessor
55	Christoph Baumhof	A New VLSI Vector Arithmetic Coprocessor for the PC.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	accurate dot product, vector arithmetic coprocessor, Long Accumulator
53	Yijun Liu, Pinghua Chen, Guobo Xie, Guangcong Liu, Zhenkun Li	Evaluating a Low-Power Dual-Core Architecture.	APPT	2007	DBLP DOI BibTeX RDF
50	Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh, Tobias G. Noll	Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	heterogeneous reconfigurable systems, dedicated ASICs, coprocessor board, CardBus, multimedia applications, text search
50	Klaus E. Schauser, Chris J. Scheiman, J. Mitchell Ferguson, Paul Z. Kolano	Exploiting the Capabilities of Communications Co-Processors.	IPPS	1996	DBLP DOI BibTeX RDF	inter-computer links, communications coprocessor architecture, dedicated hardware support, user-level message handlers, Split-C, message handling code, Meiko CS-2 platform, synchronization, parallel architectures, local area networks, synchronisation, flexibility, coprocessors, computational power, massively parallel processors, workstation networks, active messages, electronic messaging
50	Umakishore Ramachandran, Marvin H. Solomon, Mary K. Vernon	Hardware Support for Interprocess Communication.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	special-purpose coprocessor, message-based operating system, shared queues, special-purpose smart bus, smart shared memory, generalized timed Petri nets, performance evaluation, Petri nets, protocols, distributed processing, message passing, analytical modeling, interprocess communication, hardware support
48	Xu Guo 0001, Patrick Schaumont	Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform.	ARC	2009	DBLP DOI BibTeX RDF
48	Xu Guo 0001, Junfeng Fan, Patrick Schaumont, Ingrid Verbauwhede	Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security.	CHES	2009	DBLP DOI BibTeX RDF
48	Jean-Luc Beuchat, Nicolas Brisebarre, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto	A Coprocessor for the Final Exponentiation of the eta T Pairing in Characteristic Three.	WAIFI	2007	DBLP DOI BibTeX RDF	final exponentiation, FPGA, hardware accelerator, ? T pairing, characteristic three
48	John H. Kelm, Isaac Gelado, Mark J. Murphy, Nacho Navarro, Steven S. Lumetta, Wen-mei W. Hwu	CIGAR: Application Partitioning for a CPU/Coprocessor Architecture.	PACT	2007	DBLP DOI BibTeX RDF
48	Volker Hampel, Peter Sobe, Erik Maehle	Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor.	DSD	2007	DBLP DOI BibTeX RDF
48	Silvia Franchini, Antonio Gentile, M. Grimaudo, C. A. Hung, Sandro Impastato, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile	A Sliced Coprocessor for Native Clifford Algebra Operations.	DSD	2007	DBLP DOI BibTeX RDF
48	Syed Sajjad Rizvi, Syed N. Hyder, Aasia Riasat	Performance Model for a Reconfigurable Coprocessor.	SCSS (1)	2007	DBLP DOI BibTeX RDF
48	Yuan-man Tong, Zhiying Wang 0003, Kui Dai, Hongyi Lu	Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining.	Inscrypt	2006	DBLP DOI BibTeX RDF	WDDL, power analysis resistant, block cipher, design flow, Wave-pipelining
48	Yijun Liu, Stephen B. Furber	A Low Power Embedded Dataflow Coprocessor.	ISVLSI	2005	DBLP DOI BibTeX RDF
48	Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian 0001, Neda Zolfaghari	Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms.	DSD	2005	DBLP DOI BibTeX RDF
48	Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller 0006	Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger.	FPGA	2004	DBLP DOI BibTeX RDF
48	Feihui Li, Mahmut T. Kandemir	Improving Performance of Java Applications Using a Coprocessor.	IPDPS	2004	DBLP DOI BibTeX RDF
48	He Chuan, Mi Lu, Chuanwen Sun	Accelerating Seismic Migration Using FPGA-Based Coprocessor Platform.	FCCM	2004	DBLP DOI BibTeX RDF
48	Romain Kamdem, Alain Fonkoua	Coprocessor Synthesis of Multirate System Using Static Scheduling Theory.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	scheduling, real time, Codesign, codesign, hardware/software partitioning, target architecture
48	Patricia J. Teller, Michael E. Maxwell, Ann Q. Gates	Towards the design of a snoopy coprocessor for dynamic software-fault detection.	IPCCC	1999	DBLP DOI BibTeX RDF
48	Giuliano Donzellini, Stefano Nervi, Domenico Ponta, Sergio Rossi, Stefano Rovetta	Object Oriented ARM7 Coprocessor.	HICSS (3)	1998	DBLP DOI BibTeX RDF
45	Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman	A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor.	FCCM	1999	DBLP DOI BibTeX RDF	FPGA, Elliptic curve cryptography, Reconfigurable hardware, Scalar multiplication, Galois field, Coprocessor
45	Tudor Jebelean	Design of a systolic coprocessor for rational addition.	ASAP	1995	DBLP DOI BibTeX RDF	systolic coprocessor, rational addition, exact division, field programmable gate arrays, parallel architectures, systolic arrays, digital arithmetic, multiplication, addition, subtraction, rational numbers, GCD
42	Arnaud Lagger, Andres Upegui, Eduardo Sanchez, Iván González	Self-Reconfigurable Pervasive Platform for Cryptographic Application.	FPL	2006	DBLP DOI BibTeX RDF
42	Sean W. Smith	Outbound authentication for programmable secure coprocessors.	Int. J. Inf. Sec.	2004	DBLP DOI BibTeX RDF	Secure coprocessors, Authentication, Trust, Attestation
42	Sean W. Smith	Outbound Authentication for Programmable Secure Coprocessors.	ESORICS	2002	DBLP DOI BibTeX RDF
42	Harald Simmler, L. Levinson, Reinhard Männer	Multitasking on FPGA Coprocessors.	FPL	2000	DBLP DOI BibTeX RDF
39	Sébastien Bilavarn, Eric Debes, Pierre Vandergheynst, Jean-Philippe Diguet	Processor Enhancements for Media Streaming Applications.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	reconfigurable coprocessor, hardware design space exploration, video coding, codesign, multimedia processing, matching pursuit, software profiling
39	Martin Seysen	Using an RSA Accelerator for Modular Inversion.	CHES	2005	DBLP DOI BibTeX RDF	Smart card coprocessor, Euclidean algorithm, modular inversion
39	Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh	Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality.	ASAP	2000	DBLP DOI BibTeX RDF	reconfigurable coprocessor board, multimedia, VLSI, DSP, digital signal processing, ASIC, CMOS
39	Lijun Gao, Sarvesh Shrivastava, Gerald E. Sobelman	Elliptic Curve Scalar Multiplier Design Using FPGAs.	CHES	1999	DBLP DOI BibTeX RDF	FPGA, public-key cryptography, elliptic curves, reconfigurable hardware, scalar multiplication, Galois field, coprocessor
39	Robert R. Jueneman	A High Speed Manipulation Detection Code.	CRYPTO	1986	DBLP DOI BibTeX RDF	Manipulation Detection Code (MDC), birthday problem attacks, numeric data processor chip, math coprocessor chip, 8087, 80287, authentication, cryptography, digital signature, encryption, Message Authentication Code (MAC), IBM PC, checksums
37	Virgil E. Petcu, Alexandru Amaricai, Mircea Vladutiu	A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units.	DDECS	2008	DBLP DOI BibTeX RDF
37	Xia Hong 0002, Ning Hui-ming, Yan Jiang-yu	The Realization and Optimization of Secure Hash Algorithm (SHA-1) Based on LEON2 Coprocessor.	CSSE (3)	2008	DBLP DOI BibTeX RDF
37	Jalaj Jain	A Scalable and Reconfigurable Coprocessor for Image Composition.	VLSI Design	2008	DBLP DOI BibTeX RDF
37	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
37	Giovanni Busonera, Stefano Carucci, Danilo Pani, Luigi Raffo	Self-Organization on Silicon: System Integration of a Fixed-Point Swarm Coprocessor.	NICSO	2007	DBLP DOI BibTeX RDF
37	Nele Mentens, Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications.	ICSAMOS	2007	DBLP DOI BibTeX RDF
37	Ying Chen, Simon Y. Chen	Cost-Driven Hybrid Configuration Prefetching for Partial Reconfigurable Coprocessor.	IPDPS	2007	DBLP DOI BibTeX RDF
37	Henrik Svensson, Thomas Lenart, Viktor Öwall	Accelerating Vector Operations by Utilizing Reconfigurable Coprocessor Architectures.	ISCAS	2007	DBLP DOI BibTeX RDF
37	Yijun Liu, Steve B. Furber, Zhenkun Li	The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing.	PATMOS	2006	DBLP DOI BibTeX RDF
37	Mariano López-García, Enrique F. Cantó-Navarro	FPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware Coprocessor.	FPL	2006	DBLP DOI BibTeX RDF
37	Nele Mentens, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede, Bart Preneel	Fpga-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor.	FPL	2006	DBLP DOI BibTeX RDF
37	Guido Bertoni, Luca Breveglieri, Matteo Venturi	Power Aware Design of an Elliptic Curve Coprocessor for 8 bit Platforms.	PerCom Workshops	2006	DBLP DOI BibTeX RDF
37	Chuan He, Wei Zhao 0001, Mi Lu	Time Domain Numerical Simulation for Transient Waves on Reconfigurable Coprocessor Platform.	FCCM	2005	DBLP DOI BibTeX RDF
37	Matthias Meyer	An On-Chip Garbage Collection Coprocessor for Embedded Real-Time Systems.	RTCSA	2005	DBLP DOI BibTeX RDF
37	Guido Bertoni, Luca Breveglieri, Thomas J. Wollinger, Christof Paar	Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems.	ITCC (2)	2004	DBLP DOI BibTeX RDF	genus 2, parallelism, embedded processor, hardware architecture, hyperelliptic curve, co-processor
37	Alireza Hodjat, Patrick Schaumont, Ingrid Verbauwhede	Architectural Design Features of a Programmable High Throughput AES Coprocessor.	ITCC (2)	2004	DBLP DOI BibTeX RDF
37	Tillmann Schmitz, Steffen G. Hohmann, Karlheinz Meier, Johannes Schemmel, Felix Schürmann	Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms.	ICES	2003	DBLP DOI BibTeX RDF
37	Andrea Pacifici, C. Vendetti, Fabrizio Frescura, Saverio Cacopardi	A reconfigurable channel codec coprocessor for software radio multimedia applications.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
37	Nigel Boston, T. Charles Clancy, Y. Liow, Jonathan E. Webster	Genus Two Hyperelliptic Curve Coprocessor.	CHES	2002	DBLP DOI BibTeX RDF
37	Joan G. Dyer, Mark Lindemann, Ronald Perez, Reiner Sailer, Leendert van Doorn, Sean W. Smith, Steve H. Weingart	Building the IBM 4758 Secure Coprocessor.	Computer	2001	DBLP DOI BibTeX RDF
37	Takehiko Kato, Satoru Ito, Jun Anzai, Natsume Matsuzaki	A Design for Modular Exponentiation Coprocessor in Mobile Telecommunication Terminals.	CHES	2000	DBLP DOI BibTeX RDF
37	Jens Hildebrandt, Frank Golatowski, Dirk Timmermann	Scheduling coprocessor for enhanced least-laxity-first scheduling in hard real-time systems.	ECRTS	1999	DBLP DOI BibTeX RDF
37	F. Battini, P. L. Mantovani, Marco Mattavelli	Evaluation of a SPARC Board Equipped with the Ada Tasking Coprocessor (ATAC).	Ada-Europe	1995	DBLP DOI BibTeX RDF
37	Joachim Roos	Designing a Real-Time Coprocessor for Ada Tasking.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
37	Lars Lundberg	A Coprocessor for High Performance Multiprocessor Ada Tasking.	Ada-Europe	1991	DBLP DOI BibTeX RDF
37	Joel Boney	Goals and tradeoffs in the design of the MC68881 floating point coprocessor.	AFIPS National Computer Conference	1984	DBLP DOI BibTeX RDF
34	Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume	Unbridle the Bit-Length of a Crypto-coprocessor with Montgomery Multiplication.	Selected Areas in Cryptography	2006	DBLP DOI BibTeX RDF	RSA, smartcard, Montgomery multiplication, crypto-coprocessor
34	Gerald Friedl, Marco Platzner, Bernhard Rinner	A Special-purpose Coprocessor for Qualitative Simulation.	Euro-Par	1995	DBLP DOI BibTeX RDF	specialized coprocessor, qualitative simulator QSim, FPGA
34	Israel Koren, Ofra Zinaty	Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	high-precision floating-point numbers, extended double precision format, IEEE standard P754, floating-point numeric coprocessor, fast adder, digital arithmetic, execution time, microprocessor chips, approximation theory, elementary functions, function evaluation, rational approximations, silicon area, fast multiplier
32	Pranav S. Vaidya, John Jaehwan Lee, Vijay S. Pai, Miyoung Lee, Sung Jin Hur	Symbiote Coprocessor Unit - A Streaming Coprocessor for Data Stream Acceleration.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
32	Patrick Schaumont, Doris Ching, Ingrid Verbauwhede	An interactive codesign environment for domain-specific coprocessors.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	hardware description language, hardware-software codesign, Cosimulation
32	Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis	Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path.	ICSAMOS	2006	DBLP DOI BibTeX RDF
32	Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle	An adaptive system-on-chip for network applications.	IPDPS	2006	DBLP DOI BibTeX RDF
32	Mun-Kyu Lee, Keon Tae Kim, Howon Kim 0001, Dong Kyue Kim	Efficient Hardware Implementation of Elliptic Curve Cryptography over GF(pm).	WISA	2005	DBLP DOI BibTeX RDF