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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 7 occurrences of 7 keywords
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Results
Found 54 publication records. Showing 54 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
56 | Pei-Lin Pai |
DRAM Industry Trend. |
MTDT |
2006 |
DBLP DOI BibTeX RDF |
|
53 | Phil Murray, Feras Al-Hawari |
Challenges in implementing DDR3 memory interface on PCB systems: a methodology for interfacing DDR3 SDRAM DIMM to an FPGA. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
33 | Ronald N. Kalla, Balaram Sinharoy, William J. Starke, Michael S. Floyd |
Power7: IBM's Next-Generation Server Processor. |
IEEE Micro |
2010 |
DBLP DOI BibTeX RDF |
Power7, eDRAM, DDR3, SMT operation, PowerPC architecture, processor, IBM, RAS |
33 | Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John |
The virtual write queue: coordinating DRAM and last-level cache policies. |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache |
28 | Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Zhichun Zhu |
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. |
ISCA |
2009 |
DBLP DOI BibTeX RDF |
bandwidth decoupling, decoupled DIMM, DRAM memories |
28 | Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Eugene Gorbatov, Howard David, Zhichun Zhu |
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Xiaofeng Yang, Ancheng Liu, Jinjin Wang |
High Speed Multi-channel Data Cache Design Based on DDR3 SDRAM. |
AIPR |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Vladimir M. Milovanovic, Darko M. Tasovac |
A Customizable DDR3 SDRAM Controller Tailored for FPGA-Based Data Buffering Inside Real-Time Range-Doppler Radar Signal Processing Back Ends. |
EUROCON |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Ana Cóbreces, Alberto Regadío, Jesús Tabero, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro |
Seu and Sefi error detection and correction on a ddr3 memory system. |
Microelectron. Reliab. |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Jianfei Wu, Wei Zhu, Binhong Li, Yafei Li, Hongyi Wang 0003, Mengjun Wang |
Investigations on immunity of interfaces between intelligent media processor and DDR3 SDRAM memory. |
Microelectron. Reliab. |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Tan Li, Hosung Lee, GeunYong Bak, Sanghyeon Baeg |
Failure signature analysis of power-opens in DDR3 SDRAMs. |
Microelectron. Reliab. |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Matthias Jung 0001, Deepak M. Mathew, Carl Christian Rheinländer, Christian Weis, Norbert Wehn |
A Platform to Analyze DDR3 DRAM's Power and Retention Time. |
IEEE Des. Test |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Junsub Yoon, Seo Weon Heo, Jongsun Kim |
A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs. |
IEICE Electron. Express |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Sergei Odintsov, Artur Jutman, Sergei Devadze |
Marginal PCB assembly defect detection on DDR3/4 memory bus. |
ITC |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Xuedong Wang, Lingyu Shen, Min Jia |
The Design and Optimization of DDR3 Controller Based on FPGA. |
CSPS |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Johannes Bauer 0004, Michael Gruhn, Felix C. Freiling |
Lest we forget: Cold-boot attacks on scrambled DDR3 memory. |
Digit. Investig. |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Kyungbae Park, Donghyuk Yun, Sanghyeon Baeg |
Statistical distributions of row-hammering induced failures in DDR3 components. |
Microelectron. Reliab. |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Kyungbae Park, Chul Seung Lim, Donghyuk Yun, Sanghyeon Baeg |
Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 × nm technology. |
Microelectron. Reliab. |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Wenhua Ye, Huan Li |
FPGA Based DDR3 Applications in a Multichannel Channelization Data Cache. |
ISCID (1) |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Baekseok Ko, Joo-Won Kim, Kihun Oh, Chan-Keun Kwon, Soo-Won Kim |
Simulation of serpentine trace of DQ PCB layout for DDR3 applications. |
ICCE |
2016 |
DBLP DOI BibTeX RDF |
|
26 | GeunYong Bak, Soonyoung Lee, Hosung Lee, Kyungbae Park, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong, Charlie Slayman |
Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams. |
IRPS |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Simon Lindenlauf, Hans Höfken, Marko Schuba |
Cold Boot Attacks on DDR2 and DDR3 SDRAM. |
ARES |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Rajat Chauhan, Prajkta Vyavahare, Siva Kothamasu |
Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system power. |
ISQED |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Hao-Yu Yang, Shih-Hua Kuo, Tzu-Hsuan Huang, Chi-Hung Chen, Chris Lin, Mango Chia-Tso Chao |
Random pattern generation for post-silicon validation of DDR3 SDRAM. |
VTS |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma 0001, Vaidyanathan Srinivasan, Dipankar Sarma |
Power Optimization Techniques for DDR3 SDRAM. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Vladimir V. Stankovic, Nebojsa Z. Milenkovic, Oliver M. Vojinovic |
Implementation of the Complete Predictor for DDR3 SDRAM. |
IEICE Trans. Inf. Syst. |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Hongming Chen 0002, Song Ma, Liu Wang, Hao Zhang, Kenyi Pan, Yuhua Cheng |
A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller. |
Sci. China Inf. Sci. |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Wenchao Liu 0003, Zhenhua Zhang, Miao-Xin Li, Zhenglin Liu |
A Trustworthy Key Generation Prototype Based on DDR3 PUF for Wireless Sensor Networks. |
Sensors |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Abir M'zah, Bruno Monsuez |
Refresh-aware DDR3 barrel memory controller with deterministic functionality. |
ODES@CGO |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel |
A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI. |
ESSCIRC |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Shang-Ping Chen, Chih-Chien Hung, Qui-Ting Chen, Sheng-Ming Chang, Ming-Shi Liou, Bo-Wei Hsieh, Hsiang-I Huang, Brian Liu, Yan-Bin Luo |
26.6 A 2.667Gb/s DDR3 memory interface with asymmetric ODT on wirebond package and single-side-mounted PCB. |
ISSCC |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Gilbert Netzer, S. Lennart Johnsson, Daniel Ahlin, Erwin Laure |
Instrumentation for accurate energy-to-solution measurements of a texas instruments TMS320C6678 digital signal processor and its DDR3 memory. |
E2SC@SC |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Su Myat Min, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran |
A case study on exploration of last-level cache for energy reduction in DDR3 DRAM. |
MECO |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Seung Mo Jung, Jong Hyun Seok, Ho Jin Yoo, Do Hyung Kim 0002, You Keun Han, Woo-Seop Kim, Joo-Sun Choi, Jun Dong Cho |
Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module. |
SoCC |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Kambiz Kaviani, Ting Wu 0003, Jason Wei, Amir Amirkhany, Jie Shen 0010, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi 0004, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan |
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. |
IEEE J. Solid State Circuits |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Gary A. Van Huben, Kirk D. Lamb, R. Brett Tremaine, B. E. Aleman, S. M. Rubow, S. H. Rider, Warren E. Maule, Michael E. Wazlowski |
Server-class DDR3 SDRAM memory buffer chip. |
IBM J. Res. Dev. |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Heechai Kang, Kyungho Ryu, Dong-Hoon Jung, Donghwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung |
Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong |
A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. |
ISSCC |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Richard Crisp, Bill Gervasi, Wael Zohni, Bel Haba |
Cost-minimized double die DRAM packaging for ultra-high performance DDR3 and DDR4 multi-rank server DIMMs. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Navin K. Mishra, Manish Jain, Phuong Le, Sanku Mukherjee, Arul Sendhil, Amir Amirkhany |
An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface. |
CICC |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Jong-Chern Lee, Sin-Hyun Jin, Dae-Suk Kim, Young Jun Ku, Chul Kim, Byung-Kwon Park, Hong-Gyeom Kim, Seong-Jun Ahn, Jaejin Lee, Sung-Joo Hong |
A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM. |
A-SSCC |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Uksong Kang, Hoeju Chung, Seongmoo Heo, Dukha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam-Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo-Sun Choi, Changhyun Kim, Young-Hyun Jun |
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. |
IEEE J. Solid State Circuits |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Vladimir V. Stankovic, Nebojsa Z. Milenkovic |
DDR3 SDRAM with a Complete Predictor. |
IEICE Trans. Inf. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Jaejun Lee, Sungho Lee, Sangwook Nam |
Multi-Slot Main Memory System for Post DDR3. |
IEEE Trans. Circuits Syst. II Express Briefs |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Heechai Kang, Kyungho Ryu, Donghwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung |
Process variation tolerant all-digital multiphase DLL for DDR3 interface. |
CICC |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim |
1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. |
ISSCC |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Uksong Kang, Hoeju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jin Ho Kim, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim |
8Gb 3D DDR3 DRAM using through-silicon-via technology. |
ISSCC |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Xin Yang 0010, Sakir Sezer, John V. McCanny, Dwayne Burns |
DDR3 based lookup circuit for high-performance network processing. |
SoCC |
2009 |
DBLP DOI BibTeX RDF |
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26 | Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura |
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme. |
IEEE J. Solid State Circuits |
2007 |
DBLP DOI BibTeX RDF |
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26 | Churoo Park, Hoeju Chung, Yun-Sang Lee, Jaekwan Kim 0003, JaeJun Lee, Moo Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Ki-Whan Song, Kyu-Hyoun Kim, Jung-Bae Lee, Changhyun Kim, Soo-In Cho |
A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. |
IEEE J. Solid State Circuits |
2006 |
DBLP DOI BibTeX RDF |
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26 | Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura |
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme. |
ISSCC |
2006 |
DBLP DOI BibTeX RDF |
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26 | Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, Jong-Cheol Lee, Dae-Gi Bae, Nam-Seog Kim, Kang-Young Kim, Young-Jae Son, Jeong-Suk Yang, Kwon-Il Sohn, Sung-Tae Kim, In-Yeol Lee, Kwang-Jin Lee, Tae-Gyoung Kang, Su-Chul Kim, Kee-Sik Ahn, Hyun-Geun Byun |
A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. |
IEEE J. Solid State Circuits |
2003 |
DBLP DOI BibTeX RDF |
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26 | Harold Pilo, Darren Anand, John Barth 0001, Steve Burns 0001, Phil Corson, Jim Covino, Steve Lamphier |
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. |
IEEE J. Solid State Circuits |
2003 |
DBLP DOI BibTeX RDF |
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26 | Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun |
Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface. |
CICC |
2003 |
DBLP DOI BibTeX RDF |
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