Search results for "DLL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
98	Bruce F. Cockburn, Keith Boyle	Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells.	CCECE	2006	DBLP DOI BibTeX RDF
84	Yating Wu, Wai Keung Wong, Shu Hung Leung, Y. S. Zhu	A Modified De-Correlated Delay Lock Loop with Better Static Response for Synchronous DS-CDMA Systems.	VTC Spring	2007	DBLP DOI BibTeX RDF
78	Seungsoo Yoo, Jun Tae Kim, Sun Yong Kim, Youngyoon Lee, Seokho Yoon	A novel tracking scheme in location systems.	ICUIMC	2008	DBLP DOI BibTeX RDF	ELP-DLL, EML-DLL, tracking bias, tracking bias compensation, location systems
74	Kuo-Hsing Cheng, Yu-Lung Lo	A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
60	Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang	A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
60	Atsushi Suzuki, Shoji Kawahito, Daisuke Miyazaki, Masanori Furuta	A digitally skew correctable multi-phase clock generator using a master-slave DLL.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
59	Michael H. Perrott	Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits.	DAC	2002	DBLP DOI BibTeX RDF	fractional-N, sigma, PLL, frequency, delta, DLL, synthesizer
56	Yong Shim, Youngkwon Jo, Soo Hwan Kim, Suki Kim, Kwanjun Cho	A register controlled delay locked loop using a TDC and a new fine delay line scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
56	Youngkwon Jo, Yong Shim, Soo Hwan Kim, Suki Kim, Kwanjun Cho	A mixed-structure delay locked-loop with wide range and fast locking.	ISCAS	2006	DBLP DOI BibTeX RDF
56	Tom Egan, Samiha Mourad	Design-for-testability for embedded delay-locked loops.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
56	Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu	A mixed-mode delay-locked loop for wide-range operation and multiphase outputs.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
56	Cheng Jia, Linda S. Milor	A BIST Solution for The Test of I/O Speed.	ITC	2003	DBLP DOI BibTeX RDF
56	Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu, Shu-Yin Hung	A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation.	IWSOC	2003	DBLP DOI BibTeX RDF
54	Deepak Venugopal, Guoning Hu, Nicoleta Roman	Intelligent virus detection on mobile devices.	PST	2006	DBLP DOI BibTeX RDF	common functionality, security, mobile, virus detection, DLL
47	Cédric Majek, Yann Deval, Hervé Lapuyade, Jean-Baptiste Bégueret	Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS-SOI, factorial delay locked loop, multi-standard frequency synthesizer, quadrature phase signals, voltage controlled delay element
47	Md. Ibrahim Faisal, Magdy A. Bayoumi	A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers.	ISCAS	2008	DBLP DOI BibTeX RDF
47	Chih-Hsing Lin, Ching-Te Chiu	A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
47	Pengfei Li 0001, Rizwan Bashirullah	A DLL Based Multiphase Hysteretic DC-DC Converter.	ISQED	2007	DBLP DOI BibTeX RDF
47	Vasco M. Manquinho, João Marques-Silva 0001	On Applying Cutting Planes in DLL-Based Algorithms for Pseudo-Boolean Optimization.	SAT	2005	DBLP DOI BibTeX RDF
45	Stephen K. Sunter, Aubin Roy	Noise-Insensitive Digital BIST for any PLL or DLL.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	BIST, Jitter, Design for test, PLL, Mixed-signal test, DLL
42	Taeho Kwon, Zhendong Su 0001	Automatic detection of unsafe component loadings.	ISSTA	2010	DBLP DOI BibTeX RDF	unsafe component loading, dynamic analysis
42	Enrique Barajas, R. Cosculluela, D. Coutinho, Diego Mateo, José Luis González 0001, I. Cairò, S. Banda, M. Ikeda	Interactive presentation: Behavioral modeling of delay-locked loops and its application to jitter optimization in ultra wide-band impulse radio systems.	DATE	2007	DBLP DOI BibTeX RDF
42	Xiaosheng Wang	A Generalized Decision Logic Language for Information Tables.	ICFIE	2007	DBLP DOI BibTeX RDF	Decision Logic Language, Information Tables, Rough Sets, Credibility, Decision Rules
42	Xiang Gao 0002, Eric A. M. Klumperink, Bram Nauta	Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers.	ISCAS	2007	DBLP DOI BibTeX RDF
42	Po-Jen Chuang, Young-Tzong Hsiao, Yu-Shian Chiu	An Efficient Value Predictor Dynamically Using Loop and Locality Properties.	J. Supercomput.	2004	DBLP DOI BibTeX RDF	loop and locality properties, benchmarks, value prediction, prediction accuracy, hardware cost, experimental performance evaluation
42	Jorge Calera-Rubio, José Oncina	Identifying Left-Right Deterministic Linear Languages.	ICGI	2004	DBLP DOI BibTeX RDF
42	DoRon B. Motter, Igor L. Markov	A Compressed Breadth-First Search for Satisfiability.	ALENEX	2002	DBLP DOI BibTeX RDF
40	Jaeyong Lee, Sungil Cho, Kwangsub Yoon	12bits 40mhz pipelined ADC with duty-correction circuit.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	adc(analog-to-digital converter), pipeline, cmos, dll
40	Rashed Zafar Bhatti, Monty Denneau, Jeff Draper	2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection
37	Young-Soo Ryu, Young-Shig Choi	A DLL Based Clock Synthesizer with Locking Status Indicator A DLL Based Clock Synthesizer with Locking Status Indicator.	J. Inform. and Commun. Convergence Engineering	2005	DBLP BibTeX RDF
33	Cheng Jia, Linda S. Milor	A BIST Circuit for DLL Fault Detection.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
33	Jinn-Shyan Wang, Yi-Ming Wang, Chun-Yuan Cheng, Yu-Chia Liu	An improved SAR controller for DLL applications.	ISCAS	2006	DBLP DOI BibTeX RDF
33	Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski	A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider.	CCECE	2006	DBLP DOI BibTeX RDF
33	Stefan Szeider	Backdoor Sets for DLL Subsolvers.	J. Autom. Reason.	2005	DBLP DOI BibTeX RDF	unit propagation, pure literal elimination, backdoor sets, W[P]-completeness, satisfiability, parameterized complexity
33	Mathieu Renaud, Yvon Savaria	A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
33	S. Nagavarapu, J. Yan, Edward K. F. Lee, Randall L. Geiger	An asynchronous data recovery/retransmission technique with foreground DLL calibration.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
28	Narayan Prasad, Mahesh K. Varanasi	Analysis and Optimization of Diagonally Layered Lattice Schemes for MIMO Fading Channels.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
28	Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani	0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops.	VLSI Design	2008	DBLP DOI BibTeX RDF
28	John Keane 0001, Tony Tae-Hyoung Kim, Chris H. Kim	An on-chip NBTI sensor for measuring PMOS threshold voltage degradation.	ISLPED	2007	DBLP DOI BibTeX RDF	locked loop, delay, aging, NBTI
28	Bob Stengel, Said Rami	A 90nm Quadrature Generator with Frequency Extension up to 4GHz.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Scott L. Rosen, John A. Stine, William J. Weiland	A MANET simulation tool to study algorithms for generating propagation maps.	WSC	2006	DBLP DOI BibTeX RDF
28	Volnei A. Pedroni, Ricardo U. Pedroni	PLL-less clock multiplier with self-adjusting phase symmetry.	ISCAS	2006	DBLP DOI BibTeX RDF
28	Ping-Ying Wang, C.-H. Chou, Hsueh-Wu Kao	Chaos in delay locked loop.	ISCAS	2006	DBLP DOI BibTeX RDF
28	Enrico Giunchiglia, Marco Maratea	optsat: A Tool for Solving SAT Related Optimization Problems.	JELIA	2006	DBLP DOI BibTeX RDF
28	Lei Shen, Fangni Chen, Shiju Li	Performance of Coherent Delay Lock Loop in the Presence of CW Interference and Additive Noise.	IMSCCS (1)	2006	DBLP DOI BibTeX RDF
28	Mahdi Nazm Bojnordi, Nariman Moezzi Madani, Mehdi Semsarzadeh, Ali Afzali-Kusha	An Efficient Clocking Scheme for On-Chip Communications.	APCCAS	2006	DBLP DOI BibTeX RDF
28	Enrico Giunchiglia, Marco Maratea	On the Relation Between Answer Set and SAT Procedures (or, Between cmodels and smodels).	ICLP	2005	DBLP DOI BibTeX RDF
28	Wern-Ho Sheen, Ming-Jou Chang, Cheng-Shong Wu	Performance analysis of noncoherent digital delay locked loops for direct sequence spread spectrum systems with Doppler shift and quantized adaptation.	IEEE Trans. Wirel. Commun.	2004	DBLP DOI BibTeX RDF
28	Ajay Askoolum	Building C# COM DLLs for APL.	ACM SIGAPL APL Quote Quad	2004	DBLP DOI BibTeX RDF
28	Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors	A Mixed-Mode Delay-Locked-Loop Architecture.	ICCD	2003	DBLP DOI BibTeX RDF
26	Pascal Vander-Swalmen, Gilles Dequen, Michaël Krajecki	On Multi-threaded Satisfiability Solving with OpenMP.	IWOMP	2008	DBLP DOI BibTeX RDF	collaborative, parallel, combinatorial optimization, satisfiability, OpenMP, dll
26	Richard J. Busman, Walter G. Fil, Andrei V. Kondrashev	Recycling APL Code into Client/Server Applications.	APL	1995	DBLP DOI BibTeX RDF	APL/W, DDE, Dyalog, MS Windows, ODBC, SHARP APL, downsizing APL applications, APL, SQL, client/server, DB2, DLL
25	James R. Burnham, Chih-Kong Ken Yang, Haitham A. Hindi	A stochastic jitter model for analyzing digital timing-recovery circuits.	DAC	2009	DBLP DOI BibTeX RDF	delay-locked loop (DLL), mean-time-between-failures (MTBF), timing margins, timing recovery circuits, Markov chain, stochastic model, jitter, bit-error-rate (BER)
19	Mohamed Kas, Abderrazak Chahi, Ibrahim Kajo, Yassine Ruichek	DLL-GAN: Degradation-level-based learnable adversarial loss for image enhancement.	Expert Syst. Appl.	2024	DBLP DOI BibTeX RDF
19	Jonas Pelgrims, Kris Myny, Wim Dehaene	An Ultrasonic Driver Array in Metal-Oxide Thin-Film Technology Using a Hybrid TFT-Si DLL Locking Architecture.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
19	Tao Wang, Jieyang Li, Di Hua, Liangbo Lei, Peng Cao, Peng Xu, Jiawei Xu 0001, Zhiliang Hong	A Fully Integrated Digital Polar Transmitter With Single-Ended Doherty PA and DLL-Based Three-Segment Hybrid DTC in 28 nm CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
19	Jisu Park, DaYeon Yoo, Nara Yun, Jihoon Lee, DaeYoub Kim	A Thread Chaining Attack for Bypassing a DLL Injection Monitoring System*.	ICCE	2024	DBLP DOI BibTeX RDF
19	Pedro Fernández-Álvarez, Ricardo J. Rodríguez	Module extraction and DLL hijacking detection via single or multiple memory dumps.	Forensic Sci. Int. Digit. Investig.	2023	DBLP DOI BibTeX RDF
19	Zhaowen Wang, Peter R. Kinget	A Very High Linearity Twin Phase Interpolator With a Low-Noise and Wideband Delta Quadrature DLL for High-Speed Data Link Clocking.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
19	Saurabh Kumar, Yatendra Kumar Singh	A Low-Phase-Noise Self-Aligned Sub-Harmonically Injection-Locked PLL Using Aperture Phase Detector-Based DLL Windowing Technique.	IEEE Access	2023	DBLP DOI BibTeX RDF
19	Sundaresan Ramachandran, Jeet Rami, Abhinav Shah, Kyounggon Kim, Digvijaysinh Rathod	Defence against crypto-ransomware families using dynamic binary instrumentation and DLL injection.	Int. J. Electron. Secur. Digit. Forensics	2023	DBLP DOI BibTeX RDF
19	Teng-Shen Yang, Huai-Yuan Hsieh, Liang-Hung Lu	A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a -70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
19	Shenglong Zhuo, Yuwei Wang, Tao Xia, Yifan Wu, Wei Zheng, Miao Sun, Zhihong Lin, Patrick Yin Chiang	A 200 MHz 14 W Pulsed Optical Illuminator With Laser Driver ASIC and On-Chip DLL-Based Time Interpolator for Indirect Time-of-Flight Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
19	Shahram Modanlou, Gholamreza Ardeshir, Mohammad Gholami	A general jitter analysis of DLL considering the jitter accumulation effect of loop capacitor.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
19	Yung-Chuan Su, Shi-Yu Huang	Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
19	Andres Asprilla, Andreia Cathelin, Yann Deval	0.45-mW 2.35-3.0 GHz Multiplying DLL with Calibration Loop in 28nm CMOS FD-SOI.	ESSCIRC	2023	DBLP DOI BibTeX RDF
19	Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim, Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-Il Lee, Jongbum Lee, Taeseong Jang, JunHyung Kim, Sanghee Kang, Jung-Bum Shin, Yanggyoon Loh, Chang-Yong Lee, Junmyung Woo, Hye-Seung Yu, Changhyun Bae, Reum Oh, Young-Soo Sohn, Changsik Yoo, Jooyoung Lee	A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL.	ISSCC	2023	DBLP DOI BibTeX RDF
19	Gaoyuan Pang, Brian Lee 0003, Jake Jung, Chris Eom	A Fast-Lock DLL with Prediction-Based Fast-Track FDL Structure for DDR5 SDRAMs.	ASICON	2023	DBLP DOI BibTeX RDF
19	Antonin Verdier, Romain Laborde, Mohamed Ali Kandi, Abdelmalek Benzekri	A SLAHP in the Face of DLL Search Order Hijacking.	UbiSec	2023	DBLP DOI BibTeX RDF
19	Zhaowen Wang, Yudong Zhang 0006, Yuka Onizuka, Peter R. Kinget	Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
19	Dong-Hyun Yoon, Dong-Kyu Jung, Kiho Seong, Jae-Soub Han, Keun-Yong Chung, Ju Eon Kim, Tony Tae-Hyoung Kim, Kwang-Hyun Baek	A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
19	Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu	A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
19	Xingyuan Tong, Jinwu Wu, Dong Chen	Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
19	Jun-Yu Yang, Shi-Yu Huang	Tiny Phase-Error Monitor for Fault and Soft-Error-Tolerant DLL to Support Graceful Degradation and Module-Level Testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
19	Yuhang Xie, Xufeng Liao, Xincai Liu, Lianxi Liu	A DLL-Based Offset Calibration Loop Technology for Wake-Up Receivers.	ICTA	2022	DBLP DOI BibTeX RDF
19	Jonas Pelgrims, Kris Myny, Wim Dehaene	A 24V Thin-Film Ultrasonic Driver for Haptic Feedback in Metal-Oxide Thin-Film Technology using Hybrid DLL Locking Architecture.	ESSCIRC	2022	DBLP DOI BibTeX RDF
19	Jeewan Lee, Yoonjae Choi, Chulwoo Kim	A 266-3750 MHz Wide-Range Adaptive Phase-Rotator-Based All Digital DLL for LPDDR5 Controllers.	ISCAS	2022	DBLP DOI BibTeX RDF
19	Shenglong Zhuo, Yuwei Wang, Tao Xia, Yifan Wu, Lichun Xie, Wei Zheng, Zhihong Lin, Miao Sun, Lei Zhao, Yajie Qin, Rui Bai 0001, Patrick Yin Chiang	An Integrated 200MHz 4A Pulsed Laser Driver with DLL-Based Time Interpolator for Indirect Time-of-Flight Applications.	ISCAS	2022	DBLP DOI BibTeX RDF
19	Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim	A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
19	Ching-Yuan Yang, Miao-Shan Li, Ai-Jia Chuang	A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
19	Andres Asprilla, David Cordova, Yann Deval, Hervé Lapuyade, François Rivet	28nm FDSOI Ultra Low Power 1.5-2.0 GHz Factorial-DLL Frequency Synthesizer.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
19	Fernando Caballero, Luis Merino	DLL: Direct LIDAR Localization. A map-based localization approach for aerial robots.	CoRR	2021	DBLP BibTeX RDF
19	Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera	A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation.	IEICE Trans. Electron.	2021	DBLP DOI BibTeX RDF
19	Duo Sheng, Chih-Hao Liu, Sih-Ying Chen, Bin-Yang Song, Ying-Chi Chiu, Ming-Han Cai	DLL-Based Transmit Beamforming IC for High -Frequency Ultrasound Medical Imaging System.	ICCE-TW	2021	DBLP DOI BibTeX RDF
19	Fernando Caballero, Luis Merino	DLL: Direct LIDAR Localization. A map-based localization approach for aerial robots.	IROS	2021	DBLP DOI BibTeX RDF
19	Taeyeon Kim, Jongsun Kim	A 0.8-3.5 GHz Shared TDC-Based Fast-Lock All-Digital DLL with a Built-in DCC.	ISCAS	2021	DBLP DOI BibTeX RDF
19	Siman Li, Chris Eom, Jake Jung, Brian Lee 0003, Edwin Kim, Kanyu Cao	Adaptive DLL Update Scheme for Power Fluctuation Immunity Using Phase Error Detector.	ASICON	2021	DBLP DOI BibTeX RDF
19	Dong-Hyun Yoon, Dong-Kyu Jung, Kiho Seong, Tae-Hyeok Eom, Jae-Soub Han, Ju Eon Kim, Tony Tae-Hyoung Kim, Kwang-Hyun Baek	A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement.	A-SSCC	2021	DBLP DOI BibTeX RDF
19	Yen-Kuei Lu, Miao-Shan Li, Ching-Yuan Yang, Chin-Lung Lin	A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth.	A-SSCC	2021	DBLP DOI BibTeX RDF
19	Raman Thukral, Mohit Goswami, Sharayu Jagtap, Sandeep Goyal, Shalabh Gupta	A Multi-Octave Frequency Range SerDes with a DLL Free Receiver.	VDAT	2021	DBLP DOI BibTeX RDF
19	Wafa Feneniche, Khaled Rouabah, Mustapha Flissi, Salim Atia, Salah Eddine Mezaache, Sabrina Meguellati	Unambiguous method for DLL BOC signals tracking.	Int. J. Commun. Syst.	2020	DBLP DOI BibTeX RDF
19	Dongkyun Kim, Kibong Koo, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Ki Hun Kwon, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Jong-Sam Kim, Seungwook Oh, Minsu Park, Dain Im, Yongsung Lee, Mingyu Park, Jonghyuck Choi, Junhyun Chun, Kyowon Jin, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Changhyun Kim, Minsik Han	A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
19	Wataru Matsuda, Mariko Fujimoto, Takuho Mitsunaga	Detection of Malicious Tools by Monitoring DLL Using Deep Learning.	J. Inf. Process.	2020	DBLP DOI BibTeX RDF
19	Kyungho Ryu, Kil-Hoon Lee, Jung-Pil Lim, Jinho Kim, Han Su Pae, Junho Park, Hyun-Wook Lim, Jae-Youl Lee	An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
19	Dongjun Park, Jongsun Kim	A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL.	Circuits Syst. Signal Process.	2020	DBLP DOI BibTeX RDF
19	Nico Angeli, Klaus Hofmann	Low-Power All-Digital Multiphase DLL Design Using a Scalable Phase-to-Digital Converter.	IEEE Trans. Circuits Syst. I Fundam. Theory Appl.	2020	DBLP DOI BibTeX RDF
19	Youngbog Yoon, Hyunsu Park, Chulwoo Kim	A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
19	Soyeong Shin, Han-Gon Ko, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Doobock Lee, Hae-Kang Jung, Suhwan Kim, Deog-Kyoon Jeong	A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
19	Jaehong Jung, Sangdon Jung, Kyungmin Lee, Jun-Hee Jung, Seungjin Kim, Byungki Han, Seunghyun Oh, Jongwoo Lee	A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
19	Junwon Kim, Jiho Shin, Jung-Taek Seo	Research on PEB-LDR Data Analysis Technique for DLL Injection Detection on ICS Engineering Workstation.	ICEA	2020	DBLP DOI BibTeX RDF