Search results for "DOMINO"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
114	Gin Yee, Carl Sechen	Clock-Delayed Domino for Adder and Combinational Logic Desig.	ICCD	1996	DBLP DOI BibTeX RDF
110	Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita	Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	Clock-delayed domino circuit, Fault simulation, crosstalk fault
107	David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah	Timing verification of sequential domino circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	domino gates, sequential domino circuits, static timing verification, logic testing, input signals
103	Jovanka Ciric, Gin Yee, Carl Sechen	Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic.	DATE	2000	DBLP DOI BibTeX RDF
103	Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang	Charge sharing fault analysis and testing for CMOS domino logic circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors
100	Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone	Charge Sharing Fault Detection for CMOS Domino Logic Circuits.	DFT	1999	DBLP DOI BibTeX RDF	charge sharing, cs-vulnerability, pseudo gate, ATPG, domino circuit
92	Seoksoo Yoon, Seok-Ryong Yoon, Seon Wook Kim, Chulwoo Kim	Charge-Sharing-Problem Reduced Split-Path Domino Logic.	VLSI Design	2004	DBLP DOI BibTeX RDF
92	Min Zhao 0001, Sachin S. Sapatnekar	Timing-driven partitioning and timing optimization of mixedstatic-domino implementations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
92	Maik Bollmann, Rainer Hoischen, Michael Jesikiewicz, Christoph Justkowski, Bärbel Mertsching	Playing Domino: A Case Study for an Active Vision System.	ICVS	1999	DBLP DOI BibTeX RDF
92	Hans L. Bodlaender, Joost Engelfriet	Domino Treewith (Extended Abstract).	WG	1994	DBLP DOI BibTeX RDF
89	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Low-power dual Vth pseudo dual Vdd domino circuits.	SBCCI	2004	DBLP DOI BibTeX RDF	NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages
89	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Optimal Timing for Skew-Tolerant High-Speed Domino Logic.	ISVLSI	2002	DBLP DOI BibTeX RDF	keeper, optimal timing, noise, skew, domino logic, dynamic circuit
87	Rouwaida Kanj, Elyse Rosenbaum	Critical evaluation of SOI design guidelines.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
82	Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer	False-Noise Analysis for Domino Circuits.	DATE	2004	DBLP DOI BibTeX RDF
82	Gin Yee, Carl Sechen	Clock-delayed domino for dynamic circuit design.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
82	Erich Grädel	Domino Games with an Application to the Complexity of Boolean Algebras with Bounded Quantifier Alternations.	STACS	1988	DBLP DOI BibTeX RDF
78	Aiqun Cao, Ruibing Lu, Chen Li 0004, Cheng-Kok Koh	Postlayout optimization for synthesis of Domino circuits.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	optimization, synthesis, Domino logic
78	Andrea Frosini, Giulia Simi	The Reconstruction of a Bicolored Domino Tiling from Two Projections.	DGCI	2002	DBLP DOI BibTeX RDF	Domino tiling, Reconstruction Problem, NP-completeness
76	Mohab Anis, Mohamed W. Allam, Mohamed I. Elmasry	Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
71	Peiyi Zhao, Jason McNeely, Magdy A. Bayoumi, Pradeep Kumar Golconda, Weidong Kuang	A Low Power Domino with Differential-Controlled-Keeper.	ISCAS	2007	DBLP DOI BibTeX RDF
71	Wei Ling, Yvon Savaria	Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations.	ISQED	2005	DBLP DOI BibTeX RDF
71	Kwang-Il Oh, Lee-Sup Kim	A clock delayed sleep mode domino logic for wide dynamic OR gate.	ISLPED	2003	DBLP DOI BibTeX RDF	clock delay, low power, leakage, sleep mode, dynamic circuits
71	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain.	DATE	2002	DBLP DOI BibTeX RDF
71	Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita	Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
71	Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang	Charge-sharing alleviation and detection for CMOS domino circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
71	Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang	Skew-tolerant high-speed (STHS) domino logic.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
67	Zhiyu Liu, Volkan Kursun	Leakage current starved domino logic.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, domino logic, subthreshold leakage current, dual threshold voltage
67	Zhiyu Liu, Volkan Kursun	Leakage Biased Sleep Switch Domino Logic.	ISQED	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, Domino logic, subthreshold leakage current, dual threshold voltage
67	Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell	Electrical Behavior of GOS Fault affected Domino Logic Cell.	DELTA	2006	DBLP DOI BibTeX RDF	Gate-Oxide Short (GOS), Electrical analysis Boolean test, Domino logic, Defect modeling
67	Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi	A high speed and leakage-tolerant domino logic for high fan-in gates.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high speed, noise immunity, deep submicron, fan-in, domino
67	Aiqun Cao, Cheng-Kok Koh	Post-layout logic optimization of domino circuits.	DAC	2004	DBLP DOI BibTeX RDF	optimization, synthesis, layout, domino logic
67	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Low-swing clock domino logic incorporating dual supply and dual threshold voltages.	DAC	2002	DBLP DOI BibTeX RDF	low swing clock, low power, domino logic, dual supply voltage, dual threshold voltage
67	Eric W. MacDonald, Nur A. Touba	Testing domino circuits in SOI technology.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	silicon-on-insulator, SOI technology, dynamic circuit styles, fault modeling analysis, overall fault coverage, parasitic bipolar leakage, CMOS logic, logic testing, integrated circuit testing, automatic testing, fault simulation, CMOS logic circuits, leakage currents, domino circuits
67	Alvernon Walker, Algernon P. Henry, Parag K. Lala	An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring.	DFT	1997	DBLP DOI BibTeX RDF	bridging faults detection, CMOS domino logic circuits, dynamic power supply current monitoring, CMOS logic circuits, transient current
65	Debasis Samanta, Nishant Sinha 0001, Ajit Pal	Synthesis of High Performance Low Power Dynamic CMOS Circuits.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
64	Malgorzata Domino, Krzysztof Domino, Zdzislaw Gajewski	An application of higher order multivariate cumulants in modelling of myoelectrical activity of porcine uterus during early pregnancy.	Biosyst.	2019	DBLP DOI BibTeX RDF
61	Alvaro A. Cárdenas, Svetlana Radosavac, John S. Baras	Evaluation of detection algorithms for MAC layer misbehavior: theory and experiments.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	CUSUM, SPRT, intrusion detection, DOMINO, misbehavior, IEEE 802.11 MAC
60	Hadrien Cambazard, John Horan, Eoin O'Mahony, Barry O'Sullivan	Fast and Scalable Domino Portrait Generation.	CPAIOR	2008	DBLP DOI BibTeX RDF
60	Massimo Alioto, Gaetano Palumbo, Melita Pennisi	Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic.	PATMOS	2008	DBLP DOI BibTeX RDF
60	Dhiren M. Parmar, Monalisa Sarma, Debasis Samanta	A Novel Approach to Domino Circuit Synthesis.	VLSI Design	2007	DBLP DOI BibTeX RDF
60	Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy 0001	Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies.	ISQED	2004	DBLP DOI BibTeX RDF
60	Ge Yang 0004, Zhongda Wang, Sung-Mo Kang	Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies.	VLSI Design	2004	DBLP DOI BibTeX RDF
60	Volkan Kursun, Eby G. Friedman	Domino logic with variable threshold voltage keeper.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
60	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Timing constraints for domino logic gates with timing-dependent keepers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
60	Rahul Kundu, R. D. (Shawn) Blanton	ATPG for Noise-Induced Switch Failures in Domino Logic.	ICCAD	2003	DBLP DOI BibTeX RDF
60	Roy Mader, Ivan S. Kourtev	Reduced dynamic swing domino logic.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF
60	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Noise constrained transistor sizing and power optimization for dual Vst domino logic.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
60	Sungwook Kim, Gerald E. Sobelman	Efficient digit-serial FIR filters with skew-tolerant domino.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
60	Ramin Rafati, A. Z. Charaki, G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith	Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D3L (D4L) logic styles.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
60	Hendrawan Soeleman, Kaushik Roy 0001, Bipul Chandra Paul	Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic.	VLSI Design	2001	DBLP DOI BibTeX RDF
60	Jonathan T.-Y. Chang, Edward J. McCluskey	Detecting resistive shorts for CMOS domino circuits.	ITC	1998	DBLP DOI BibTeX RDF
60	Niraj K. Jha	Testing for multiple faults in domino-CMOS logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
56	Jinhui Wang, Lei Zuo, Na Gong, Daming Gao, Shuqin Geng, Wang Zhang, Ligang Hou, Xiaohong Peng, Wuchen Wu	Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks.	ISNN (1)	2009	DBLP DOI BibTeX RDF	Dual threshold domino OR, Leakage power, Speed, Wavelet Neural Networks
56	Bo Fu, Qiaoyan Yu, Paul Ampadu	Energy-delay minimization in nanoscale domino logic.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	delay, energy, leakage, low voltage, domino
56	Zhiyu Liu, Volkan Kursun	Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages.	ISQED	2006	DBLP DOI BibTeX RDF	Low Voltage Swing, Gate Oxide Leakage, Domino Logic, Subthreshold Leakage, Dual Threshold Voltage
56	Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang	Minimum delay optimization for domino circuits - a coupling-aware approach.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Logic synthesis, coupling, domino logic, delay minimization
56	Jung-Lin Yang, Erik Brunvand	Using dynamic domino circuits in self-timed systems.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	asynchronous circuits, domino logic, self-timed circuits
56	Ayoob E. Dooply, Kenneth Y. Yun	Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines.	ARVLSI	1999	DBLP DOI BibTeX RDF	Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault
56	Ron Lin	Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes.	VLSI Design	1997	DBLP DOI BibTeX RDF	shift switching, asynchronous VLSI comparator, precharged CMOS domino logic, VLSI, semaphore
54	Min Zhao 0001, Sachin S. Sapatnekar	Timing-driven partitioning for two-phase domino and mixed static/domino implementations.	ICCAD	1999	DBLP DOI BibTeX RDF
54	Volkan Kursun, Eby G. Friedman	Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits.	ISQED	2004	DBLP DOI BibTeX RDF
54	Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry	High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies.	ISLPED	2000	DBLP DOI BibTeX RDF
49	Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng	A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
49	Yi Liang, Lei Wang 0004, Jianfeng Zhan, Ruihua Di	A Performance Model for Domino Mail Server.	CSSE (3)	2008	DBLP DOI BibTeX RDF
49	Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou	Testable Designs of Multiple Precharged Domino Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
49	Zhiyu Liu, Volkan Kursun	PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
49	Yi-Yu Liu, TingTing Hwang	Crosstalk-Aware Domino-Logic Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
49	Yi-Yu Liu, TingTing Hwang	Crosstalk-aware domino logic synthesis.	DATE	2006	DBLP DOI BibTeX RDF
49	Chris Worman, Boting Yang	On the Computation of Colored Domino Tilings of Simple and Non-simple Orthogonal Polygons.	ISAAC	2005	DBLP DOI BibTeX RDF
49	William J. Cook, Daniel G. Espinoza, Marcos Goycoolea	A Study of Domino-Parity and k-Parity Constraints for the TSP.	IPCO	2005	DBLP DOI BibTeX RDF
49	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Low-power domino circuits using NMOS pull-up on off-critical paths.	ASP-DAC	2005	DBLP DOI BibTeX RDF
49	Amir Amirabadi, Y. Mortazavi, Nariman Moezzi Madani, Ali Afzali-Kusha, Mehrdad Nourani	Domino logic with an efficient variable threshold voltage keeper.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
49	Yonghee Im, Kaushik Roy 0001	LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits.	ISVLSI	2003	DBLP DOI BibTeX RDF
49	P. C. Chen, James B. Kuo	Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
49	Yonghee Im, Kaushik Roy 0001	A logic-aware layout methodology to enhance the noise immunity of domino circuits.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
49	Rahul Kundu, R. D. (Shawn) Blanton	Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk.	ITC	2003	DBLP DOI BibTeX RDF
49	Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm	A technique for Improving dual-output domino logic.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
49	B. Chappell, Xinning Wang, Priyadarsan Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain	A System-Level Solution to Domino Synthesis with 2 GHz Application.	ICCD	2002	DBLP DOI BibTeX RDF
49	Volkan Kursun, Eby G. Friedman	Low swing dual threshold voltage domino logic.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF
49	Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou	On Testability of Multiple Precharged Domino Logic.	ISQED	2000	DBLP DOI BibTeX RDF
49	Tan-Li Chou, Kaushik Roy 0001	Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
49	Niraj K. Jha	Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
49	Alan M. Sykes	A second generation DOMINO for statisticians.	APL	1987	DBLP DOI BibTeX RDF	APL
45	Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya	An Efficient Parallel Prefix Sums Architecture with Domino Logic.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	shift switching, binary prefix sums, binary counting, VLSI design, scalable architectures, domino logic, Hardware-algorithms
45	Min Zhao 0001, Sachin S. Sapatnekar	Technology mapping algorithms for domino logic.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	XOR/XNOR logic, dual-monotonic gates, parameterized library, phase assignment, synthesis, technology mapping, Domino logic
45	C. Mohan 0001	A Database Perspective on Lotus Domino/Notes.	SIGMOD Conference	1999	DBLP DOI BibTeX RDF	Lotus Domino, heterogeneous data access, groupware, replication, recovery, logging, semi-structured data, Lotus Notes, ARIES, Notes
45	Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya	An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic.	IPPS/SPDP	1999	DBLP DOI BibTeX RDF	Special-purpose parallel architectures, digital signal processing, computer arithmetic, VLSI design, domino logic
43	Volkan Kursun, Zhiyu Liu	Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies.	ISCAS	2006	DBLP DOI BibTeX RDF
43	T. J. Thorp, G. S. Yee, Carl M. Sechen	Design and synthesis of dynamic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
43	Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy 0001	Synthesis of Selectively Clocked Skewed Logic Circuits.	ISQED	2002	DBLP DOI BibTeX RDF
43	Alexandre Solomatnikov, Kaushik Roy 0001, Cheng-Kok Koh, Dinesh Somasekhar	Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family.	ICCD	2000	DBLP DOI BibTeX RDF
43	Eric Gayles, Kevin P. Acken, Robert Michael Owens, Mary Jane Irwin	A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
43	Norman D. Thomson	Applying Matrix Divide in APL and J.	APL	1994	DBLP DOI BibTeX RDF	APL, J
40	Walid Elgharbawy, Pradeep Golconda, Magdy A. Bayoumi	Noise-tolerant high fan-in dynamic CMOS circuit design.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high fan-in domino, CMOS, noise-tolerant, subthreshold leakage, dynamic circuits
40	Fatih Hamzaoglu, Mircea R. Stan	Circuit-level techniques to control gate leakage for sub-100nm CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	low power, MTCMOS, gate leakage, domino circuits
40	Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser	Logic optimization by output phase assignment in dynamic logic synthesis.	ICCAD	1996	DBLP DOI BibTeX RDF	dynamic logic synthesis, logic duplication, minimum logic duplication penalty, output phase assignment, logic design, heuristic algorithms, optimal algorithms, domino logic, logic optimization, area overhead, logic functions, inverters
38	Maxim Raya, Imad Aad, Jean-Pierre Hubaux, Alaeddine El Fawal	DOMINO: Detecting MAC Layer Greedy Behavior in IEEE 802.11 Hotspots.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	greedy behavior, IEEE 802.11, medium access control, network monitoring, wireless local-area networks, Public networks
38	Amir Amirabadi, A. Chehelcheraghi, S. H. Rasouli, A. Seyedi, Ali Afzali-Kusha	Low power and high performance clock delayed domino logic using saturated keeper.	ISCAS	2006	DBLP DOI BibTeX RDF
38	Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Ivan E. Sutherland	GasP Control for Domino Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
38	Aiqun Cao, Ruibing Lu, Cheng-Kok Koh	Post-layout logic duplication for synthesis of domino circuits with complex gates.	ASP-DAC	2005	DBLP DOI BibTeX RDF