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1983-1992 (15) 1993-1994 (30) 1995 (15) 1996 (21) 1997 (33) 1998 (31) 1999 (53) 2000 (55) 2001 (52) 2002 (45) 2003 (50) 2004 (35) 2005 (50) 2006 (56) 2007 (58) 2008 (66) 2009 (75) 2010 (58) 2011 (61) 2012 (77) 2013 (68) 2014 (94) 2015 (119) 2016 (124) 2017 (131) 2018 (126) 2019 (136) 2020 (96) 2021 (123) 2022 (122) 2023 (134) 2024 (37)
Publication types (Num. hits)
article(827) book(1) data(1) inproceedings(1400) phdthesis(17)
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Found 2246 publication records. Showing 2246 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
134Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik An approach for adaptive DRAM temperature and power management. Search on Bibsonomy ICS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF power, temperature, DRAM
127Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti, James E. Smith 0001 Power-Efficient DRAM Speculation. Search on Bibsonomy HPCA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
126Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge High-Performance DRAMs in Workstation Environments. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF DRAM architectures, DRAM performance, DRAM systems, DDR DRAM, Direct Rambus DRAM, PC100 SDRAM, DDR2 DRAM, system modeling
118Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang 0010, Howard David DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. Search on Bibsonomy ISPASS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF channel bandwidth utilization, DRAM-level prefetching, dynamic random access memory, fully-buffered DIMM, dual in-line memory module, redundant bandwidth, memory block, L2 cache block, DRAM power consumption, SPEC2000 program, software cache prefetching, idle memory latency, power saving, multicore processor, memory controller, interconnect structure, DRAM chip
108Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors. Search on Bibsonomy ARVLSI The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
105George L. Yuan, Ali Bakhoda, Tor M. Aamodt Complexity effective memory access scheduling for many-core accelerator architectures. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF graphics processors, on-chip interconnection networks, memory controller
102Bianca Schroeder, Eduardo Pinheiro, Wolf-Dietrich Weber DRAM errors in the wild: a large-scale field study. Search on Bibsonomy SIGMETRICS/Performance The full citation details ... 2009 DBLP  DOI  BibTeX  RDF dimm, dram reliability, ecc, hard error, empirical study, memory, soft error, dram, large-scale systems, data corruption
102Taku Ohsawa, Koji Kai, Kazuaki J. Murakami Optimizing the DRAM refresh count for merged DRAM/logic LSIs. Search on Bibsonomy ISLPED The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
99Yangyang Pan, Tong Zhang 0002 Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking. Search on Bibsonomy ASAP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
96Mrinmoy Ghosh, Hsien-Hsin S. Lee Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. Search on Bibsonomy MICRO The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
96Jahangir Hasan, Satish Chandra 0001, T. N. Vijaykumar Efficient Use of Memory Bandwidth to Improve Network Processor Throughput. Search on Bibsonomy ISCA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
96Yangyang Pan, Tong Zhang 0002 DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF dram-based fpga, memory stacking, 3d integration
96Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi Rethinking DRAM design and organization for energy-constrained multi-cores. Search on Bibsonomy ISCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF chipkill, dram architecture, subarrays, energy-efficiency, locality
86Scott Beamer, Chen Sun 0003, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic Re-architecting DRAM memory systems with monolithically integrated silicon photonics. Search on Bibsonomy ISCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF dram architecture, energy-efficiency, silicon photonics
86Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik A power and temperature aware DRAM architecture. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF page hit aware write buffer, power, temperature, DRAM
82Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM. Search on Bibsonomy HPCA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
80Youhei Zenda, Koji Nakamae, Hiromu Fujioka Cost Optimum Embedded DRAM Design by Yield Analysis. Search on Bibsonomy MTDT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
80Haifeng Yu, Gershon Kedem DRAM-Page Based Prediction and Prefetching. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
77Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt Improving memory bank-level parallelism in the presence of prefetching. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
77Onur Mutlu, Thomas Moscibroda Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. Search on Bibsonomy MICRO The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
70Pei-Lin Pai DRAM Industry Trend. Search on Bibsonomy MTDT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
70Zhichun Zhu, Zhao Zhang 0010 A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. Search on Bibsonomy HPCA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
70Anru Wang, Wayne Wei-Ming Dai Area-IO DRAM/logic integration with system-in-a-package (SiP). Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
70Markus Rudack, Dirk Niggemeyer Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
67Zhao Zhang 0010, Zhichun Zhu, Xiaodong Zhang 0001 Design and Optimization of Large Size and Low Overhead Off-Chip Caches. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
67Ahmed M. Amin, Zeshan Chishti Rank-aware cache replacement and write buffering to improve DRAM energy efficiency. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF DRAM energy efficiency, cache replacement, write buffer
67Kshitij Sudan, Niladrish Chatterjee, David W. Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis Micro-pages: increasing DRAM efficiency with locality-aware data placement. Search on Bibsonomy ASPLOS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF dram row-buffer management, data placement
67Qi Wu 0006, Jian-Qiang Lu, Kenneth Rose, Tong Zhang 0002 Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF three-dimentional integration, dram, decoupling capacitor
67Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger Architecting phase change memory as a scalable dram alternative. Search on Bibsonomy ISCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF dram alternative, performance, scalability, power, energy, phase change memory, pcm, endurance
67Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Zhichun Zhu Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. Search on Bibsonomy ISCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF bandwidth decoupling, decoupled DIMM, DRAM memories
67Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin Fault models for embedded-DRAM macros. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF memory testing, embedded DRAM
67Zaid Al-Ars, Ad J. van de Goor DRAM Specific Approximation of the Faulty Behavior of Cell Defects. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF memory specific fault analysis, approximating dynamic behavior, memory testing, DRAM
64Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers Scalable high performance main memory system using phase-change memory technology. Search on Bibsonomy ISCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF dram caching, phase change memory, wear leveling
64Chin-Te Kao, Sam Wu, Jwu E. Chen A case study of failure analysis and guardband determination for a 64M-bit DRAM. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF guardband determination, prevention strategy, test derivation, test cost, 64 Mbit, integrated circuit testing, yield, DRAM, failure analysis, failure analysis, test selection, DRAM chips, product quality, integrated circuit yield, integrated circuit economics
64Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter Combined DRAM and logic chip for massively parallel systems. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits
60Rakesh S. Anigundi, Hongbin Sun 0001, Jian-Qiang Lu, Kenneth Rose, Tong Zhang 0002 Architecture design exploration of three-dimensional (3D) integrated DRAM. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
60Ibrahim Hur, Calvin Lin A comprehensive approach to DRAM power management. Search on Bibsonomy HPCA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
60Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi Effective Management of DRAM Bandwidth in Multicore Processors. Search on Bibsonomy PACT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
60Li Zhao 0002, Ravi R. Iyer 0001, Ramesh Illikkal, Donald Newell Exploring DRAM cache architectures for CMP server platforms. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
60Vasily G. Moshnyaga, Hua Vo, Glenn Reinman, Miodrag Potkonjak Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
60Haakon Dybdahl, Marius Grannæs, Lasse Natvig Cache Write-Back Schemes for Embedded Destructive-Read DRAM. Search on Bibsonomy ARCS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
60Anru Wang, Wayne Wei-Ming Dai Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP). Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
60Zhao Zhang 0010, Zhichun Zhu, Xiaodong Zhang 0001 Cached DRAM for ILP Processor Memory Access Latency Reduction. Search on Bibsonomy IEEE Micro The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
60Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin Hardware and Software Techniques for Controlling DRAM Power Modes. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF low power compilation, software-directed energy management, low power, Memory architecture
60Vinodh Cuppu, Bruce L. Jacob Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?. Search on Bibsonomy ISCA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Systems Application Architecture
60Brian Davis, Bruce L. Jacob, Trevor N. Mudge The New DRAM Interfaces: SDRAM, RDRAM and Variants. Search on Bibsonomy ISHPC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
57Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum Impact of JVM superoperators on energy consumption in resource-constrained embedded systems. Search on Bibsonomy LCTES The full citation details ... 2008 DBLP  DOI  BibTeX  RDF superoperators, embedded systems, java virtual machine, energy estimation, profile-guided optimization
57G. Jack Lipovski A four megabit Dynamic Systolic Associative Memory chip. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
57Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF memory technology, dynamic voltage scaling, DRAM, molecular electronics, molecular memory, low-power memory
57Xiaobo Fan, Carla Schlatter Ellis, Alvin R. Lebeck Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets. Search on Bibsonomy PACS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Modeling, Petri Nets, DRAM, Memory Controller, Control Policy
51Bill Lin 0001, Jun (Jim) Xu, Nan Hua, Hao Wang 0006, Haiquan (Chuck) Zhao A randomized interleaved DRAM architecture for the maintenance of exact statistics counters. Search on Bibsonomy SIGMETRICS Perform. Evaluation Rev. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
51Gabriel H. Loh Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
51Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Eugene Gorbatov, Howard David, Zhichun Zhu Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. Search on Bibsonomy MICRO The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
51Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt Prefetch-Aware DRAM Controllers. Search on Bibsonomy MICRO The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
51Mohammed G. Khatib, Berend-Jan van der Zwaag, Pieter H. Hartel, Gerard J. M. Smit Interposing Flash between Disk and DRAM to Save Energy for Streaming Workloads. Search on Bibsonomy ESTIMedia The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
51Jike Chong, Chidamber Kulkarni, Gordon J. Brebner Building a flexible and scalable DRAM interface for networking applications on FPGAs. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
51Jyi-Tsong Lin, Mike Chang A New 1T DRAM Cell With Enhanced Floating Body Ef. Search on Bibsonomy MTDT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
51Lars Friebe, Yoshikazu Yabe, Masato Motomura A Study of Channeled DRAM Memory Architectures. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
51Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang A Programmable BIST Core for Embedded DRAM. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
51Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge A Performance Comparison of Contemporary DRAM Architectures. Search on Bibsonomy ISCA The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
48Girish B. C., R. Govindarajan A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor. Search on Bibsonomy QEST The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
48Vasily G. Moshnyaga, Hoa Vo, Glenn Reinman, Miodrag Potkonjak Handheld System Energy Reduction by OS-Driven Refresh. Search on Bibsonomy PATMOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
48Qi Zhao 0006, Jun (Jim) Xu, Zhen Liu Design of a novel statistics counter architecture with optimal space and time efficiency. Search on Bibsonomy SIGMETRICS/Performance The full citation details ... 2006 DBLP  DOI  BibTeX  RDF statistics counter, data streaming, router
48Jung Ho Ahn, Mattan Erez, William J. Dally Architecture - The design space of data-parallel memory systems. Search on Bibsonomy SC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
48Laurent Lopez, Jean-Michel Portal, Didier Née A New Embedded Measurement Structure for eDRAM Capacitor. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
48Philip Machanick Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
48Joohee Kim, Marios C. Papaefthymiou Block-based multiperiod dynamic memory design for low data-retention power. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
48Jorge García-Vidal, Jesús Corbal, Llorenç Cerdà, Mateo Valero Design and Implementation of High-Performance Memory Systems for Future Packet Buffers. Search on Bibsonomy MICRO The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
48Ananth Hegde, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin VL-CDRAM: variable line sized cached DRAMs. Search on Bibsonomy CODES+ISSS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF CDRAM, VL-CDRAM, variable line, energy
48Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Eugene Gorbatov, Howard David, Zhao Zhang 0010 Software thermal management of dram memory for multicore systems. Search on Bibsonomy SIGMETRICS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF thermal management, DRAM memories
48Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang 0010 Thermal modeling and management of DRAM memory systems. Search on Bibsonomy ISCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF thermal management, thermal modeling, DRAM memories
45Zhichun Zhu, Zhao Zhang 0010, Xiaodong Zhang 0001 Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. Search on Bibsonomy HPCA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF DRAM configurations, fine-grain priority scheduling, memory-intensive applications and multi-channel memory systems
45Wei-Fen Lin, Steven K. Reinhardt, Doug Burger Designing a Modern Memory Hierarchy with Hardware Prefetching. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Rambus DRAM, caches, Prefetching, memory bandwidth, spatial locality, memory system design
45Balasubramanya Bhat, Frank Mueller 0001 Making DRAM Refresh Predictable. Search on Bibsonomy ECRTS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF DRAM Refresh, Real-Time Systems, Timing Analysis, DRAM, Worst-Case Execution Time, Timing Predictability
45Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John The virtual write queue: coordinating DRAM and last-level cache policies. Search on Bibsonomy ISCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache
45Ki Chul Chun, Pulkit Jain, Chris H. Kim A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF 3T DRAM, gain cell, retention time, cache, static power, embedded DRAM
42Sying-Jyan Wang, Chen-Jung Wei Efficient built-in self-test algorithm for memory. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF built-in self-test algorithm, built-in self test, BIST, DRAM, test patterns, pseudorandom testing, coupling faults, DRAM chips
41Ciji Isen, Lizy Kurian John ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF allocated and freed memory states, cross-boundary or cross-layer architecture optimizations, memory power and energy, program semantic aware architecture
41Daniel Schmidt 0001, Norbert Wehn DRAM power management and energy consumption: a critical assessment. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF modelling, measurement, power management, SDRAM
41Vijay Khawshe, Kapil Vyas, Renu Rangnekar, Prateek Goyal, Vijay Krishna, Kashinath Prabhu, Pravin Kumar Venkatesan, Leneesh Raghavan, Rajkumar Palwai, M. Thrivikraman, Kunal Desai, Abhijit Abhyankar A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
41Martin Versen, Achim Schramm, Jan Schnepp, Dorina Diaconescu Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
41Chan-Kyung Kim, Bai-Sun Kong, Chil-Gee Lee, Young-Hyun Jun CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
41Chiyuan Ma, Shuming Chen A DRAM Precharge Policy Based on Address Analysis. Search on Bibsonomy DSD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Motoi Ichihashi, Haruki Toda Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Masaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
41Virantha N. Ekanayake, Rajit Manohar Asynchronous DRAM Design and Synthesis. Search on Bibsonomy ASYNC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Wei-Chung Cheng, Massoud Pedram Power-optimal encoding for a DRAM address bus. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
41Masashi Hashimoto Adder Merged DRAM Architecture. Search on Bibsonomy MTDT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
41Wei-Fen Lin, Steven K. Reinhardt, Doug Burger Reducing DRAM Latencies with an Integrated Memory Hierarchy Design. Search on Bibsonomy HPCA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
41Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin DRAM Energy Management Using Software and Hardware Directed Power Mode Control. Search on Bibsonomy HPCA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Low Power Compilation, Software-Directed Energy Management, Low Power, Memory Architecture
41Daisuke Kawakami, Yuichiro Shibata, Hideharu Amano A prototype chip of multicontext FPGA with DRAM for virtual hardware. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
41Brian R. Kessler, Jeffrey H. Dreibelbis, Tim McMahon, Joshua S. McCloy, Rex Kho BIST-Based Bitfail Mapping of an Embedded DRAM. Search on Bibsonomy MTDT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
41Sunho Chang, Lee-Sup Kim Design trade-off in merged DRAM logic for video signal processing. Search on Bibsonomy ISCAS (5) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
41Wei-Chung Cheng, Massoud Pedram Power-optimal encoding for DRAM address bus (poster session). Search on Bibsonomy ISLPED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
41Matthias Gries The Impact of Recent DRAM Architectures on Embedded Systems Performance. Search on Bibsonomy EUROMICRO The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
41Shinji Miyano, Katsuhiko Sato, Kenji Numata Universal Test Interface for Embedded-DRAM Testing. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
41Roderick McConnell, Udo Möller, Detlev Richter How we test Siemens Embedded DRAM Cores. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
41Tzi-cker Chiueh, Srinidhi Varadarajan Design and Evaluation of a DRAM-based Shared Memory ATM Switch. Search on Bibsonomy SIGMETRICS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
41John Poulton An Embedded DRAM for CMOS ASICs. Search on Bibsonomy ARVLSI The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
38Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger Use ECP, not ECC, for hard failures in resistive memories. Search on Bibsonomy ISCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF hard failures, resistive memories, memory, error correction, phase change memory
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