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Publication years (Num. hits)
1988-1993 (17) 1994-1997 (23) 1998 (20) 1999 (20) 2000 (23) 2001 (20) 2002 (32) 2003 (23) 2004 (27) 2005 (34) 2006 (34) 2007 (29) 2008 (29) 2009-2010 (23) 2011-2013 (17) 2014-2016 (15) 2017-2022 (17) 2023-2024 (7)
Publication types (Num. hits)
article(100) incollection(4) inproceedings(304) phdthesis(2)
Venues (Conferences, Journals, ...)
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The graphs summarize 314 occurrences of 223 keywords

Results
Found 410 publication records. Showing 410 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
98Gerhard P. Fettweis DSPs: why don't they just go away!. Search on Bibsonomy LCTES-SCOPES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
93Peter Westermann, Ludwig Schwoerer, André Kaufmann Applying Data Mapping Techniques to Vector DSPs. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Vector DSPs, Vectorizing compilers
70Peter Westermann, Hartmut Schröder Modeling Scalable SIMD DSPs in LISA. Search on Bibsonomy SAMOS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF SIMD DSPs, Scalable Processor Models, LISA
65Peter Westermann, Ludwig Schwoerer, André Kaufmann Applying Data Mapping Techniques to Vector DSPs. Search on Bibsonomy ICSAMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
65Michael Hosemann, Gerhard P. Fettweis On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering. Search on Bibsonomy SAMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
59Björn Franke, Michael F. P. O'Boyle Compiler parallelization of C programs for multi-core DSPs with multiple address spaces. Search on Bibsonomy CODES+ISSS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF address resolution, multiple address space compilation, DSPs, data partitioning
54Michael Hosemann, Gerhard P. Fettweis On Enhancing SIMD-controlled DSPs for Performing Recursive Filtering. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
54Markus Lorenz, Peter Marwedel Phase Coupled Code Generation for DSPs Using a Genetic Algorithm. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
54Jie Guo 0007, Michael Hosemann, Gerhard P. Fettweis Employing Compilers for Determining Architectural Features of Application-Specific DSPs. Search on Bibsonomy PARELEC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
54Paul S. Graham, Brent E. Nelson Frequency-Domain Sonar Processing in FPGAs and DSPs. Search on Bibsonomy FCCM The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
44V. Parthasarathy, S. Aram valartha Bharathi, V. Rhymend Uthariaraj Performance Analysis of Embedded Media Applications in Newer ARM Architectures. Search on Bibsonomy ICPP Workshops The full citation details ... 2005 DBLP  DOI  BibTeX  RDF ARM v6, DSP Extensions, Instruction set architecture (ISA), Single Instruction Multiple Data (SIMD)
44Jeonghun Cho, Yunheung Paek, David B. Whalley Fast memory bank assignment for fixed-point digital signal processors. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF dual memory banks, nonorthogonal architecture, Compiler, DSP, dependence analysis, maximum spanning tree
44Gene Frantz Digital Signal Processor Trends. Search on Bibsonomy IEEE Micro The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
43Jintao Wang, Rui Lv, Pengdong Gao, Yongquan Lu, Chu Qiu, Wenhua Yu The Design of HDTV H.264 Encoding System Based on Multi-DSPs Architecture. Search on Bibsonomy CSSE (4) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic. Search on Bibsonomy Appl. Intell. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Memory assignment, Repair method, Genetic algorithm, Multi-Objective optimization, Embedded processors
43Dan Zhang, Zeng-zhi Li, Hai Wang, Tao Zhan A Novel Genetic Algorithm for Variable Partition of Dual Memory Bank DSPs. Search on Bibsonomy ICNC (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Siddharth Rele, Vipin Jain, Santosh Pande, J. Ramanujam Compact and efficient code generation through program restructuringon limited memory embedded DSPs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
43Rainer Leupers Instruction Scheduling for Clustered VLIW DSPs. Search on Bibsonomy IEEE PACT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
43Naji Ghazal, A. Richard Newton, Jan M. Rabaey Predicting performance potential of modern DSPs. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
43Rainer Leupers, Peter Marwedel Time-constrained code compaction for DSPs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
43Marcos Luiz Mucheroni, Célio Estevan Morón, José Hiroki Saito ArchMDSP: using DSPs for parallel image processing. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF ArchMDSP, image mapping, real-time problems, fault-tolerant problems, sub-image distribution available, Sun SparcStation, Sbus, multiple-module carrier card, TMS320C40 processors, timing measurements, 8 Mbyte, parallel architecture, parallel machines, parallel machine, speedup, operators, digital signal processors, communication overhead, parallel programming environment, image size, pipeline structure, parallel image processing
39Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers Offset assignment using simultaneous variable coalescing. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Stack offset assignment, address registers, autoincrement addressing modes, variable coalescing, DSPs, register allocation
33M. Van Der Horst, Kees van Berkel 0001, Johan Lukkien, Rudolf H. Mak Recursive Filtering on a Vector DSP with Linear Speedup. Search on Bibsonomy ASAP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
33Ross Snider, Yongming Zhu Developing a Data Driven System for Computational Neuroscience. Search on Bibsonomy International Conference on Computational Science The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
33Yuhei Kaneko, Nobuhiko Sugino, Akinori Nishihara Memory allocation method for indirect addressing with an index register. Search on Bibsonomy APCCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob Transparent data-memory organizations for digital signal processors. Search on Bibsonomy CASES The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
33Sungjoon Jung, Yunheung Paek The very portable optimizer for digital signal processors. Search on Bibsonomy CASES The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
33Adrian Johnstone, Elizabeth Scott, Tim Womack Experience Paper: Reverse Compilation of Digital Signal Processor Assembler Source to ANSI-C. Search on Bibsonomy ICSM The full citation details ... 1999 DBLP  DOI  BibTeX  RDF reverse compilation, low to high level language translation, digital signal processing
33Mazen A. R. Saghir, Paul Chow, Corinna G. Lee Exploiting Dual Data-Memory Banks in Digital Signal Processors. Search on Bibsonomy ASPLOS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
32Chun Jason Xue, Tiantian Liu 0001, Zili Shao, Jingtong Hu, Zhiping Jia, Weijia Jia 0001, Edwin Hsing-Mean Sha Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks. Search on Bibsonomy ICASSP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
32Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs. Search on Bibsonomy EUC Workshops The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Partha Biswas, Nikil D. Dutt Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction
32Bharath Iyer, Sadagopan Srinivasan, Bruce L. Jacob Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs. Search on Bibsonomy ISCA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Viera Sipková Efficient Variable Allocation to Dual Memory Banks of DSPs. Search on Bibsonomy SCOPES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
32Partha Biswas, Nikil D. Dutt Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF dependence conflict graph, heterogeneous-connectivity-based DSP, restricted data dependence graph, instruction set extensions, instruction set architecture, static single assignment
32Markus Lorenz, Lars Wehmeyer, Thorsten Dräger Energy aware compilation for DSPs with SIMD instructions. Search on Bibsonomy LCTES-SCOPES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF zero overhead hardware loop, DSP, vectorization, energy minimization, SIMD instruction
32Eugenio Suárez Cáner, José Manoel de Seixas, Rodrigo Coura Torres A Development Environment for Multilayer Neural Network Applications Mapped onto DSPs with Multiprocessing Capabilities. Search on Bibsonomy VECPAR The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Nagisa Ishiura, Tatsuo Watanabe Datapath oriented codesign method of application specific DSPs using retargetable compiler. Search on Bibsonomy APCCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32Gary William Grewal, Thomas Charles Wilson Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T). Search on Bibsonomy MICRO The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel Optimized address assignment for DSPs with SIMD memory accesses. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001 Low-power realization of FIR filters on programmable DSPs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
32Guido Araujo, Sharad Malik Code generation for fixed-point DSPs. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF scheduling, code generation, register allocation
32Jan M. Rabaey, Marlene Wan An Energy-Conscious Exploration Methodology for Reconfigurable DSPs. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
32Thomas Charles Wilson, Gary William Grewal Shake And Bake: A Method of Mapping Code to Irregular DSPs. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
32Gary William Grewal A Global Mode Instruction Minimization Technique for Embedded DSPs. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
32Rainer Leupers, Peter Marwedel Time-constrained code compaction for DSPs. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF code generation techniques, digital signal processing algorithms, encoding restrictions, exact timing behavior, hard real-time constraints, integer programming model, local code compaction, programmable DSP, rigid heuristics, time-constrained code compaction, real-time systems, timing, integer programming, instruction-level parallelism, source coding, automatic programming, digital signal processing chips, side-effects
32Edward A. Lee, E. Goei, H. Heine, W.-H. Ho, Shuvra S. Bhattacharyya, Jeffery C. Bier, E. Guntvedt GABRIEL: A Design Environment for Programmable DSPs. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
27Atsushi Ishii, Toyotaro Suzumura Elastic Stream Computing with Clouds. Search on Bibsonomy IEEE CLOUD The full citation details ... 2011 DBLP  DOI  BibTeX  RDF SPADE, Amazon EC2, Cloud, Dynamic Load Balancing, DSMS, Data Stream Processing, System S, DSPS
27Guido Araujo, Guilherme Ottoni, Marcelo Silva Cintra Global array reference allocation. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Address registers, auto-increment addressing modes, DSPs, register allocation
22André Ludwig, Marek Kowalkiewicz Supporting Service Level Agreement Creation with Past Service Behavior Data. Search on Bibsonomy BIS (Workshops) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Dynamic Service Profiling, Service behavior, Service Level Agreement, Contracting
22Hong Liu 0002, Ke Wu, Peter Meusel, Nikolaus Seitz, Gerd Hirzinger, M. H. Jin, Yiwei Liu, Shaowei Fan, T. Lan, Zhaopeng Chen Multisensory five-finger dexterous hand: The DLR/HIT Hand II. Search on Bibsonomy IROS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
22Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli ADAPTO: full-adder based reconfigurable architecture for bit level operations. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
22Hangpei Tian, Deyuan Gao, Deli Wang, Yian Zhu, Shengbing Zhang, Jing Wang Dynamically Reconfigurable Instruction Set for Software Radio Encoding/Coding. Search on Bibsonomy MUE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Instruction Set, Software Radio
22Yi-Hsuan Lee, Cheng Chen An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF non-orthogonal architecture, code generation, DSP
22Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors. Search on Bibsonomy CC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
22Muhammet Fikret Ercan Parallel Image Understanding on a Multi-DSP System. Search on Bibsonomy ICCSA (2) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
22Ozcan Ozturk 0001, Mahmut T. Kandemir, Suleyman Tosun An ILP based approach to address code generation for digital signal processors. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF code generation, DSP, integer linear programming
22Takashi Shono, Yushi Shirato, Hiroyuki Shiba, Kazuhiro Uehara, Katsuhiko Araki, Masahiro Umehira IEEE 802.11 wireless LAN implemented on software defined radio with hybrid programmable architecture. Search on Bibsonomy IEEE Trans. Wirel. Commun. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Björn Franke, Michael F. P. O'Boyle A Complete Compiler Approach to Auto-Parallelizing C Programs for Multi-DSP Systems. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF conversion from sequential to parallel forms, modeling, evaluation, compilers, measurement, performance measures, interprocessor communications, arrays, real-time and embedded systems, restructuring, Parallel processors, simulation of multiple-processor systems, reverse engineering and reengineering, signal processing systems
22Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matús, Marcus Bronzel, Gerhard P. Fettweis Synchronous Transfer Architecture (STA). Search on Bibsonomy SAMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
22Kees A. Vissers Programming models and architectures for FPGA platforms. Search on Bibsonomy CASES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
22John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. Search on Bibsonomy ISCA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
22Jae C. Oh, Madhura S. Tamhankar, Daniel Mossé Design of Very Lightweight Agents for Reactive Embedded Systems. Search on Bibsonomy ECBS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Björn Franke, Michael F. P. O'Boyle Combining Program Recovery, Auto-Parallelisation and Locality Analysis for C Programs on Multi-Processor Embedded Systems. Search on Bibsonomy IEEE PACT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Erik Eckstein, Bernhard Scholz Addressing Mode Selection. Search on Bibsonomy CGO The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch Hardware/Software Trade-Offs for Advanced 3G Channel Coding. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
22Christoph W. Keßler, Andrzej Bednarski A Dynamic Programming Approach to Optimal Integrated Code Generation. Search on Bibsonomy LCTES/OM The full citation details ... 2001 DBLP  DOI  BibTeX  RDF integrated code generation, time profile, dynamic programming, register allocation, instruction scheduling, instruction selection
22Ashok Sudarsanam, Sharad Malik Simultaneous reference allocation in code generation for dual data memory bank ASIPs. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF memory bank assignment, code generation, register allocation, code optimization, graph labelling
22David W. Currie, Alan J. Hu, Sreeranga P. Rajan Automatic formal verification of DSP software. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
22Anupam Basu, Rainer Leupers, Peter Marwedel Register-Constrained Address Computation in DSP Programs. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF DSP compiler, address computation, embedded processors
22Shuvra S. Bhattacharyya, Edward A. Lee Scheduling synchronous dataflow graphs for efficient looping. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
21Yang Wang, Qinglin Wang, Xiangdong Pei, Songzhu Mei, Rongchun Li, Jie Liu 0002 High performance dilated convolutions on multi-core DSPs. Search on Bibsonomy CCF Trans. High Perform. Comput. The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
21Wei Tang 0010, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. Search on Bibsonomy VLSI Technology and Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Deshun Bi, Xiaowen Tian, Shengguo Li, Dezun Dong Efficiently Running SpMV on Multi-Core DSPs for Block Sparse Matrix. Search on Bibsonomy ICPADS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Yufei Guo, Xinjie An, Shijie Li, Yingbo Cui, Peng Zhang, Biao Long, Shanshan Li MTMap: A Long-Read Alignment Tool based on Multi-Core DSPs. Search on Bibsonomy BIBM The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Yang Wang, Qinglin Wang, Xiangdong Pei, Songzhu Mei, Jie Liu 0002 Optimizing Pointwise Convolutions on Multi-core DSPs. Search on Bibsonomy ICA3PP (7) The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Deshun Bi, Shengguo Li, Yichen Zhang, Xiaojian Yang, Dezun Dong Efficiently Running SpMV on Multi-core DSPs for Banded Matrix. Search on Bibsonomy ICA3PP (5) The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Xiaolei Zhao, Zhaoyun Chen, Yang Shi, Mei Wen, Chunyun Zhang Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs. Search on Bibsonomy DAC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Shangfei Yin, Qinglin Wang, Ruochen Hao, Tianyang Zhou, Songzhu Mei, Jie Liu 0002 Optimizing Irregular-Shaped Matrix-Matrix Multiplication on Multi-Core DSPs. Search on Bibsonomy CoRR The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Shun Orita, Akiko Narita, Kenji Ichijo Design of Multicore Dataflow DSPs with Different Loop Iteration Mechanisms. Search on Bibsonomy ICCE-TW The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Wei Niu 0002, Jiexiong Guan, Xipeng Shen, Yanzhi Wang, Gagan Agrawal, Bin Ren GCD2: A Globally Optimizing Compiler for Mapping DNNs to Mobile DSPs. Search on Bibsonomy MICRO The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Bowen Zhu, Yanyi Wang, Weiping Li, Feng Wang, Jiaxuan Liu, Jianjun Yu 40-Gbit/s W-band Signal Delivery over 4600-m Wireless Distance Employing Advanced DSPs. Search on Bibsonomy ICC Workshops The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Elliott Wen, Jiaxing Shen DSPBooster: Offloading Unmodified Mobile Applications to DSPs for Power-performance Optimal Execution. Search on Bibsonomy COMPSAC The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Rafael Romón Sagredo, Erik Börjeson, Ali Mirani, Magnus Karlsson 0001, Per Larsson-Edefors Waveform Memory for Real-Time FPGA Test of Fiber-Optic Receiver DSPs. Search on Bibsonomy NorCAS The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Ankita Shah, Uma Shanker Tiwary Dominance Submissiveness Predisposition Scale (DSPS): Development and Validation. Search on Bibsonomy ICHI The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Shangfei Yin, Qinglin Wang, Ruochen Hao, Tianyang Zhou, Songzhu Mei, Jie Liu 0002 Optimizing Irregular-Shaped Matrix-Matrix Multiplication on Multi-Core DSPs. Search on Bibsonomy CLUSTER The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21David Uzan, Roger Kahn, Shlomo Weiss Perceptron based filtering of futile prefetches in embedded VLIW DSPs. Search on Bibsonomy J. Syst. Archit. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
21Elif Bilge Kavun, Nele Mentens, Jo Vliegen, Tolga Yalçin Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs. Search on Bibsonomy IACR Cryptol. ePrint Arch. The full citation details ... 2019 DBLP  BibTeX  RDF
21Elif Bilge Kavun, Nele Mentens, Jo Vliegen, Tolga Yalçin Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs. Search on Bibsonomy ReConFig The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Rui Qin 0002, Yong Yuan, Fei-Yue Wang 0001 Exploring Optimal Revenue Models For DSPs In Real Time Bidding Advertising. Search on Bibsonomy SOLI The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Amir HajiRassouliha, Andrew J. Taberner, Martyn P. Nash, Poul M. F. Nielsen Suitability of recent hardware accelerators (DSPs, FPGAs, and GPUs) for computer vision and image processing algorithms. Search on Bibsonomy Signal Process. Image Commun. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Yuan Li, Wei Li 0032, Lu Li 0005 Hyperspectral Anomaly Dectection on Multicore DSPs. Search on Bibsonomy CISP-BMEI The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs. Search on Bibsonomy J. Hardw. Syst. Secur. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
21Sander Vocke, Henk Corporaal, Roel Jordans, Rosilde Corvino, Rick J. M. Nas Extending Halide to Improve Software Development for Imaging DSPs. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
21Rui Chang, Jun Wu 0006, Haoqi Ren A compilation method for zero overhead loop in DSPs with VLIW. Search on Bibsonomy WCSP The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
21Shiming Sun, Hongxu Jiang, Bo Li 0006 An efficient Markov chain-based data prefetching for motion estimation of HEVC on multi-core DSPs. Search on Bibsonomy Multim. Tools Appl. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
21Sheng Liu 0001, Haiyan Chen, Jianghua Wan, Yaohua Wang Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs. Search on Bibsonomy ISVLSI The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
21Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs. Search on Bibsonomy SPACE The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
21Xiangyang Liu, Hua Bao Efficient Implementation of 2-D FCT with Reduced Memory Access for Programmable DSPs. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
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