Search results for "Delay"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
78	Ananta K. Majhi, Vishwani D. Agrawal	Tutorial: Delay Fault Models and Coverage.	VLSI Design	1998	DBLP DOI BibTeX RDF	delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test
60	W. Melody Moh, Yu-Jen Chien, Irene Zhang, Teng-Sheng Moh	Delay performance evaluation of high speed protocols for multimedia communications.	ICCCN	1995	DBLP DOI BibTeX RDF	delay performance evaluation, high speed protocols, delay fairness, worst-case delay performance, distributed queue dual bus, CRMA, cyclic reservation multiple access, DQMA, distributed queue multiple access, FDQ, fair distributed queue, heavy network load, reservation-based protocols, throughput, multimedia communication, multimedia communication, multimedia traffic, quality of service requirements, DQDB, access delay, message delay, heterogeneous traffic
55	Subhrajit Bhattacharya, Sujit Dey, Franc Brglez	Fast true delay estimation during high level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
52	Mukund Sivaraman, Andrzej J. Strojwas	Diagnosis of parametric path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing
49	Ioannis Papapanagiotou, John S. Vardakas, Georgios S. Paschos, Michael D. Logothetis, Stavros A. Kotsopoulos	Performance evaluation of IEEE 802.11e based on ON-OFF traffic model.	MobiMedia	2007	DBLP DOI BibTeX RDF	MAC delay, QoS, IEEE 802.11e, end-to-end delay, queuing delay
49	Eun Sei Park, M. Ray Mercer, Thomas W. Williams	The Total Delay Fault Model and Statistical Delay Fault Coverage.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	delay fault model, delay fault coverage, statistical delay fault coverage, defect level model, logic testing, delay testing, delay faults
46	Youxin Gao, D. F. Wong 0001	Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model.	DATE	2000	DBLP DOI BibTeX RDF
43	Branka Medved Rogina, Bozidar Vojnovic	Metastability evaluation method by propagation delay distribution measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement
43	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns
43	Andrew B. Kahng, Kei Masuko, Sudhakar Muddu	Analytical delay models for VLSI interconnects under ramp input.	ICCAD	1996	DBLP DOI BibTeX RDF	SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections
42	Huawei Li 0001, Zhongcheng Li, Yinghua Min	Reduction of Number of Paths to be Tested in Delay Testing.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	linearly independent, analytical delay model, delay testing, path sensitization
42	Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu	Generation of tenacious tests for small gate delay faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage
42	Rodica Branzei, Giulio Ferrari, Vito Fragnelli, Stef Tijs	Two Approaches to the Problem of Sharing Delay Costs in Joint Projects.	Ann. Oper. Res.	2002	DBLP DOI BibTeX RDF	activity graph, delay cost, taxation, serial cost sharing, bankruptcy
41	William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Delay fault coverage, test set size, and performance trade-offs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
40	Mukund Sivaraman, Andrzej J. Strojwas	Timing analysis based on primitive path delay fault identification.	ICCAD	1997	DBLP DOI BibTeX RDF	primitive path delay faults, correlated delay, floating mode, timing analysis, timing verification, false path, path delay fault testing
40	Sudhakar M. Reddy, Peter Maxwell	Fundamentals of Small-Delay Defect Testing.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
40	Sandeep Kumar Goel, Krishnendu Chakrabarty	Circuit Topology-Based Test Pattern Generation for Small-Delay Defects.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
40	Sandeep Kumar Goel, Narendra Devta-Prasanna	Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
40	Narendra Devta-Prasanna, Sandeep Kumar Goel	Small-Delay Defect Coverage Metrics.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
40	Nisar Ahmed, Mohammad Tehranipoor	Faster-than-at-Speed Test for Screening Small-Delay Defects.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
40	Abdelmajid Khelil, Faisal Karim Shaikh, Azad Ali, Neeraj Suri, Christian Reinl	Delay Tolerant Monitoring of Mobility-Assisted WSN.	Delay Tolerant Networks	2011	DBLP BibTeX RDF
40	Angela Sara Cacciapuoti, Marcello Caleffi, Luigi Paura	Mobile Peer-to-Peer Systems over Delay Tolerant Networks.	Delay Tolerant Networks	2011	DBLP BibTeX RDF
40	Corrado Moiso, Antonio Manzalini, Francesco De Pellegrini, Iacopo Carreras, Daniele Miorandi, Athanasios V. Vasilakos	R-P2P: a Data-Centric Middleware for Delay Tolerant Applications.	Delay Tolerant Networks	2011	DBLP BibTeX RDF
40	Maode Ma, Chao Lu, Hui Li 0006	Delay Tolerant Networking.	Delay Tolerant Networks	2011	DBLP BibTeX RDF
40	Ruhai Wang, Xuan Wu, Tiaotiao Wang, Tarik Taleb	Delay Tolerant Networking (DTN) Protocols for Space Communications.	Delay Tolerant Networks	2011	DBLP BibTeX RDF
40	Seung Keun Yoon, Zygmunt J. Raas	Energy-Aware Routing Protocol for Delay Tolerant Networks.	Delay Tolerant Networks	2011	DBLP BibTeX RDF
40	Kevin R. Fall, Cecilia Mascolo, Jörg Ott, Lars C. Wolf	09071 Executive Summary - Delay and Disruption-Tolerant Networking (DTN) II.	Delay and Disruption-Tolerant Networking (DTN) II	2009	DBLP BibTeX RDF
40	Kevin R. Fall, Cecilia Mascolo, Jörg Ott, Lars C. Wolf	09071 Abstracts Collection - Delay and Disruption-Tolerant Networking (DTN) II.	Delay and Disruption-Tolerant Networking (DTN) II	2009	DBLP BibTeX RDF
40	Baris Bozkurt, Thierry Dutoit, Laurent Couvreur	Spectral Analysis of Speech Signals Using Chirp Group Delay.	WNSP	2005	DBLP DOI BibTeX RDF	Phase processing, chirp group delay, group delay, zzt, ASR feature extraction
40	Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng	On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set.	VTS	2000	DBLP DOI BibTeX RDF	Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing
40	Shibin Song, Joseph Kee-Yin Ng, Bihai Tang	Statistical Delay Analysis with Self-Similar Input Traffic in ATM Networks.	RTCSA	1999	DBLP DOI BibTeX RDF	Real-Time ATM Networks, Statistical Delay Analysis, Efficient Delay Computation, Performance Evaluation, Self-similar Traffic
40	Mukund Sivaraman, Andrzej J. Strojwas	A diagnosability metric for parametric path delay faults.	VTS	1996	DBLP DOI BibTeX RDF	diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set
40	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	On test coverage of path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	two-pass test generation method, falling transition, line delay test, longest sensitizable path, decreasing length, redundant stuck-at fault, computational complexity, fault diagnosis, logic testing, delays, redundancy, combinational circuits, fault simulation, circuit analysis computing, test coverage, path delay faults, benchmark circuits, coverage metric, combinational logic circuits, longest paths
39	Abbas El Gamal, James P. Mammen, Balaji Prabhakar, Devavrat Shah	Optimal throughput-delay scaling in wireless networks: part I: the fluid model.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF	throughput scaling, throughput-delay tradeoff, wireless networks, queueing theory, random walks, scaling laws
39	Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu	Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model.	ICCD	2002	DBLP DOI BibTeX RDF
39	Masoud Sharif, Babak Hassibi	A delay analysis for opportunistic transmission in fading broadcast channels.	INFOCOM	2005	DBLP DOI BibTeX RDF
38	Matthew K. H. Leung, John C. S. Lui, David K. Y. Yau	Characterization and Performance Evaluation for Proportional Delay Differentiated Services.	ICNP	2000	DBLP DOI BibTeX RDF	proportional delay differentiated services, Internet differentiated services, traffic classes, tariff rate, time-dependent priority scheduling, proportional delay model, delay ratios, scheduling parameters, efficient control algorithm, relative waiting time, performance evaluation, performance evaluation, Internet, delays, telecommunication traffic, waiting times, telecommunication services, ISP, feasible regions, average waiting time, service classes
38	Seiichiro Tani, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro	Efficient Path Selection for Delay Testing Based on Path Clustering.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	clustering, delay testing, delay fault, path delay
38	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	function-robust tests, functional delay fault model, delay faults, path delay faults, robust tests
38	Matthew Andrews, Antonio Fernández 0001, Mor Harchol-Balter, Frank Thomson Leighton, Lisa Zhang	General Dynamic Routing with Per-Packet Delay Guarantees of O(distance + 1 / session rate).	FOCS	1997	DBLP DOI BibTeX RDF	per-packet delay, queue buildup, scheduling, packet-switching, communication networks, dynamic routing, telecommunication networks, performance guarantees, delay bounds, bursty traffic, packet delay, arbitrary topology
38	Aiguo Lu, Erik L. Dagless, Jonathan M. Saul	DART: delay and routability driven technology mapping for LUT based FPGAs.	ICCD	1995	DBLP DOI BibTeX RDF	DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets
38	Wuudiann Ke, Premachandran R. Menon	Multifault testability of delay-testable circuits.	VTS	1995	DBLP DOI BibTeX RDF	delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits
38	Mukund Sivaraman, Andrzej J. Strojwas	Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults.	ICCAD	1996	DBLP DOI BibTeX RDF	fabrication process, coverage, delay testing, delay fault, path sensitization
38	Syed Sohel Hussain, Yih-Chyun Jenq	Analysis and Optimization of a Banyan-Based ATM Switch by Simulations.	LCN	1996	DBLP DOI BibTeX RDF	Banyan based ATM switch, switch optimization, switch analysis, delay variance, performanc analysis, uniform traffic, three-state model, nonblocking first stage, packet blocking, enhanced priority scheme, single buffer Banyan network, double buffer switching element, delay sensitive voice packet, asynchronous transfer mode, asynchronous transfer mode, delay, throughput, bandwidth, simulation results, voice traffic, data traffic
37	Yu-Sheng Huang, Chih-wen Hsueh	Minimizing the maximum end-to-end delay on tree structure using the distributed pinwheel model.	RTCSA	2000	DBLP DOI BibTeX RDF	maximum end-to-end delay minimisation, distributed pinwheel model, end-to-end timing requirements, tight maximum delay bound, quality of service, Internet, computational complexity, timing, computer networks, heuristic algorithm, processor scheduling, timing constraints, simulation result, distributed real-time systems, tree structure, heuristic programming, NP-hard problems, linear-time algorithm, pipeline structure
37	S. Cremoux, Christophe Fagot, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	A new test pattern generation method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
37	Yinghua Min, Zhuxing Zhao, Zhongcheng Li	An Analytical Delay Model Based on Boolean Process.	VLSI Design	1996	DBLP DOI BibTeX RDF	waveform polynomial, transition delay, floating delay, sensitization, Boolean process
37	Colin J. Ihrig, Gerold Joseph Dhanabalan, Alex K. Jones	A low-power CMOS thyristor based delay element with programmability extensions.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	delay element, thyristor, low power
36	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001	A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
36	Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal	Test Generation for Path Delay Faults Using Binary Decision Diagrams.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Boolean algebraic test generation, redundant delay faults, robust delay tests, scan testing of delay faults, binary decision diagrams, delay faults
36	Daniel C. McCrackin	Eliminating Interlocks in Deeply Pipelined Processors by Delay Enforced Multistreaming.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	deeply pipelined processors, delay enforced multistreaming, data dependency problem, jump problem, interdispatch delay, stream dispatching algorithms, modified fixed delay, encoded delay with fixed minimum, pipeline processing, processor architecture, interleaving, interlocks
35	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Safe Delay Optimization for Physical Synthesis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	safe delay optimization, SafeResynth, safe resynthesis technique, immediately-measurable delay improvement, circuit timing, route length, physical synthesis, electronic design automation, route congestion, circuit delay
35	Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu	An Application-Independent Delay Testing Methodology for Island-Style FPGA.	DFT	2004	DBLP DOI BibTeX RDF	segment delay fault, FPGA, delay testing, path delay fault
35	Maria K. Michael, Spyros Tragoudas	ATPG tools for delay faults at the functional level.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	functional-level testing, path delay fault simulation (coverage), testing digital circuits, Automatic test pattern generation, Binary Decision Diagrams, delay testing, Boolean Satisfiability, path delay fault testing
35	Wen Ching Wu, Chung-Len Lee 0001, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir	Oscillation Ring Delay Test for High Performance Microprocessors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault
35	Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee	Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis.	VTS	2000	DBLP DOI BibTeX RDF	delay defects, delay fault modeling, delay testing, critical paths, statistical timing analysis
35	Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das	Delay Fault Coverage Enhancement Using Variable Observation Times.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	statistical delay fault coverage, delay test observation times, delay fault testing
35	Joseph Kee-Yin Ng, Shibin Song, Wei Zhao 0001	Integrated delay analysis of regulated ATM switch.	RTSS	1997	DBLP DOI BibTeX RDF	integrated delay analysis, regulated ATM switch, worst case delay, hard real-time connection, real-time connection traffic, arrival functions, priority driven scheduling, FIFO scheduling, admission probability, cell delay estimation, performance, asynchronous transfer mode, deadline, simulation experiments, service functions, piecewise linear functions
35	Chung-Ping Chen, Hai Zhou 0001, D. F. Wong 0001	Optimal non-uniform wire-sizing under the Elmore delay model.	ICCAD	1996	DBLP DOI BibTeX RDF	Elmore delay model, IBM RS/6000 workstation, NWSA-db, NWSA-md, NWSA-wd algorithm, general routing trees, maximum sink delay, minimization objectives, optimal nonuniform wire sizing, routing-tree problem, sink-delay bounds, total area, total weighted sink-delays, wire-sizing formula, circuit analysis computing, Lagrangian relaxation
35	Jacob Savir	Generator choices for delay test.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test
35	Hagit Attiya, David Hay	The inherent queuing delay of parallel packet switches.	SPAA	2004	DBLP DOI BibTeX RDF	leaky-bucket traffic, load balancing, packet switching, clos networks, queuing delay, delay jitter, inverse multiplexing
35	Moonsoo Kang, Chansu Yu	Job-Based Queue Delay Modeling in a Space-Shared Hypercube.	ICPP Workshops	1999	DBLP DOI BibTeX RDF	topological delay, processor allocation, space sharing, queue delay, Hypercube computer
35	Angela Krstic, Kwang-Ting Cheng	Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	resynthesis for testability, timing defects, delay testing, path delay faults, VLSI testing
35	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga	A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	marginal delay, test generation, combinational circuit, gate delay faults
35	Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram	Timing-based delay test for screening small delay defects.	DAC	2006	DBLP DOI BibTeX RDF	test generation, delay testing
35	Taieb Znati, Rami G. Melhem	Node delay assignment strategies to support end-to-end delay requirements in heterogeneous networks.	IEEE/ACM Trans. Netw.	2004	DBLP DOI BibTeX RDF	quality of service (QoS), packet scheduling, end-to-end delay
35	Duncan M. Hank Walker	K Longest Paths.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
35	Mahmut Yilmaz	Output Deviations-Based SDD Testing.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
35	Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor	Circuit Path Grading Considering Layout, Process Variations, and Cross Talk.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
35	Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin	Timing-Aware ATPG.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
35	Haojin Zhu, Xiaodong Lin 0001, Rongxing Lu, Yanfei Fan, Xuemin Shen	A Routing-Compatible Credit-Based Incentive Scheme for DTNs.	Delay Tolerant Networks	2011	DBLP BibTeX RDF
35	Thrasyvoulos Spyropoulos, Rao Naveed Bin Rais, Thierry Turletti, Katia Obraczka, Athanasios V. Vasilakos	DTN Routing: Taxonomy and Design.	Delay Tolerant Networks	2011	DBLP BibTeX RDF
35	Carlo Caini, Rosario Firrincieli	DTN and Satellite Communications.	Delay Tolerant Networks	2011	DBLP BibTeX RDF
35	Shabbir Ahmed 0002, Salil S. Kanhere	Message Dissemination in Vehicular Networks.	Delay Tolerant Networks	2011	DBLP BibTeX RDF
35	Kevin R. Fall, Cecilia Mascolo, Jörg Ott, Lars C. Wolf (eds.)	Delay and Disruption-Tolerant Networking (DTN) II, 08.02. - 11.02.2009	Delay and Disruption-Tolerant Networking (DTN) II	2009	DBLP BibTeX RDF
35	Gunnar Karlsson, Ólafur Ragnar Helgason, Vladimir Vukadinovic	On the Performance of Pedestrian Content Distribution.	Delay and Disruption-Tolerant Networking (DTN) II	2009	DBLP BibTeX RDF
35	Eiko Yoneki, Pan Hui 0001, Jon Crowcroft	Wireless Epidemic Spread in Dynamic Human Networks.	Delay and Disruption-Tolerant Networking (DTN) II	2009	DBLP BibTeX RDF
34	Josef Schmid, Timo Schüring, Christoph Smalla	Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow.	ISQED	2001	DBLP DOI BibTeX RDF
34	Petar Djukic, Shahrokh Valaee	Delay aware link scheduling for multi-hop TDMA wireless networks.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	TDMA scheduling algorithms, scheduling delay, stop-and-go queueing
34	I-De Huang, Yi-Shing Chang, Sandeep K. Gupta 0001, Sreejit Chakravarty	An Industrial Case Study of Sticky Path-Delay Faults.	VTS	2008	DBLP DOI BibTeX RDF	sticky paths, timing false paths, path reprioritization, delay testing, test quality
34	Hechmi Khlifi, Jean-Charles Grégoire	Estimation and Removal of Clock Skew From Delay Measures.	LCN	2004	DBLP DOI BibTeX RDF	clock skew, delay measurement
34	Jun (Jim) Xu, Richard J. Lipton	On fundamental tradeoffs between delay bounds and computational complexity in packet scheduling algorithms.	SIGCOMM	2002	DBLP DOI BibTeX RDF	quality of service, computational complexity, decision tree, packet scheduling, delay bound
34	Tatsuhiro Tsuchiya, Masatoshi Yamaguchi, Tohru Kikuno	Minimizing the Maximum Delay for Reaching Consensus in Quorum-Based Mutual Exclusion Schemes.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	distributed systems, mutual exclusion, communication delay, Quorums, coteries
34	Kartik Gopalan, Tzi-cker Chiueh, Yow-Jian Lin	Probabilistic delay guarantees using delay distribution measurement.	ACM Multimedia	2004	DBLP DOI BibTeX RDF	measurement-based, admission control, statistical multiplexing
34	Masoud Sharif, Babak Hassibi	Delay Considerations for Opportunistic Scheduling in Broadcast Fading Channels.	IEEE Trans. Wirel. Commun.	2007	DBLP DOI BibTeX RDF
34	Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi 0001, Majid Sarrafzadeh	Optimal integer delay-budget assignment on directed acyclic graphs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
34	Yoon G. Kim, Afshin Shiravi, Paul S. Min	Prediction-Based Routing through Least Cost Delay Constraint.	IPDPS	2004	DBLP DOI BibTeX RDF
34	Eun Sei Park, M. Ray Mercer	An efficient delay test generation system for combinational logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
34	Eun Sei Park, M. Ray Mercer	An Efficient Delay Test Generation System for Combinational Logic Circuits.	DAC	1990	DBLP DOI BibTeX RDF
33	Youxin Gao, Martin D. F. Wong	Wire-sizing optimization with inductance consideration using transmission-line model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
33	Libin Dong, Rami G. Melhem, Daniel Mossé	Effect of scheduling jitter on end-to-end delay in TDMA protocols.	RTCSA	2000	DBLP DOI BibTeX RDF	scheduling jitter, TDMA protocols, time slot allocation algorithm, transmission rate, ETE delay bound, simulations, scheduling, distributed system, real-time systems, delays, time division multiple access, time division multiple access, jitter, real time communication, end-to-end delay, packet delay, destination node
33	Ping Zhou, Charles Thompson	Available Bit Rate (ABR) Source Control and Delay Estimation.	LCN	2000	DBLP DOI BibTeX RDF	nonlinear estimation, ABR source control, transmission rate regulation, ABR traffic source, linear quadratic rate regulation, round-trip propagation delay estimation, nonlinear least mean square, NLMS algorithm, ATM standard, asynchronous transfer mode, ATM network, simulation results, telecommunication traffic, least squares approximations, telecommunication control, delay estimation, delay estimation, available bit rate
33	Priyadarsan Patra, Donald S. Fussell	Power-efficient delay-insensitive codes for data transmission.	HICSS (1)	1995	DBLP DOI BibTeX RDF	telecommunication switching, power-efficient delay-insensitive codes, dynamic delay-insensitive codes, switching energy optimization, data pins, protocols, delays, power consumption, codes, asynchronous systems, data communication, data communication, data transmission, energy reduction, delay-insensitive circuits
33	Erik Burman, Guillaume Delay, Alexandre Ern	The Unique Continuation Problem for the Heat Equation Discretized with a High-Order Space-Time Nonconforming Method.	SIAM J. Numer. Anal.	2023	DBLP DOI BibTeX RDF
33	Pranoy Roy, Reza Ilka, Jiangbiao He, Yuan Liao, Aaron M. Cramer, Justin Mccann, Samuel Delay, Steven Coley, Melissa Geraghty, Sachindra Dahal	Impact of Electric Vehicle Charging on Power Distribution Systems: A Case Study of the Grid in Western Kentucky.	IEEE Access	2023	DBLP DOI BibTeX RDF
33	Sahan Wijethunga, Shehan Kaushalya Senavirathna, Kavishka Dissanayake, Janith Bandara Senanayaka, Eranda Somathilake, Upekha Hansanie Delay, Roshan Indika Godaliyadda, Mervyn Parakrama B. Ekanayake, Janaka V. Wijayakulasooriya	IMU-based Modularized Wearable Device for Human Motion Classification.	CoRR	2023	DBLP DOI BibTeX RDF
33	Oleksandr Zaitsev, François Vendel, Etienne Delay	Cormas: The Software for Participatory Modelling and its Application for Managing Natural Resources in Senegal.	CoRR	2023	DBLP DOI BibTeX RDF
33	Oleksandr Zaitsev, François Vendel, Etienne Delay	Cormas: The Software for Participatory Modelling and Its Application for Managing Natural Resources in Senegal.	Euro-Par Workshops	2023	DBLP DOI BibTeX RDF
33	Eranda Somathilake, Upekha Hansanie Delay, Janith Bandara Senanayaka, Samitha Gunarathne, Roshan Indika Godaliyadda, Mervyn Parakrama B. Ekanayake, Janaka V. Wijayakulasooriya, Chathura Rathnayake	Assessment of Fetal and Maternal Well-Being During Pregnancy Using Passive Wearable Inertial Sensor.	IEEE Trans. Instrum. Meas.	2022	DBLP DOI BibTeX RDF
33	Angelos K. Sikalidis, Aleksandra S. Kristo, Scott K. Reaves, Franz J. Kurfess, Ann M. DeLay, Kathryn Vasilaky, Lorraine Donegan	Capacity Strengthening Undertaking - Farm Organized Response of Workers against Risk for Diabetes: (C.S.U. - F.O.R.W.A.R.D. with Cal Poly) - A Concept Approach to Tackling Diabetes in Vulnerable and Underserved Farmworkers in California.	Sensors	2022	DBLP DOI BibTeX RDF