Search results for "Delay-Insensitive"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
115	Priyadarsan Patra, Donald S. Fussell	Power-efficient delay-insensitive codes for data transmission.	HICSS (1)	1995	DBLP DOI BibTeX RDF	telecommunication switching, power-efficient delay-insensitive codes, dynamic delay-insensitive codes, switching energy optimization, data pins, protocols, delays, power consumption, codes, asynchronous systems, data communication, data communication, data transmission, energy reduction, delay-insensitive circuits
105	Jia Di, Parag K. Lala	Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Reed-Muller expression, nanoscale circuit, layout, stuck-at fault, cellular arrays, delay-insensitive circuit
99	H. Bekker, E. J. Dijkstra	Delay-Insensitive Synchronization on a Message-Passing Architecture with an Open Collector Bus.	PDP	1996	DBLP DOI BibTeX RDF	delay-insensitive synchronization, open collector bus, high latency, constraint algorithm, SHAKE, Constraint Molecular Dynamics simulation, ring architecture, delay insensitive algorithm, performance evaluation, performance, parallel algorithms, parallel algorithms, parallel architectures, message passing, multiprocessor interconnection networks, multiprocessor interconnection networks, synchronisation, digital simulation, physics computing, system buses, communication time, message passing architecture
74	Sandeep Pagey	Fast functional testing of delay-insensitive circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	four-phase handshake signalling, Martin's method, distributed circuit, OR/C blocks, generation of test sequences, program flow graph, logic testing, delays, design for testability, logic CAD, asynchronous circuits, functional testing, testing time, self-timed circuits, delay-insensitive circuits, OR gates
70	Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo	Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	Delay-insensitive codes, self-timed design, delay-insensitive communication, block codes
59	Pedro A. Molina, Peter Y. K. Cheung	A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems.	ASYNC	1997	DBLP DOI BibTeX RDF	Tri-state Buffers, Asynchronous, Composability, Bus, Data Path, Delay-Insensitive, Handshake Circuits
57	Hiroshi Saito, Alex Kondratyev, Takashi Nanya	Design of Asynchronous Controllers with Delay Insensitive Interface.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	delay insensitive interface, gate-level transformation, behavioral transformation, asynchronous circuits, hazards
57	Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya	Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic.	ASYNC	1998	DBLP DOI BibTeX RDF	pulse-driven logic, Josephson junction device, RSFQ device, pipeline, asynchronous circuit, delay-insensitive circuit
54	Jia Lee, Ferdinand Peper, Susumu Adachi, Kenichi Morita	Universal Delay-Insensitive Circuits with Bidirectional and Buffering Lines.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	bidirectional buffering lines, module, Asynchronous systems, universality, delay-insensitive circuits
54	Willem C. Mallon, Jan Tijmen Udding	Using Metrics for Proof Rules for Recursively Defined Delay-insensitive Specifications.	ASYNC	1997	DBLP DOI BibTeX RDF	delay-insensitive specifications, recursive definition, linear proofs, intuitive induction rule, algebraic specification, algebraic specifications, theorem provers, correctness proofs, proof rules, proof rule
48	Gregg N. Hoyer, Gin Yee, Carl Sechen	Locally clocked pipelines and dynamic logic.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
48	Yoshio Kameda	Pulse-Driven Delay-Insensitive Circuits using Single-Flux-Quantum Devices.	ICCD	1996	DBLP DOI BibTeX RDF
45	David K. Probst, Hon Fung Li	Partial-Order Model Checking: A Guide for the Perplexed.	CAV	1991	DBLP DOI BibTeX RDF	delay-insensitive system, partial-order representation, recurrence structure, model checking, state explosion, state encoding
45	Daniel H. Linder, James C. Harden	Phased Logic Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Asynchronous circuitry, delay-insensitive circuitry, dual-rail encoding, LEDR, phased logic, synchronous circuitry, data flow, marked graphs
43	Jia Di, Dilip P. Vasudevan	Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays.	DELTA	2006	DBLP DOI BibTeX RDF
43	Christopher LaFrieda, Rajit Manohar	Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits.	DSN	2004	DBLP DOI BibTeX RDF
42	Lei Wang 0014, Carl McCrosky	Performance Comparison of Control Schemes for ABR Service in ATM LANs.	MASCOTS	1997	DBLP DOI BibTeX RDF	ABR service, ATM Forum, available bit rate service, constrained cell loss, network resource utilization, CBR/VBR services, burst level traffic control, rate based feedback control, loss sensitive applications, delay insensitive applications, burst transfer delay, simulation, asynchronous transfer mode, bandwidth, performance comparison, ATM LAN, delay variation
41	Masashi Imai, Metehan Özcan, Takashi Nanya	Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model.	ASYNC	2004	DBLP DOI BibTeX RDF
41	A. Neslin Ismailoglu, Murat Askar	Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders.	ISCAS	2007	DBLP DOI BibTeX RDF
41	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling.	ISVLSI	2006	DBLP DOI BibTeX RDF
41	Jia Di, Parag K. Lala, Dilip P. Vasudevan	On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.	DFT	2005	DBLP DOI BibTeX RDF
38	Igor Lemberski, Mark B. Josephs	Optimal Two-Level Delay - Insensitive Implementation of Logic Functions.	PATMOS	2002	DBLP DOI BibTeX RDF
38	Mark B. Josephs, Dennis P. Furey	Delay-Insensitive Interface Specification and Synthesis.	DATE	2000	DBLP DOI BibTeX RDF
38	Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni	On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic.	ASYNC	1997	DBLP DOI BibTeX RDF
38	Priyadarsan Patra, Donald S. Fussell	Efficient Delay-Insensitive RSFQ Circuits.	ICCD	1996	DBLP DOI BibTeX RDF
38	David M. Goldschlag	Mechanically Verifying Safety and Liveness Properties of Delay Insensitive Circuits.	CAV	1991	DBLP DOI BibTeX RDF
38	Anders Gammelgaard	Implementation Conditions for Delay Insensitive Circuits.	PARLE (1)	1989	DBLP DOI BibTeX RDF
36	Dario Pompili, Tommaso Melodia, Ian F. Akyildiz	Routing algorithms for delay-insensitive and delay-sensitive applications in underwater sensor networks.	MobiCom	2006	DBLP DOI BibTeX RDF	routing algorithms, underwater sensor networks
35	Raffaele Mascella, Luca G. Tallini	Efficient m-Ary Balanced Codes which Are Invariant under Symbol Permutation.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Coding and information theory, m{hbox{-}}rm ary communication, line codes, DC-free communication, delay-insensitive communication, error control codes, digital communication, constant weight codes, balanced codes
35	Yannick Monnet, Marc Renaudin, Régis Leveugle	Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	quasi-delay insensitive, hardening techniques, Asynchronous circuits, data encryption standard, fault attacks
35	Yannick Monnet, Marc Renaudin, Régis Leveugle	Asynchronous circuits transient faults sensitivity evaluation.	DAC	2005	DBLP DOI BibTeX RDF	quasi delay insensitive, simulation, fault model, asynchronous circuits, transient fault
35	Hemangee K. Kapoor, Mark B. Josephs	Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis.	DAC	2004	DBLP DOI BibTeX RDF	asynchronous logic synthesis, delay-insensitive decomposition
35	Marc Renaudin, Pascal Vivet, Frédéric Robin	ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor.	ASYNC	1998	DBLP DOI BibTeX RDF	asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design
35	R. S. Hogg, W. I. Hughes, David W. Lloyd	A Novel Asynchronous ALU for Massively Parallel Architectures.	PDP	1996	DBLP DOI BibTeX RDF	novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit
35	Priyadarsan Patra, Donald S. Fussell	Fully asynchronous, robust, high-throughput arithmetic structures.	VLSI Design	1995	DBLP DOI BibTeX RDF	fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers
35	David K. Probst, Hon Fung Li	Using Partial-Order Semantics to Avoid the State Explosion Problem in Asynchronous Systems.	CAV	1990	DBLP DOI BibTeX RDF	delay-insensitive system, branching point, recurrence structure, behavior machine, behavior state, model checking, state explosion, partial-order semantics
31	Masashi Imai, Takashi Nanya	A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations.	ASYNC	2006	DBLP DOI BibTeX RDF
31	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Area efficient delay-insensitive and differential current sensing on-chip interconnect.	SoCC	2008	DBLP DOI BibTeX RDF
31	Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Furey	Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments.	ACSD	2004	DBLP DOI BibTeX RDF
29	Amitava Mitra, William F. McLaughlin, Steven M. Nowick	Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication.	ASYNC	2007	DBLP DOI BibTeX RDF
29	Yannick Monnet, Marc Renaudin, Régis Leveugle	Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs.	IOLTS	2007	DBLP DOI BibTeX RDF
29	Giuseppe Campobello, Marco Castano, Carmine Ciofi, Daniele Mangano	GALS networks on chip: a new solution for asynchronous delay-insensitive links.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
29	G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin	Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits.	CHES	2006	DBLP DOI BibTeX RDF	QDI Asynchronous circuits, Path Swapping (PS), Power analysis
29	G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard	Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
29	Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin	Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
29	G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain	DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement.	DATE	2005	DBLP DOI BibTeX RDF
29	Konrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald	Delay Insensitive Encoding and Power Analysis: A Balancing Act.	ASYNC	2005	DBLP DOI BibTeX RDF
29	Hemangee K. Kapoor, Mark B. Josephs	Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation.	ACSD	2005	DBLP DOI BibTeX RDF
29	Myeong-Hoon Oh, Dong-Soo Har	A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic.	PATMOS	2004	DBLP DOI BibTeX RDF
29	Alexander Taubin, Karl Fant, John McCardle	Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing.	ICCD	2002	DBLP DOI BibTeX RDF
29	Robert Berks, Radu Negulescu	Partial-Order Correctness-Preserving Properties of Delay-Insensitive Circuits.	ASYNC	2001	DBLP DOI BibTeX RDF
29	W. J. Bainbridge, Stephen B. Furber	Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding.	ASYNC	2001	DBLP DOI BibTeX RDF
29	Nattha Sretasereekul, Takashi Nanya	Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits.	ASP-DAC	2001	DBLP DOI BibTeX RDF
29	Willem C. Mallon	On Directed Transformations of Delay-Insensitive Specifications, Alternations and Dynamic Nondeterminism.	ASYNC	2000	DBLP DOI BibTeX RDF	{Communicating Processes}, {Computer Aided Design}, Meta-stability, Formal Methods, Handshake Protocol, Delay-Insensitivity
29	Fu-Chiung Cheng, Chuin-Ren Wang	Specification and Design of a Quasi-Delay-Insensitive Java Card.	VLSI Design	2000	DBLP DOI BibTeX RDF
29	Tom Verhoeff	Analyzing Specifications for Delay-Insensitive Circuits.	ASYNC	1998	DBLP DOI BibTeX RDF
29	Priyadarsan Patra, Stanislav Polonsky, Donald S. Fussell	Delay Insensitive Logic for RSFQ Superconductor Technology.	ASYNC	1997	DBLP DOI BibTeX RDF
29	Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho	Delay-Insensitive Carry-Lookahead Adders.	VLSI Design	1997	DBLP DOI BibTeX RDF
29	S. C. Leung, Hon Fung Li	On the realizability and synthesis of delay-insensitive behaviors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
29	S. C. Leung, Hon Fung Li	A syntax-directed translation for the synthesis of delay-insensitive circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
29	Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura	TITAC: Design of A Quasi-Delay-Insensitive Microprocessor.	IEEE Des. Test Comput.	1994	DBLP DOI BibTeX RDF
29	Mark B. Josephs, Jan Tijmen Udding	Delay-Insensitive Circuits: An Algebraic Approach to their Design.	CONCUR	1990	DBLP DOI BibTeX RDF
29	Alain J. Martin	The Design of a Delay-Insensitive Microprocessor: An Example of Circuit Synthesis by Program Transformation.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
26	David W. Lloyd, Jim D. Garside	A Practical Comparison of Asynchronous Design Styles.	ASYNC	2001	DBLP DOI BibTeX RDF
26	Scott C. Smith	Design of a logic element for implementing an asynchronous FPGA.	FPGA	2007	DBLP DOI BibTeX RDF	NULL convention logic (NCL), asynchronous logic design, field programmable gate array (FPGA), reconfigurable logic, delay-insensitive circuits
26	Mehrdad Najibi, Kamran Saleh, Hossein Pedram	Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	quasi-delay insensitive, standard-cell layout, asynchronous circuits
26	Signe J. Silver, Janusz A. Brzozowski	True Concurrency in Models of Asynchronous Circuit Behavior.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	multiple-winner, single-winner, semi-modular, asynchronous, circuit, interleaving, true concurrency, delay-insensitive
26	Luca G. Tallini, Bella Bose	Transmission Time Analysis for the Parallel Asynchronous Communication Scheme.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	delay-insensitive codes, proximity detecting codes, low weight codes, Asynchronous communication, constant weight codes, unordered codes
26	Scott C. Smith	Speedup of Self-Timed Digital Systems Using Early Completion.	ISVLSI	2002	DBLP DOI BibTeX RDF	asynchronous, NCL, NULL Convention Logic, delay-insensitive
26	Luca G. Tallini, Bella Bose	Some Transmission Time Analysis for the Parallel Asynchronous Communication Scheme.	FTCS	1999	DBLP DOI BibTeX RDF	delay-insensitive codes, proximity detecting codes, low weight codes, Asynchronous communication, constant weight codes, unordered codes
26	Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian	A Tabular Method for Guard Strengthening, Symmetrization, and Operator Reduction for Martin's Asynchronous Design Methodology.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	formal program transformation, self-timed logic, signal transition graphs (STG), speed independent circuits, guarded commands, delay insensitive circuits, Asynchronous sequential circuits
24	Dario Pompili, Tommaso Melodia	Three-dimensional routing in underwater acoustic sensor networks.	PE-WASUN	2005	DBLP DOI BibTeX RDF	routing algorithms, mathematical programming/optimization, underwater acoustic sensor networks
24	Myeong-Hoon Oh, Dong-Soo Har	Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP DOI BibTeX RDF
22	P. Balasubramanian 0001, David A. Edwards, Charlie Brej	Self-timed full adder designs based on hybrid input encoding.	DDECS	2009	DBLP DOI BibTeX RDF
19	Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger	Early evaluation for performance enhancement in phased logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
19	Susumu Adachi, Ferdinand Peper, Jia Lee	Universality of Hexagonal Asynchronous Totalistic Cellular Automata.	ACRI	2004	DBLP DOI BibTeX RDF
19	Mark B. Josephs	Formal Derivation of a Loadable Asynchronous Counter.	MPC	1998	DBLP DOI BibTeX RDF
19	Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni	Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits.	ISMVL	1997	DBLP DOI BibTeX RDF
19	Yong Zhang, Xin Zhang 0001	QoS Based Proportional Fair Scheduling Algorithm for CDMA Forward Link.	VTC Spring	2007	DBLP DOI BibTeX RDF
19	Zaheer Tabassam, Andreas Steininger	Towards Resilient Quasi Delay Insensitive Conditional Control Elements.	DSD	2023	DBLP DOI BibTeX RDF
19	Zaheer Tabassam, Andreas Steininger	SET Effects on Quasi Delay Insensitive and Synchronous Circuits.	ETS	2023	DBLP DOI BibTeX RDF
19	Zaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer	ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic.	ASYNC	2023	DBLP DOI BibTeX RDF
19	Duarte Lopes de Oliveira, Marcus H. Victor, Luiz C. Moreira, Felipe F. Nascimento	Design of Quasi Delay Insensitive Combinational Circuits Based on Optimized DIMS.	LASCAS	2023	DBLP DOI BibTeX RDF
19	Dalta Imam Maulana, Wanyeong Jung	An Energy-Efficient Delay Insensitive Asynchronous Interface for Globally Asynchronous Locally Synchronous (GALS) System.	ISCAS	2023	DBLP DOI BibTeX RDF
19	Zeguo Liu, Jingyi Yuan, Feng Wu, Lin Cheng 0001	A 12V/24V-to-1V PWM-Controlled DSD Converter With Delay-Insensitive and Dual-Phase Charging Techniques for Fast Transient Responses.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
19	Yue Feng, Yuanli Yue, Qiang Wu 0005, Chao Wang 0074	Delay-Insensitive Time Stretch Interrogation of Fiber Bragg Grating Sensors.	CSNDSP	2022	DBLP DOI BibTeX RDF
19	Orlando Verducci Jr., Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista	Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices.	LASCAS	2022	DBLP DOI BibTeX RDF
19	Raghda El Shehaby, Andreas Steininger	Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines.	DDECS	2021	DBLP DOI BibTeX RDF
19	Duarte Lopes de Oliveira, Gabriel C. Duarte, Gracieth Cavalcanti Batista	A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication.	LASCAS	2021	DBLP DOI BibTeX RDF
19	Taciano A. Rodolfo, Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans	Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison.	ISCAS	2021	DBLP DOI BibTeX RDF
19	Orlando Verducci Jr., Duarte Lopes de Oliveira, Robson L. Moreno	Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices.	LATS	2021	DBLP DOI BibTeX RDF
19	Linh Duc Tran, Thanh Chi Pham, Omid Kavehei, Peter C. M. Burton, Glenn Ian Matthews	Extended Boolean algebra for asynchronous quasi-delay-insensitive logic.	IET Circuits Devices Syst.	2020	DBLP DOI BibTeX RDF
19	Padmanabhan Balasubramanian, Nikos E. Mastorakis	Quasi-Delay-Insensitive Implementation of Approximate Addition.	Symmetry	2020	DBLP DOI BibTeX RDF
19	P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis	Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications.	CoRR	2020	DBLP BibTeX RDF
19	Yuri Stepchenkov, Yuri Rogdestvenski, Anton N. Kamenskih, Yuri Diachenko, Denis Diachenko	Improvement of the Quasi Delay-Insensitive Pipeline Noise Immunity.	DESSERT	2020	DBLP DOI BibTeX RDF
19	P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis	Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder.	CoRR	2019	DBLP BibTeX RDF
19	P. Balasubramanian 0001	Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders.	CoRR	2019	DBLP BibTeX RDF
19	Quang Tran Minh 0001, Van An Le, Tran Khanh Dang, Nam Thoai, Takeshi Kitahara	Flow aggregation for SDN-based delay-insensitive traffic control in mobile core networks.	IET Commun.	2019	DBLP DOI BibTeX RDF
19	Yi-Fan Evan Chang, Ruei-Yang Huang, Jie-Hong R. Jiang	Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits.	ASYNC	2019	DBLP DOI BibTeX RDF
19	P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis	Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications.	EECS	2019	DBLP DOI BibTeX RDF