Search results for "Design-for-Testability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
85	Dong Xiang, Yi Xu, Hideo Fujiwara	Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	inversion parity, nonscan design for testability, sequential depth for testability, Conflict, testability measure, partial scan design
78	Indradeep Ghosh, Niraj K. Jha, Sujit Dey	A low overhead design for testability and test generation technique for core-based systems-on-a-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
75	Frank F. Hsu, Janak H. Patel	A distance reduction approach to design for testability.	VTS	1995	DBLP DOI BibTeX RDF	distance reduction approach, center state, test function embedding technique, SFT techniques, logic testing, finite state machines, finite state machines, design for testability, design for testability, sequential circuits, sequential circuits, flip-flops, flip-flops, synthesis for testability, test function, average distance, DFT techniques
68	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Easily Testable Cellular Carry Lookahead Adders.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model
63	Dong Xiang, Shan Gu, Hideo Fujiwara	Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
63	Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee	A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality.	ISQED	2000	DBLP DOI BibTeX RDF	Equivalent faults, One-port circuits, Fault diagnosis, Design for testability, Fault collapsing
63	Alvin Jee, F. Joel Ferguson	A methodolgy for characterizing cell testability.	VTS	1997	DBLP DOI BibTeX RDF	cell testability, stuck-at fault coverage, IC quality, physical design for testability, metric, integrated circuit design, integrated circuit design, DPM, manufacturing defects
61	Charles E. Stroud, Ahmed E. Barbour	Testability and test generation for majority voting fault-tolerant circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	majority voting circuits, fault-tolerance, Design for testability, test pattern generation, multiple stuck-at faults
56	Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang	Design-for-testability and fault-tolerant techniques for FFT processors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
56	Dong Xiang, Shan Gu, Hideo Fujiwara	Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
55	Hingsam S. Fung, Sanford Hirschhorn, R. Kulkarni	Design for testability in a silicon compilation environment.	DAC	1985	DBLP DOI BibTeX RDF
53	Karim Arabi, Bozena Kaminska, Stephen K. Sunter	Design for testability of integrated operational amplifiers using oscillation-test strategy.	ICCD	1996	DBLP DOI BibTeX RDF	integrated operational amplifiers, oscillation-test strategy, vector-less test solution, test mode, oscillation frequency, nominal tolerance, digital circuitry, high fault coverage, simulation, design for testability, design for testability, oscillators, operational amplifiers, Monte Carlo analysis
47	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	A design-for-testability technique for register-transfer level circuits using control/data flow extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
47	Abhijit Chatterjee, Jacob A. Abraham	Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	Built-in self-test, test generation, design-for-testability, iterative logic array, pseudo-exhaustive test
47	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
46	Amey Karkare, Manoj Singla, Ajai Jain	Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit.	VLSI Design	1998	DBLP DOI BibTeX RDF	Testability Preserving Transformations, Testability Enhancing Transformations, DFT, Testability, Delay Faults
46	Irith Pomeranz, Sudhakar M. Reddy	Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines.	DATE	1998	DBLP DOI BibTeX RDF	synchronization, design-for-testability, synchronous sequential circuits
46	Frank F. Hsu, Janak H. Patel	Design for Testability Using State Distances.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	state distance, finite-state-machine, design-for-testability, synthesis-for-testability
46	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.	ICCD	1995	DBLP DOI BibTeX RDF	design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
45	Kee Sup Kim, Charles R. Kime	Partial scan flip-flop selection by use of empirical testability.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	scan flip-flop selection, serial scan, design for testability, testability, partial scan
43	Sandhya Seshadri, Michael S. Hsiao	Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	behavioral level, value range, SSA representation, design for testability
42	Sujit Dey, Miodrag Potkonjak	Nonscan design-for-testability techniques using RT-level design information.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
42	Thao Nguyen, Navid Rezvani	Printed Circuit Board Assembly Test Process and Design for Testability.	ISQED	2008	DBLP DOI BibTeX RDF
39	Irith Pomeranz, Sudhakar M. Reddy	Synthesis for Broadside Testability of Transition Faults.	VTS	2008	DBLP DOI BibTeX RDF	broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
39	Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara	Design for Testability Based on Single-Port-Change Delay Testing for Data Paths.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
39	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Hierarchical test generation and design for testability methods for ASPPs and ASIPs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
39	Da Wang, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001	Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	microprocessor design-for-testability, built-in self-test, test generation, at-speed testing
39	Teemu Kanstrén	A Study on Design for Testability in Component-Based Embedded Software.	SERA	2008	DBLP DOI BibTeX RDF	testing, components, design for testability, embedded software
39	Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida	Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	core test, design-for-testability, BIST, scan, boundary scan, test bus
39	Prab Varma, Tushar Gheewala	The economics of scan-path design for testability.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	state retention problem, Design for testability, scan, partial scan, test economics, life-cycle costs
38	Giacomo Buonanno, Franco Fummi, Donatella Sciuto	TIES: A testability increase expert system for VLSI design.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	design for testability techniques, DfT advisor, testability analysis, testable design
38	Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni	A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	Radio Frequency (RF) Testing, Design for Testability (DFT), Voltage Controlled Oscillator (VCOs)
38	Cecilia Metra, T. M. Mak, Martin Omaña 0001	Fault secureness need for next generation high performance microprocessor design for testability structures.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	built in self test, design for testability, microprocessor, comparator, fault secureness
38	Yervant Zorian	Fundamentals of MCM Testing and Design-for-Testability.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	known good dies, design-for-testability, MCM testing
38	Michiel M. Ligthart, Emile H. L. Aarts, Frans P. M. Beenker	Design-for-testability of PLA's using statistical cooling.	DAC	1986	DBLP DOI BibTeX RDF	PLA testing, statistical cooling, design-for-testability, PLA
38	Seiken Yano	Unified scan design with scannable memory arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits
38	Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara	A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	strong testability, partially strong testability, complete fault efficiency, design-for-testability, data paths
38	Tomokazu Yoneda, Hideo Fujiwara	Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	consecutive transparency, built-in self test, design for testability, system-on-a-chip, test access mechanism, consecutive testability
38	Tomokazu Yoneda, Hideo Fujiwara	A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	consecutive transparency, core-based systems-on-a-chip, design for testability, test access mechanism, consecutive testability
38	Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik	Integration of partial scan and built-in self-test.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	test points, built-in self-test, design for testability, partial scan
38	Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer	On testable multipliers for fixed-width data path architectures.	ICCAD	1995	DBLP DOI BibTeX RDF	Fixed-Width Architectures, Built-in Self -Test, High-level Synthesis, Design for Testability
37	Thomas W. Williams	Design for Testability: The Path to Deep Submicron.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
37	Roberto Bevacqua, Luca Guerrazzi, Franco Fummi	SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation.	EUROMICRO	1996	DBLP DOI BibTeX RDF	test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences
37	S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault	Test configurations to enhance the testability of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector
37	Mohamed Soufi, Yvon Savaria, Bozena Kaminska	On the design of at-speed testable VLSI circuits.	VTS	1995	DBLP DOI BibTeX RDF	at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique
37	Imtiaz P. Shaik, Michael L. Bushnell	A graph approach to DFT hardware placement for robust delay fault BIST.	VLSI Design	1995	DBLP DOI BibTeX RDF	graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
37	Elizabeth M. Rudnick, Janak H. Patel	A genetic approach to test application time reduction for full scan and partial scan circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	partial scan circuits, design-for-testability techniques, compact test set generation, genetic algorithms, genetic algorithms, logic testing, design for testability, logic design, sequential circuits, combinational circuits, DFT, flip-flops, test application time reduction, full scan circuits
34	Shyue-Kung Lu, Chien-Hung Yeh	Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
33	Abhijit Chatterjee, Naveena Nagi	Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial.	VLSI Design	1997	DBLP DOI BibTeX RDF
33	Vivek Chickermane, Jaushin Lee, Janak H. Patel	Addressing design for testability at the architectural level.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
33	Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu	Design of C-Testable Multipliers Based on the Modified Booth Algorithm.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	modified Booth Algorithm, c-testable design, design for testability, multiplier, exhaustive testing, cell fault model
33	Arun Balakrishnan, Srimat T. Chakradhar	Software transformations for sequential test generation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	sequential test generation, high fault coverage test sets, testability properties, inverse mapping, software engineering, logic testing, timing, design for testability, sequential circuits, sequential circuits, DFT, software model, software transformations
32	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	A design for testability technique for RTL circuits using control/data flow extraction.	ICCAD	1996	DBLP DOI BibTeX RDF
32	Sujit Dey, Vijay Gangaram, Miodrag Potkonjak	A controller-based design-for-testability technique for controller-data path circuits.	ICCAD	1995	DBLP DOI BibTeX RDF
32	Sujit Dey, Miodrag Potkonjak	Non-scan design-for-testability of RT-level data paths.	ICCAD	1994	DBLP DOI BibTeX RDF
31	Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi	A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
31	Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang, Soon-Jyh Chang	An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders.	APCCAS	2006	DBLP DOI BibTeX RDF
31	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs.	DAC	1997	DBLP DOI BibTeX RDF
31	Shaahin Hessabi, Mohamed Y. Osman, Mohamed I. Elmasry	Differential BiCMOS logic circuits: fault characterization and design-for-testability.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
31	Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara	A DFT Method for Time Expansion Model at Register Transfer Level.	DAC	2007	DBLP DOI BibTeX RDF
31	Shyue-Kung Lu, Mau-Jung Lu	Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model.	DELTA	2004	DBLP DOI BibTeX RDF
31	Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet	Test and Testability of a Monolithic MEMS for Magnetic Field Sensing.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	design for testability, production testing, low-cost testing, MEMS testing
30	Richard M. Chou, Kewal K. Saluja	Sequential Circuit Testing: From DFT to SFT.	VLSI Design	1997	DBLP DOI BibTeX RDF	design-for-testability methods, SFT techniques, large sequential circuits, logic testing, automatic test pattern generation, ATPG, synthesis-for-testability, sequential circuit testing, DFT techniques
30	Rolf Drechsler, Junhao Shi, Görschwin Fey	MuTaTe: an efficient design for testability technique for multiplexor based circuits.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	multiplexor based circuits, design for testability, logic synthesis, BDDs, decision diagrams
30	Yves Le Traon, Daniel Deveaux, Jean-Marc Jézéquel	Self-Testable Components: From Pragmatic Tests to Design-for-Testability Methodology.	TOOLS (29)	1999	DBLP DOI BibTeX RDF	testing, design-for-testability, self-test, design by contract, reusable components
30	Sujit Dey, Anand Raghunathan, Kenneth D. Wagner	Design for Testability Techniques at the Behavioral and Register-Transfer Levels.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability
30	Saied Bozorgui-Nesbat, Edward J. McCluskey	Lower Overhead Design for Testability of Programmable Logic Arrays.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	test generation for PLA's, PLA testing, Design for testability, programmable logic arrays (PLA)
29	Chia Yee Ooi, Hideo Fujiwara	A New Design-for-Testability Method Based on Thru-Testability.	J. Electron. Test.	2011	DBLP DOI BibTeX RDF
29	Dong Xiang, Yi Xu	Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement.	ICCD	2001	DBLP DOI BibTeX RDF
29	Rachida Dssouli, Kamel Karoui, Kassem Saleh, Omar Cherkaoui	Communications software design for testability: specification transformations and testability measures.	Inf. Softw. Technol.	1999	DBLP DOI BibTeX RDF
29	Sandhya Seshadri, Michael S. Hsiao	An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques.	ITC	1999	DBLP DOI BibTeX RDF
29	Ting-Hua Chen, Melvin A. Breuer	Automatic Design for Testability Via Testability Measures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1985	DBLP DOI BibTeX RDF
28	Dhruva R. Chakrabarti, Ajai Jain	An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph
28	Franco Fummi, Donatella Sciuto, M. Serro	Synthesis for testability of large complexity controllers.	ICCD	1995	DBLP DOI BibTeX RDF	large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates
26	Jin-Fu Li 0001, Cheng-Wen Wu	Efficient FFT network testing and diagnosis schemes.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
26	Mehrdad Bidjan-Irani	A Rule-Based Design-for-Testability Rule Checker.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
25	Matthew L. King, Kewal K. Saluja	Testing Micropipelined Asynchronous Circuits.	ITC	2004	DBLP DOI BibTeX RDF
25	Thomas W. Williams	Testing in Nanometer Technologies.	DATE	1999	DBLP DOI BibTeX RDF
25	Jacob Savir	Design for Testability to Combat Delay Faults.	ICCD	1999	DBLP DOI BibTeX RDF	BIST, LFSR, Delay Test, MISR, LSSD, SRL
25	Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka	A Design for testability Method Using RTL Partitioning.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	line-up structure, internally balanced structure, acyclic structure, partitioning, ATPG, DFT, RTL, isolation, balanced structure
25	Benoit Baudry, Yves Le Traon, Gerson Sunyé	Testability Analysis of a UML Class Diagram.	IEEE METRICS	2002	DBLP DOI BibTeX RDF
25	João Paulo Teixeira 0001, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves	A methodology for testability enhancement at layout level.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	physical design rules for testability, simulation, fault modeling, testability analysis
25	Irith Pomeranz, Sudhakar M. Reddy	Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths.	VLSI Design	2008	DBLP DOI BibTeX RDF
25	Thomas W. Williams, Rohit Kapur	Design for Testability in Nanometer Technologies; Searching for Quality.	ISQED	2000	DBLP DOI BibTeX RDF
25	Juan A. Prieto, Adoración Rueda, Ian Andrew Grout, Eduardo J. Peralías, José L. Huertas, Andrew Mark David Richardson	An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits.	DATE	1998	DBLP DOI BibTeX RDF
25	Irith Pomeranz, Sudhakar M. Reddy	On Full Reset as a Design-For-Testability Technique.	VLSI Design	1997	DBLP DOI BibTeX RDF
24	Anthony Chung, Tao Huang 0019	Two Approaches for the Improvement in Testability of Communication Protocols.	ACIS-ICIS	2005	DBLP DOI BibTeX RDF
24	Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz	Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs.	DSD	2005	DBLP DOI BibTeX RDF
24	Nai-Chi Lee	A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF
24	João Paulo Teixeira 0001, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves, R. Crespo	A strategy for testability enhancement at layout level.	EURO-DAC	1990	DBLP DOI BibTeX RDF
24	Irith Pomeranz, Sudhakar M. Reddy	Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity.	VLSI Design	2008	DBLP DOI BibTeX RDF
24	Loganathan Lingappan, Niraj K. Jha	Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
24	Loganathan Lingappan, Niraj K. Jha	Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
24	Irith Pomeranz, Sudhakar M. Reddy	Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
24	Irith Pomeranz, Sudhakar M. Reddy	On masking of redundant faults in synchronous sequential circuits with design-for-testability logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
24	Loganathan Lingappan, Niraj K. Jha	Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits.	VTS	2005	DBLP DOI BibTeX RDF
24	Cecilia Metra, T. M. Mak, Martin Omaña 0001	Are Our Design for Testability Features Fault Secure?	DATE	2004	DBLP DOI BibTeX RDF
24	Irith Pomeranz, Sudhakar M. Reddy	On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic.	ICCAD	2003	DBLP DOI BibTeX RDF
24	Sanghyeon Baeg, William A. Rogers	A cost-effective design for testability: clock line control and test generation using selective clocking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
24	Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar	Primitive delay faults: identification, testing, and design for testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF