Search results for "Designs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
78	Gholamreza B. Khosrovshahi, Behruz Tayfeh-Rezaie	Some Indecomposable t-Designs.	Des. Codes Cryptogr.	2004	DBLP DOI BibTeX RDF	indecomposable designs, large sets of t-designs, disjoint designs, t-designs
64	Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar	A multiplier generator for Xilinx FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
60	Eric S. Lee, Thomas Whalen	Synthetic designs: a new form of true experimental design for use in information systems development.	SIGMETRICS	2007	DBLP DOI BibTeX RDF	synthetic experimental designs, experimental designs
60	Michael Braun, Adalbert Kerber, Reinhard Laue	Systematic Construction of q-Analogs of t-(v, k, lambda)-Designs.	Des. Codes Cryptogr.	2005	DBLP DOI BibTeX RDF	designs over finite fields, Kramer-Mesner method, group actions, q-analogs, t-designs
52	Dean S. Hoskins, Charles J. Colbourn, Douglas C. Montgomery	Software performance testing using covering arrays: efficient screening designs with categorical factors.	WOSP	2005	DBLP DOI BibTeX RDF	D-optimal designs, performance testing, covering arrays
50	Jianzhong Shi, Akash Randhar, Dinesh Bhatia	Macro Block Based FPGA Floorplanning.	VLSI Design	1997	DBLP DOI BibTeX RDF	macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design
48	Ziba Eslami, Gholamreza B. Khosrovshahi, Morteza Mohammad Noori	Enumeration of t-Designs Through Intersection Matrices.	Des. Codes Cryptogr.	2004	DBLP DOI BibTeX RDF	derived designs, intersection matrices, t-designs
45	Ronald H. Hardin, Neil J. A. Sloane	McLaren's Improved Snub Cube and Other New Spherical Designs in Three Dimensions.	Discret. Comput. Geom.	1996	DBLP DOI BibTeX RDF
41	Behruz Tayfeh-Rezaie	On the Existence of Large Sets of t-designs of Prime Sizes.	Des. Codes Cryptogr.	2005	DBLP DOI BibTeX RDF	large sets of t-designs, (N, t)-partitionable sets, recursive constructions, t-designs
41	Usman Khalid, Jahanzeb Anwer, Nor Hisham Hamid, Vijanth S. Asirvadam	The Impact of Sensitive Inputs on the Reliability of Nanoscale Circuits.	Computational Intelligence in Digital and Network Designs and Applications	2015	DBLP DOI BibTeX RDF
41	Yann Kieffer, Lilia Zaourar	Applying Operations Research to Design for Test Insertion Problems.	Computational Intelligence in Digital and Network Designs and Applications	2015	DBLP DOI BibTeX RDF
41	Quentin Angermann, Aymeric Histace, Olivier Romain, Xavier Dray, Andréa Pinna 0001, Bertrand Granado	Smart Videocapsule for Early Diagnosis of Colorectal Cancer: Toward Embedded Image Analysis.	Computational Intelligence in Digital and Network Designs and Applications	2015	DBLP DOI BibTeX RDF
41	Kunal Das, Arijit Dey, Dipannita Podder, Mallika De, Debashis De	Quantum Dot Cellular Automata: A Promising Paradigm Beyond Moore.	Computational Intelligence in Digital and Network Designs and Applications	2015	DBLP DOI BibTeX RDF
41	Oana Stan, Renaud Sirdey	Introduction to Optimization Under Uncertainty Techniques for High-Performance Multicore Embedded Systems Compilation.	Computational Intelligence in Digital and Network Designs and Applications	2015	DBLP DOI BibTeX RDF
41	Jai Narayan Tripathi, Jayanta Mukherjee 0002	Decoupling Network Optimization by Swarm Intelligence.	Computational Intelligence in Digital and Network Designs and Applications	2015	DBLP DOI BibTeX RDF
41	Houman Zarrabi, A. J. Al-Khalili, Yvon Savaria	Design Intelligence for Interconnection Realization in Power-Managed SoCs.	Computational Intelligence in Digital and Network Designs and Applications	2015	DBLP DOI BibTeX RDF
41	Mohamed Ibrahim, Cherif R. Salama, M. Watheq El-Kharashi, Ayman Wahba	Pin-Count and Wire Length Optimization for Electrowetting-on-Dielectric Chips: A Metaheuristics-Based Routing Algorithm.	Computational Intelligence in Digital and Network Designs and Applications	2015	DBLP DOI BibTeX RDF
41	Sayed Taha Muhammad, Rabab Ezz-Eldin, Magdy A. El-Moursy, Amr M. Refaat	Low-Power NoC Using Optimum Adaptation.	Computational Intelligence in Digital and Network Designs and Applications	2015	DBLP DOI BibTeX RDF
41	Ayan Palchaudhuri, Rajat Subhra Chakraborty	A Fabric Component Based Approach to the Architecture and Design Automation of High-Performance Integer Arithmetic Circuits on FPGA.	Computational Intelligence in Digital and Network Designs and Applications	2015	DBLP DOI BibTeX RDF
41	Yu Wang 0021, Weishan Dong, Junchi Yan, Li Li 0022, Chunhua Tian, Chao Zhang 0010, Zhihu Wang, Chunyang Ma	Digital IIR Filter Design with Fix-Point Representation Using Effective Evolutionary Local Search Enhanced Differential Evolution.	Computational Intelligence in Digital and Network Designs and Applications	2015	DBLP DOI BibTeX RDF
41	Logan Rakai, Amin Farshidi	Sizing Digital Circuits Using Convex Optimization Techniques.	Computational Intelligence in Digital and Network Designs and Applications	2015	DBLP DOI BibTeX RDF
38	Eric Merchant	Exponentially Many Hadamard Designs.	Des. Codes Cryptogr.	2006	DBLP DOI BibTeX RDF	Hadamard designs, symmetric designs, BIBD
38	Mahsa Vahidi, Alex Orailoglu	Testability metrics for synthesis of self-testable designs and effective test plans.	VTS	1995	DBLP DOI BibTeX RDF	testability metrics, self-testable designs, effective test plans, unified metrics, synthesis phases, VLSI, VLSI, built-in self test, high level synthesis, high level synthesis, design for testability, BIST, DFT, logic CAD, integrated circuit design, benchmark designs
37	Michael Zapf, Ute Lindheimer, Armin Heinzl	The myth of accelerating business processes through parallel job designs.	Inf. Syst. E Bus. Manag.	2007	DBLP DOI BibTeX RDF	Job parallelization, Order processing, Process simulation, Coordination theory, Business process design, Parallel designs
37	Stelios Georgiou, Christos Koukouvinos	Self-Orthogonal and Self-Dual Codes Constructed via Combinatorial Designs and Diophantine Equations.	Des. Codes Cryptogr.	2004	DBLP DOI BibTeX RDF	generalized orthogonal designs, construction, self-dual codes, Diophantine equations
35	Jun-Wu Dong, Dingyi Pei, Xueli Wang	A Key Predistribution Scheme Based on 3-Designs.	Inscrypt	2007	DBLP DOI BibTeX RDF	key predistribution schemes, 3-designs, Möbius planes, sensor networks, combinatorial designs
35	Gennian Ge, Alan C. H. Ling	Group Divisible Designs with Block Size Four and Group Type gum1 with Minimum m.	Des. Codes Cryptogr.	2005	DBLP DOI BibTeX RDF	group divisible designs, double group divisible designs
35	Kowen Lai, Christos A. Papachristou, Mikhail Baklashov	BIST testability enhancement using high level test synthesis for behavioral and structural designs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	BIST testability, behavioral designs, industrial benchmark, controllability, built-in self test, observability, DFT, transparency, fidelity, structural designs, high level test synthesis
34	Jun Hu, Xiaofeng Yu, Yan Zhang 0007, Tian Zhang 0001, Xuandong Li, Guoliang Zheng	Checking Component-Based Embedded Software Designs for Scenario-Based Timing Specifications.	EUC	2005	DBLP DOI BibTeX RDF	embedded software designs, real-time systems, model checking, UML sequence diagrams, interface automata
34	Sherif M. Yacoub, Hany H. Ammar, Tom Robinson	Dynamic Metrics for Object Oriented Designs.	IEEE METRICS	1999	DBLP DOI BibTeX RDF	Object-Oriented Designs and Real-Time OO Modeling, Dynamic Metrics, Design Quality
33	Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang	A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs.	DATE	2003	DBLP DOI BibTeX RDF
31	Keith M. Martin	On the Applicability of Combinatorial Designs to Key Predistribution for Wireless Sensor Networks.	IWCC	2009	DBLP DOI BibTeX RDF	sensor networks, Key predistribution, combinatorial designs
31	Bernhard Peischl, Naveed Riaz, Franz Wotawa	Advances in Automated Source-Level Debugging of Verilog Designs.	New Challenges in Applied Intelligence Technologies	2008	DBLP DOI BibTeX RDF	debugging of hardware designs, multiple testcases, model-based diagnosis, software debugging
31	Haibin Kan, Hong Shen 0001	The maximal rates of more general complex orthogonal designs.	PDCAT	2005	DBLP DOI BibTeX RDF	complex orthogonal designs, maximal rates, delays, space-time block codes
31	Franz Wotawa	Debugging VHDL Designs: Introducing Multiple Models and First Empirical Results.	Appl. Intell.	2004	DBLP DOI BibTeX RDF	debugging hardware designs, modeling for diagnosis, model-based diagnosis
31	Kwang-Ting Cheng	Partial scan designs without using a separate scan clock.	VTS	1995	DBLP DOI BibTeX RDF	flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock
30	David M. Cohen, Siddhartha R. Dalal, Michael L. Fredman, Gardner C. Patton	The AETG System: An Approach to Testing Based on Combinatiorial Design.	IEEE Trans. Software Eng.	1997	DBLP DOI BibTeX RDF	Testing, experimental designs, combinatorial designs, orthogonal arrays
30	Jacob Savir	Generator choices for delay test.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test
30	Ling Zhuo, Viktor K. Prasanna	High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
30	Jacob E. Boon	Generating exact D-optimal designs for polynomial models.	SpringSim (3)	2007	DBLP BibTeX RDF	general linear regression, optimal experimental design, mathematical optimization
30	Zhijiang Chang, Georgi Gaydadjiev, Stamatis Vassiliadis	Infrastructure for Cross-Layer Designs Interaction.	ICCCN	2007	DBLP DOI BibTeX RDF
30	Love Singhal, Elaheh Bozorgzadeh	Multi-layer Floorplanning on a Sequence of Reconfigurable Designs.	FPL	2006	DBLP DOI BibTeX RDF
30	Jingzhao Ou, Viktor K. Prasanna	PyGen: A MATLAB/Simulink Based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
30	Dean S. Hoskins, Renée Turban, Charles J. Colbourn	Experimental designs in software engineering: d-optimal designs and covering arrays.	WISER	2004	DBLP DOI BibTeX RDF	d-optimal designs, factorial experiments, covering arrays
28	Thomas W. Williams	Testing in Nanometer Technologies.	DATE	1999	DBLP DOI BibTeX RDF
28	Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai	DFM/DFY practices during physical designs for timing, signal integrity, and power.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, DFY, dynamic IR drop, process variation, physical designs, DFM, design for manufacturability, signal integrity, timing integrity, yield analysis, design for yield
28	Sushmita Ruj, Bimal K. Roy	Key Predistribution Using Partially Balanced Designs in Wireless Sensor Networks.	ISPA	2007	DBLP DOI BibTeX RDF	PBIBD designs, Resiliency, Combinatorial Design
28	Ilias S. Kotsireas, Christos Koukouvinos	Inequivalent Hadamard matrices from orthogonal designs.	PASCO	2007	DBLP DOI BibTeX RDF	orthogonal designs, systems of polynomial equations, Hadamard matrices
28	Elli Georgiadou, Eleni Berki, Maria del Brezo Cordero, Margaret Ross 0001, Geoff Staples	Towards Formalised Guidelines for Migrating Structured Designs to UML: A Case Study.	Softw. Qual. J.	2005	DBLP DOI BibTeX RDF	isomorphic models, UML, testing, reuse, re-engineering, structured designs, OO
28	Dong-Joon Shin, P. Vijay Kumar, Tor Helleseth	An Assmus-Mattson-Type Approach for Identifying 3-Designs from Linear Codes over Z4.	Des. Codes Cryptogr.	2004	DBLP DOI BibTeX RDF	Z 4 codes, Assmus-Mattson, complete weight enumerator, t-designs
28	David Masson	Designs and Representation of the Symmetric Group.	Des. Codes Cryptogr.	2003	DBLP DOI BibTeX RDF	association scheme, Specht module, Hahn polynomials, Designs, tableaux, self-dual codes, symmetric group
28	Daniel Köb, Bernhard Peischl, Franz Wotawa	Debugging VHDL Designs Using Temporal Process Instances.	IEA/AIE	2003	DBLP DOI BibTeX RDF	debugging of hardware designs, model-based diagnosis, software debugging
28	John R. Samson Jr., Wilfrido Alejandro Moreno, Fernando J. Falquez	Validating fault tolerant designs using laser fault injection (LFI).	DFT	1997	DBLP DOI BibTeX RDF	fault tolerant designs validation, laser fault injection, VHSIC technology, in situ testing, transient error conditions, VLSI, faults, automated testing, transient, VLSI technology
28	William W. Agresti, William M. Evanco	Projecting Software Defects From Analyzing Ada Designs.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	software defects projection, context coupling, Ada designs, process characteristics, import-export of declarations, reuse level, regression analyses, Ada, static analysis, software quality, software quality, software metrics, software reliability, statistical analysis, visibility, defect density
27	Norifumi Kamiya, Marc P. C. Fossorier	Quasi-Cyclic Codes from a Finite Affine Plane.	Des. Codes Cryptogr.	2006	DBLP DOI BibTeX RDF	affine planes, incidence matrices, oval designs, combinatorial designs, quasi-cyclic codes
27	Artan Dimnaku, Rex K. Kincaid, Michael W. Trosset	Approximate Solutions of Continuous Dispersion Problems.	Ann. Oper. Res.	2005	DBLP DOI BibTeX RDF	maximin distance designs, space-filling designs, nonlinear programming, location theory, computer experiments
27	Vamsi Krishna, N. Ranganathan	A Methodology for High Level Power Estimation and Exploration.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Low Power Designs, Power Estimation, Switching Activity, High Level Designs
27	David B. Skillicorn	A New Class of Fault-Tolerant Static Interconnection Networks.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	balanced incomplete block designs, performance-cost tradeoffs, fault-tolerant static interconnection networks, combinatorial block designs, fault-tolerant properties, performance evaluation, fault tolerant computing, multiprocessor interconnection networks, graceful degradation
26	Ling Zhuo, Viktor K. Prasanna	Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
26	John Arhin	On the structure of 1-designs with at most two block intersection numbers.	Des. Codes Cryptogr.	2007	DBLP DOI BibTeX RDF	05B25, AMS Classifications 05B05
26	Yinghui Li, Hlaing Minn, Naofal Al-Dhahir, A. Robert Calderbank	Pilot Designs for Consistent Frequency-Offset Estimation in OFDM Systems.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
26	Ling Zhuo, Viktor K. Prasanna	Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems.	ICPADS (1)	2006	DBLP DOI BibTeX RDF
26	Masahiro Fujita, Shunsuke Sasaki, Ken Matsui	Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse.	IRI	2005	DBLP DOI BibTeX RDF
26	Byungjeong Lee, Chisu Wu	An Automatic Restructuring Approach Preserving the Behavior of Object-Oriented Designs.	APSEC	2001	DBLP DOI BibTeX RDF
26	Masayoshi Yoshimura	Implementation of Multiobjective Optimization Procedures at the Product Design Planning Stage.	System Modelling and Optimization	2005	DBLP DOI BibTeX RDF	Product design planning stage, Pareto optimum solutions, Comparison of alternative designs, Hierarchical optimization problem, Rapid evaluation, Deeper insight into design solutions, Multiobjective optimization
26	Reinhard Rauscher	A Design Assistant for Scheduling of Design Decisions.	EUROMICRO	1996	DBLP DOI BibTeX RDF	scheduling, scheduling, VLSI designs, design decisions, design assistant
26	Douglas E. Harms, Bruce W. Weide	Copying and Swapping: Influences on the Design of Reusable Software Components.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	data movement primitive, generic reusable software components, generic module designs, swapping style, data structures, software reusability
25	Min-Lun Chuang, Chun-Yao Wang	Synthesis of reversible sequential elements.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	sequential elements, sequential circuits, Reversible logic
25	Ju-wook Jang, Seonil B. Choi, Viktor K. Prasanna	Energy- and time-efficient matrix multiplication on FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
25	Yingmin Li, Mark Hempstead, Patrick Mauro, David M. Brooks, Zhigang Hu, Kevin Skadron	Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices.	ISLPED	2005	DBLP DOI BibTeX RDF	architecture, power, temperature, clock gating
25	Seonil Choi, Viktor K. Prasanna	Time and Energy Efficient Matrix Factorization Using FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
25	John W. Byers, Michael Mitzenmacher, Georgios Zervas	Adaptive weighing designs for keyword value computation.	WSDM	2010	DBLP DOI BibTeX RDF	weighing designs, regression, least squares, design of experiments
25	Xinlu Zhang, Jun Guo 0004, Suogang Gao	Two new error-correcting pooling designs from d -bounded distance-regular graphs.	J. Comb. Optim.	2009	DBLP DOI BibTeX RDF	s e -disjunct matrix, Distance-regular graph, Strongly closed subgraphs, Pooling designs
25	Christos Koukouvinos, Dimitris E. Simos	Self-dual Codes over Small Prime Fields from Combinatorial Designs.	CAI	2009	DBLP DOI BibTeX RDF	construction, combinatorial designs, Self-dual codes
25	Sudhir Vinjamuri, Viktor K. Prasanna	Hierarchical Dependency Graphs: Abstraction and Methodology for Mapping Systolic Array Designs to Multicore Processors.	PaCT	2009	DBLP DOI BibTeX RDF	systolic array designs, parallel programming, high performance computing, multicore, dependency graphs
25	Hong-Bin Chen, Hung-Lin Fu, Frank K. Hwang	An upper bound of the number of tests in pooling designs for the error-tolerant complex model.	Optim. Lett.	2008	DBLP DOI BibTeX RDF	Nonadaptive algorithms, Disjunct matrices, Pooling designs
25	Mohammad Tehranipoor, Kenneth M. Butler	Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	PSN, IR drop, power supply noise, deep-submicron designs
25	Rosa Gil 0001, César A. Collazos 0001	Integrating Emotions and Knowledge in Aesthetics Designs Using Cultural Profiles.	HCI (11)	2007	DBLP DOI BibTeX RDF	aesthetics designs, cultural relations, interfaces, emotions
25	Mohamed H. Zaki, Ghiath Al Sammane, Sofiène Tahar	Formal Verification of Analog and Mixed Signal Designs in Mathematica.	International Conference on Computational Science (2)	2007	DBLP DOI BibTeX RDF	AMS Designs, Formal Verification, Mathematica
25	Ulrich Dempwolff	Affine Rank 3 Groups on Symmetric Designs.	Des. Codes Cryptogr.	2004	DBLP DOI BibTeX RDF	rank 3 groups, symmetric designs
25	Dong-Joon Shin, P. Vijay Kumar, Tor Helleseth	3-Designs from the Z4-Goethals Codes via a New Kloosterman Sum Identity.	Des. Codes Cryptogr.	2003	DBLP DOI BibTeX RDF	Z 4-Goethals codes, Kloosterman sums, t-designs
25	Frank K. Hwang, Yu-Chi Liu	Random Pooling Designs Under Various Structures.	J. Comb. Optim.	2003	DBLP DOI BibTeX RDF	random pooling designs, clone library screening, k-clique
25	Víctor A. Braberman, Fabio Pieniazek	Duration Properties over Real Time System Designs.	IWSSD	2000	DBLP BibTeX RDF	Duration Properties, Model-Checking, Timed Automata, Real-Time System Designs
25	Hans T. Heineken, Wojciech Maly	Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs.	ICCAD	1996	DBLP DOI BibTeX RDF	Standard Cell Designs, Synthesis, Interconnects, Manufacturability, Yield
25	Ching-Long Su, Alvin M. Despain	Cache designs for energy efficiency.	HICSS (1)	1995	DBLP DOI BibTeX RDF	cache design techniques, superpipelined processors, cache energy consumption estimation, block buffering, cache sub-banking, Gray code addressing, instruction cache designs, consecutive accessing, energy efficiency, microprocessors, power consumption, energy conservation, data caches, cache storage, superscalar processors, Gray codes, energy reduction, CMOS memory circuits
25	Frank Poirot, Gerard Tarroux, Ramine Roane	Optimization using implicit techniques for industrial designs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	implicit techniques, Boolean functions, Boolean functions, logic synthesis, logic CAD, binary decision diagrams, hardware description languages, hardware description languages, industrial designs, circuit optimisation, optimization techniques, design complexity
25	William L. Bradley, Ranga Vemuri	Transformations for functional verification of synthesized designs.	VLSI Design	1995	DBLP DOI BibTeX RDF	low-level functional verification, synthesized designs, clocking mechanisms, provably equivalent model, hierarchical network of modules, reduced state set, de-phase transform, align transform, algorithm, formal verification, transforms, transforms, logic CAD, clocks, hierarchical system, reachable states
25	Sergio Cárdenas-García, Marvin V. Zelkowitz	A Management Tool For Evaluation of Software Designs.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	economic decision theory, prototyping investigative system, equilibrium probabilities, software tools, decision support system, decision support systems, program verification, program verification, software designs, software prototyping, risk analysis, functional model, evaluation strategy, Selector, management tool
24	Emre Kolotoglu, Emine Sule Yazici	On Minimal Defining Sets of Full Designs and Self-Complementary Designs, and a New Algorithm for Finding Defining Sets of t-Designs.	Graphs Comb.	2010	DBLP DOI BibTeX RDF
23	David Ahlström, Andy Cockburn, Carl Gutwin, Pourang Irani	Why it's quick to be square: modelling new and existing hierarchical menu designs.	CHI	2010	DBLP DOI BibTeX RDF	performance models, menus, hierarchical menus
23	Vummintala Shashidhar, B. Sundar Rajan, P. Vijay Kumar	Asymptotic-Information-Lossless Designs and the Diversity-Multiplexing Tradeoff.	IEEE Trans. Inf. Theory	2009	DBLP DOI BibTeX RDF
23	Jennifer Seberry, Kenneth Finlayson, Sarah Spence Adams, Tadeusz A. Wysocki, Tianbing Xia, Beata J. Wysocki	The Theory of Quaternion Orthogonal Designs.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
23	Christopher G. Jennings, Arthur E. Kirkpatrick	Design as traversal and consequences: an exploration tool for experimental designs.	Graphics Interface	2007	DBLP DOI BibTeX RDF	history capture, design space exploration, experimental design, design rationale, design spaces, creativity support
23	Mustafa Gök, Çaglar Yilmaz	Efficient Cell Designs for Systolic Smith-Waterman Implementations.	FPL	2006	DBLP DOI BibTeX RDF
23	Mustafa Gök, Çaglar Yilmaz	Hardware Designs for Local Alignment of Protein Sequences.	ISCIS	2006	DBLP DOI BibTeX RDF
23	Kyung-Yong Jung	Automatic Classification for Grouping Designs in Fashion Design Recommendation Agent System.	KES (1)	2006	DBLP DOI BibTeX RDF
23	Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu	Low Power Multiplier Designs Based on Improved Column Bypassing Schemes.	APCCAS	2006	DBLP DOI BibTeX RDF
23	Genyuan Wang, Xiang-Gen Xia 0001	On optimal multilayer cyclotomic space-time code designs.	IEEE Trans. Inf. Theory	2005	DBLP DOI BibTeX RDF
23	Haibin Kan, Hong Shen 0001	A counterexample for the open problem on the minimal delays of orthogonal designs with maximal rates.	IEEE Trans. Inf. Theory	2005	DBLP DOI BibTeX RDF
23	Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty	Untestable Multi-Cycle Path Delay Faults in Industrial Designs.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF