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Publication years (Num. hits)
1991-1998 (16) 1999-2000 (17) 2001 (40) 2002 (29) 2003 (40) 2004 (38) 2005 (42) 2006 (37) 2007 (32) 2008 (32) 2009 (39) 2010 (29) 2011 (35) 2012 (31) 2013 (41) 2014 (26) 2015 (45) 2016 (36) 2017 (34) 2018 (30) 2019 (23) 2020 (35) 2021 (26) 2022 (21) 2023 (30) 2024 (5)
Publication types (Num. hits)
article(398) inproceedings(399) phdthesis(12)
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Results
Found 809 publication records. Showing 809 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
170Ming-Dou Ker, Hun-Hsien Chang, Tung-Yang Chen ESD buses for whole-chip ESD protection. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
154Ganesh R. Shamnur, Rajesh R. Berigei XStatic: A Simulation Based ESD Verification and Debug Environment. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF XStatic, ESD
141Chih-Hung Liu 0001, Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Yao-Wen Chang, Sy-Yen Kuo, Shih-Yi Yuan, Yu-Wei Chen An Efficient Graph-Based Algorithm for ESD Current Path Analysis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
141Harald Gossner ESD protection for the deep sub micron regime - a challenge for design methodology. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
127Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits. Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
127Ming-Dou Ker, Tung-Yang Chen Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
126Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu 0001, Yao-Wen Chang, Sy-Yen Kuo Current path analysis for electrostatic discharge protection. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
124Ming-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF ESD, ESD protection circuit, substrate-triggered technique
113Paul C. F. Tong, Ping-Ping Xu, Wensong Chen, John Hui, Patty Z. Q. Liu A novel substrate-triggered ESD protection structure for a bus switch IC with on-chip substrate-pump. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
110Thomas Pompl, Christian Schlünder, Martina Hommel, Heiko Nielen, Jens Schneider Practical aspects of reliability analysis for IC designs. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF ESD, TDDB of intermetal dielectric, design-in reliability, gate oxide integrity, hot carrier stress, stress-induced voiding, NBTI, electromigration
99Ming-Dou Ker, Chun-Yu Lin 0001, Guo-Xuan Meng ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
99Bo-Shih Huang, Ming-Dou Ker New matching methodology of low-noise amplifier with ESD protection. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
99Rouying Zhan, Haigang Feng, Qiong Wu 0013, Haolu Xie, Xiaokang Guan, Guang Chen, Albert Z. Wang ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
99Natarajan Mahadeva Iyer, M. K. Radhakrishnan ESD Reliability Challenges for RF/Mixed Signal Design & Processing. Search on Bibsonomy VLSI Design The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
99Rouying Zhan, Haigang Feng, Qiong Wu 0013, Guang Chen, Xiaokang Guan, Albert Z. Wang A technology-independent CAD tool for ESD protection device extraction: ESDExtractor. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
99Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang Full chip ESD design rule checking. Search on Bibsonomy ISCAS (5) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
95Charvaka Duvvury ESD: Design For IC Chip Quality and Reliability. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Electrostatic Discharge, ESD design, Machine Model, Charged Device Model, ESD simulations, Human Body Model
87Rouying Zhan, Haigang Feng, Qiong Wu 0013, Xiaokang Guan, Guang Chen, Haolu Xie, Albert Z. Wang Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
85Hsin-Chyh Hsu, Ming-Dou Ker Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
85Rouying Zhan, Haolu Xie, Haigang Feng, Albert Z. Wang ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
85Ming-Dou Ker, Wen-Yi Chen Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
85Sachio Hayashi, Fumihiro Minami, Masaaki Yamada Full-Chip Analysis Method of ESD Protection Network. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
85J. Shorb, Xiaoyong Li 0001, David J. Allstot A resonant pad for ESD protected narrowband CMOS RF applications. Search on Bibsonomy ISCAS (1) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
85Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
83Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Electrostatic discharge (ESD), electrical overstress (EOS), LVTSCR, latch-up, burn-in
71Thorsten Weyl, Dave Clarke 0004, Karl Rinne, James A. Power ESD event simulation automation using automatic extraction of the relevant portion of a full chip. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
71Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Kuo-Feng Yu, Tong-Chern Ong A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
71Kun-Hsien Lin, Ming-Dou Ker ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
71Rouying Zhan, Haigang Feng, Qiong Wu 0013, Haolu Xie, Xiaokang Guan, Guang Chen, Albert Z. Wang ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
71Ming-Dou Ker, Chien-Ming Lee Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits. Search on Bibsonomy ISCAS (1) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
71Haigang Feng, Rouying Zhan, Qiong Wu 0013, Guang Chen, Xiaokang Guan, Haolu Xie, Albert Z. Wang Mixed-mode ESD protection circuit simulation-design methodology. Search on Bibsonomy ISCAS (4) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
71Haigang Feng, Rouying Zhan, Guang Chen, Qiong Wu 0013, Xiaokang Guan, Haolu Xie, Albert Z. Wang Bonding-pad-oriented on-chip ESD protection structures for ICs. Search on Bibsonomy ISCAS (1) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
71Xiaofang Gao, Juin J. Liou, Joe Bernier, Gregg D. Croft, Adelmo Ortiz-Conde Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
71Ming-Dou Ker, Kuo-Chun Hsu On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process. Search on Bibsonomy ISCAS (5) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
71Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Win ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
71Choshu Ito, Kaustav Banerjee, Robert W. Dutton Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications. Search on Bibsonomy ISQED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
71Ming-Dou Ker, Chung-Yu Wu, Tao Cheng, Hun-Hsien Chang Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
70Nidhir Kumar, Senthil N. Velu, Rajan Verma Gateway to Chips: High Speed I/O Signalling and Interface. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
70Javier A. Salcedo, Juin J. Liou, Muhammad Yaqub Afridi, Allen R. Hefner Novel electrostatic discharge protection structure for a monolithic gas sensor systems-on-a-chip. Search on Bibsonomy ISCAS (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
57Yanjie Wang, Anthony Ho, Kris Iniewski, Vincent C. Gaudet Inductive ESD Protection For Narrow Band and Ultra-Wideband CMOS Low Noise Amplifiers. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
57Jingtao Zhou, Mingwei Wang 0001 ESD: The Enterprise Semantic Desktop. Search on Bibsonomy APWeb Workshops The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
57Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Marek Syrzycki Design Strategies for ESD Protection in SOC. Search on Bibsonomy IWSOC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
57V. Chandrasekhar, Kartikeya Mayaram Analysis of CMOS RF LNAs with ESD protection. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
57Ming-Dou Ker, Che-Hao Chuang ESD protection circuits with novel MOS-bounded diode structures. Search on Bibsonomy ISCAS (5) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
57H. Feng, R. Zhan, Q. Wu, G. Chen, X. Guan, A. Z. Wang RC-SCR: a novel low-voltage ESD protection circuit with new triggering mechanism. Search on Bibsonomy APCCAS (2) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
57Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang ESD design rule checker. Search on Bibsonomy ISCAS (5) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
56Naoyuki Shigyo, Hirobumi Kawashima, Seiji Yasuda Design of ESD Protection Device Using Statistical Methods. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF ESD, TCAD, Statistical methods, Hypothesis test, DOE
56Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang Chip-level charged-device modeling and simulation in CMOS integrated circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
56Seth Robertson, Eric V. Siegel, Matthew Miller, Salvatore J. Stolfo Surveillance Detection in High Bandwidth Environments. Search on Bibsonomy DISCEX (1) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
54Mehdi Sagheb-Tehrani Expert systems development: some issues of design process. Search on Bibsonomy ACM SIGSOFT Softw. Eng. Notes The full citation details ... 2005 DBLP  DOI  BibTeX  RDF expert systems (ES), expert systems development (ESD), knowledge engineer (KEN), information technology (IT), design process
46David Alvarez, Michel J. Abou-Khalil, Christian Russ, Kiran V. Chatty, Robert Gauthier 0002, D. Kontos, Junjun Li, Christopher Seguin, Ralph Halbach Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
46Jon Appleton Wendy Carlos: Clockwork Orange, Sonic Seasonings, Tales of Heaven and Hell Compact discs, 1998 (reissues), ESD 81362/81382/81352; available from East Side Digital, 530 North 3rd St., Minneapolis, Minnesota 55401, USA; telephone (612) 375-0233; fax (612) 375-9580; electronic mail esd@noside.com; World Wide Web http: //www.noside.com/esd/wendycarlos.html. Search on Bibsonomy Comput. Music. J. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
46James Harley The Residents: Wormwood: Curious Stories from the Bible Compact disc, 1998, East Side Digital, ESD 81332; available from East Side Digital, 530 North 3rd St., Minneapolis, Minnesota 55401, USA; telephone (612) 375-0233; fax (612) 375-9580; electronic mail esd@noside.com; World Wide Web www.noside.com/esd/. Search on Bibsonomy Comput. Music. J. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
43Pui-In Mak, Ka-Hou Ao Ieong, Rui Paulo Martins An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Linda Hole, Oliver M. Williams The emotion sampling device (ESD). Search on Bibsonomy BCS HCI (2) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF emotion sampling device, mobile devices, experience, interface design, affect, event-based, appraisal
43Markus P. J. Mergens, Geert Wybo, Bart Keppens, Benjamin Van Camp, Frederic De Ranter, Koen G. Verhaege, John Armer, Phillip Jozwiak, Christian C. Russ ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Yuanzhong (Paul) Zhou, Duane Connerney, Ronald Carroll, Timwah Luk Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC Models. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Ming-Dou Ker, Wei-Jen Chang, Wen-Yu Lo Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43R. Zhan, H. Feng, Q. Wu, G. Chen, X. Guan, A. Z. Wang A new algorithm for ESD protection device extraction based on subgraph isomorphism. Search on Bibsonomy APCCAS (2) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
43Joseph C. Bernier, Gregg D. Croft, W. R. Young A process independent ESD design methodology. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
42Xiongfei Meng, Resve A. Saleh, Karim Arabi Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
42Jianxin Pang, Rong Zhang, Lu Lu 0001, Zhengkai Liu Image Quality Assessment Based on Energy of Structural Distortion. Search on Bibsonomy PCM The full citation details ... 2007 DBLP  DOI  BibTeX  RDF structural distortion, inner product, Image quality assessment, image structure
42Xiongfei Meng, Resve A. Saleh, Karim Arabi Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
42Gem Stapleton, John Howse, John Taylor 0001, Simon J. Thompson What Can Spider Diagrams Say? Search on Bibsonomy Diagrams The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
42Ronald Leenes, Jörgen Svensson Size Matters - Electronic Service Delivery by Municipalities? Search on Bibsonomy EGOV The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
42Tung X. Bui, Melvin F. Shakun Introduction to the Negotiation Support System minitrack. Search on Bibsonomy HICSS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
31Sourabh Khandelwal, D. Bavi ASM-ESD - A comprehensive physics-based compact model for ESD Diodes. Search on Bibsonomy IRPS The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
31Jian-Hsing Lee, Yeh-Jen Huang, Li-Yang Hong, Li-Fan Chen, Yeh-Ning Jou, Shin-Cheng Lin, Walter Wohlmuth, Chih-Cherng Liao, Ching-Ho Li, Shoa-Chang Huang, Ke-Horng Chen Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection. Search on Bibsonomy IRPS The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
31Ashish Joglekar, Gaurav Bhandari, Rajesh Sundaresan ESD wrist strap-based EDA sensor cum ESD strap integrity monitor. Search on Bibsonomy IECON The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
31Jian Liu 0027, Divya Acharya, Nathaniel Peachey Triggering Optimization on NAND ESD Clamp and Its ESD Protection IO Scheme for CMOS Designs. Search on Bibsonomy IRPS The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
31Feilong Zhang 0001, Chenkun Wang, Fei Lu 0004, Qi Chen 0008, Cheng Li, X. Shawn Wang, Daguang Li, Albert Z. Wang A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
31Shih-Hung Chen Esd Challenges in Advanced Finfet and Gaa Nanowire cmos Technologies: Designing Diode Based ESD Protection in Advanced State of the Art Technologies. Search on Bibsonomy CICC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
31Horaira Abu, Salem Abdennadher, Benoit Provost, Harry Muljono Augmenting ESD and EOS physical analysis with per pin ESD and leakage DFT. Search on Bibsonomy ISQED The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
31Minoh Son, Changkun Park Cell-Based ESD Diodes with a Zigzag-Shaped Layout to Enhance the ESD Survival Level. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
31Zhixing Lv, Nan Yan, Bingliang Bao Pin-pin ESD protection for electro-explosive device under severe human body ESD. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
31Akram A. Salman, Farzan Farbiz, Ann Concannon, Hal Edwards, Gianluca Boselli Improved inductive-system-level IEC ESD performance for automotive applications using mutual ballasted ESD protection technique. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
31Jian Cao 0002, Zhenxu Ye, Yuan Wang 0001, Guangyi Lu, Xing Zhang 0002 A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network. Search on Bibsonomy ASICON The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
31Nicolas Monnereau, Fabrice Caignet, David Trémouilles, Nicolas Nolhier, Marise Bafleur Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
31Chih-Ting Yeh, Ming-Dou Ker PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
31Lingli Jiang, Hang Fan, Ming Qiao, Bo Zhang 0027, Zhaoji Li ESD characterization of a 190V LIGBT SOI ESD power clamp structure for plasma display panel applications. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
31Ningyuan Yin, Liji Wu, Tengfei Zhai, Xiangmin Zhang, Rui Zhu A novel ESD device for Whole-Chip ESD protection network of TPMS mixed signal SoC. Search on Bibsonomy ASICON The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
31Zitao Shi, Xin Wang 0031, Albert Z. Wang, Yuhua Cheng A 5kV ESD-protected 2.4GHz PA in 180nm RFCMOS optimized by ESD-PA co-design technique. Search on Bibsonomy ASICON The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
31Chih-Ting Yeh, Ming-Dou Ker Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. Search on Bibsonomy VLSI-DAT The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
31Chih-Ting Yeh, Ming-Dou Ker Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
31Tommaso Cilento, M. Schenkel, C. Yun, R. Mishra, Junjun Li, Kiran V. Chatty, Robert Gauthier 0002 Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
31Haipeng Zhang, Liang Zhang, Dejun Wang, Guohua Liu, Mi Lin, Xiaoyan Niu, Lingyan Fan Negative ESD robustness of a novel anti-ESD TGFPTD SOI LDMOS. Search on Bibsonomy APCCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
31Wolfgang Stadler, Tilo Brodbeck, Reinhold Gärtner, Harald Gossner Do ESD fails in systems correlate with IC ESD robustness? Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
31Shih-Hung Chen, Ming-Dou Ker Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
31Ming-Dou Ker, Cheng-Cheng Yen Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Steven Thijs, Mototsugu Okushima, Jonathan Borremans, Philippe Jansen, Dimitri Linten, Mirko Scholz, Piet Wambacq, Guido Groeseneken Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications. Search on Bibsonomy CICC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Shih-Hung Chen, Chih-Ting Yeh Active ESD protection design against cross-power-domain ESD stresses in CMOS integrated circuits. Search on Bibsonomy APCCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Ming-Dou Ker, Wei-Jen Chang Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
31Shih-Hung Chen, Ming-Dou Ker Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
31Ming-Dou Ker, Kun-Hsien Lin ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Steven H. Voldman A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I - ESD. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Yong-Ha Song, Choong-Kyun Kim, Moo-Young Park, Bum-Suk Kye, Jeongil Seo, Dong-Soo Cho, Taek-Soo Kim, Gab-soo Han A study of an abnormal ESD failure mechanism and threshold voltage caused by ESD current zapping sequence. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
29Junjun Li, Sopan Joshi, Ryan Barnes, Elyse Rosenbaum Compact modeling of on-chip ESD protection devices using Verilog-A. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Maurits Ortmanns, N. Unger, André Rocke, Marcus Gehrke, Hans-Jürgen Tiedtke A retina stimulator ASIC with 232 electrodes, custom ESD protection and active charge balancing. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Elyse Rosenbaum, Sami Hyvonen On-chip ESD protection for RF I/Os: devices, circuits and models. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Sebastian Magierowski, Rafal Dlugosz, Adam Dabrowski 3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protection. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
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