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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 809 publication records. Showing 809 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
170 | Ming-Dou Ker, Hun-Hsien Chang, Tung-Yang Chen |
ESD buses for whole-chip ESD protection. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
154 | Ganesh R. Shamnur, Rajesh R. Berigei |
XStatic: A Simulation Based ESD Verification and Debug Environment. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
XStatic, ESD |
141 | Chih-Hung Liu 0001, Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Yao-Wen Chang, Sy-Yen Kuo, Shih-Yi Yuan, Yu-Wei Chen |
An Efficient Graph-Based Algorithm for ESD Current Path Analysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
141 | Harald Gossner |
ESD protection for the deep sub micron regime - a challenge for design methodology. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
127 | Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng |
Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
127 | Ming-Dou Ker, Tung-Yang Chen |
Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
126 | Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu 0001, Yao-Wen Chang, Sy-Yen Kuo |
Current path analysis for electrostatic discharge protection. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
124 | Ming-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo |
ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process. |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
ESD, ESD protection circuit, substrate-triggered technique |
113 | Paul C. F. Tong, Ping-Ping Xu, Wensong Chen, John Hui, Patty Z. Q. Liu |
A novel substrate-triggered ESD protection structure for a bus switch IC with on-chip substrate-pump. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
110 | Thomas Pompl, Christian Schlünder, Martina Hommel, Heiko Nielen, Jens Schneider |
Practical aspects of reliability analysis for IC designs. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
ESD, TDDB of intermetal dielectric, design-in reliability, gate oxide integrity, hot carrier stress, stress-induced voiding, NBTI, electromigration |
99 | Ming-Dou Ker, Chun-Yu Lin 0001, Guo-Xuan Meng |
ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
99 | Bo-Shih Huang, Ming-Dou Ker |
New matching methodology of low-noise amplifier with ESD protection. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
99 | Rouying Zhan, Haigang Feng, Qiong Wu 0013, Haolu Xie, Xiaokang Guan, Guang Chen, Albert Z. Wang |
ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
99 | Natarajan Mahadeva Iyer, M. K. Radhakrishnan |
ESD Reliability Challenges for RF/Mixed Signal Design & Processing. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
99 | Rouying Zhan, Haigang Feng, Qiong Wu 0013, Guang Chen, Xiaokang Guan, Albert Z. Wang |
A technology-independent CAD tool for ESD protection device extraction: ESDExtractor. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
99 | Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang |
Full chip ESD design rule checking. |
ISCAS (5) |
2001 |
DBLP DOI BibTeX RDF |
|
95 | Charvaka Duvvury |
ESD: Design For IC Chip Quality and Reliability. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
Electrostatic Discharge, ESD design, Machine Model, Charged Device Model, ESD simulations, Human Body Model |
87 | Rouying Zhan, Haigang Feng, Qiong Wu 0013, Xiaokang Guan, Guang Chen, Haolu Xie, Albert Z. Wang |
Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
85 | Hsin-Chyh Hsu, Ming-Dou Ker |
Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
85 | Rouying Zhan, Haolu Xie, Haigang Feng, Albert Z. Wang |
ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
85 | Ming-Dou Ker, Wen-Yi Chen |
Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
85 | Sachio Hayashi, Fumihiro Minami, Masaaki Yamada |
Full-Chip Analysis Method of ESD Protection Network. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
85 | J. Shorb, Xiaoyong Li 0001, David J. Allstot |
A resonant pad for ESD protected narrowband CMOS RF applications. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
85 | Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang |
Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
83 | Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev |
Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
Electrostatic discharge (ESD), electrical overstress (EOS), LVTSCR, latch-up, burn-in |
71 | Thorsten Weyl, Dave Clarke 0004, Karl Rinne, James A. Power |
ESD event simulation automation using automatic extraction of the relevant portion of a full chip. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
71 | Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Kuo-Feng Yu, Tong-Chern Ong |
A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
71 | Kun-Hsien Lin, Ming-Dou Ker |
ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
71 | Rouying Zhan, Haigang Feng, Qiong Wu 0013, Haolu Xie, Xiaokang Guan, Guang Chen, Albert Z. Wang |
ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
71 | Ming-Dou Ker, Chien-Ming Lee |
Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
71 | Haigang Feng, Rouying Zhan, Qiong Wu 0013, Guang Chen, Xiaokang Guan, Haolu Xie, Albert Z. Wang |
Mixed-mode ESD protection circuit simulation-design methodology. |
ISCAS (4) |
2003 |
DBLP DOI BibTeX RDF |
|
71 | Haigang Feng, Rouying Zhan, Guang Chen, Qiong Wu 0013, Xiaokang Guan, Haolu Xie, Albert Z. Wang |
Bonding-pad-oriented on-chip ESD protection structures for ICs. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
71 | Xiaofang Gao, Juin J. Liou, Joe Bernier, Gregg D. Croft, Adelmo Ortiz-Conde |
Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
71 | Ming-Dou Ker, Kuo-Chun Hsu |
On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
71 | Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Win |
ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
71 | Choshu Ito, Kaustav Banerjee, Robert W. Dutton |
Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications. |
ISQED |
2001 |
DBLP DOI BibTeX RDF |
|
71 | Ming-Dou Ker, Chung-Yu Wu, Tao Cheng, Hun-Hsien Chang |
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC. |
IEEE Trans. Very Large Scale Integr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
70 | Nidhir Kumar, Senthil N. Velu, Rajan Verma |
Gateway to Chips: High Speed I/O Signalling and Interface. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
70 | Javier A. Salcedo, Juin J. Liou, Muhammad Yaqub Afridi, Allen R. Hefner |
Novel electrostatic discharge protection structure for a monolithic gas sensor systems-on-a-chip. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
57 | Yanjie Wang, Anthony Ho, Kris Iniewski, Vincent C. Gaudet |
Inductive ESD Protection For Narrow Band and Ultra-Wideband CMOS Low Noise Amplifiers. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
57 | Jingtao Zhou, Mingwei Wang 0001 |
ESD: The Enterprise Semantic Desktop. |
APWeb Workshops |
2006 |
DBLP DOI BibTeX RDF |
|
57 | Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Marek Syrzycki |
Design Strategies for ESD Protection in SOC. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
|
57 | V. Chandrasekhar, Kartikeya Mayaram |
Analysis of CMOS RF LNAs with ESD protection. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
57 | Ming-Dou Ker, Che-Hao Chuang |
ESD protection circuits with novel MOS-bounded diode structures. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
57 | H. Feng, R. Zhan, Q. Wu, G. Chen, X. Guan, A. Z. Wang |
RC-SCR: a novel low-voltage ESD protection circuit with new triggering mechanism. |
APCCAS (2) |
2002 |
DBLP DOI BibTeX RDF |
|
57 | Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang |
ESD design rule checker. |
ISCAS (5) |
2001 |
DBLP DOI BibTeX RDF |
|
56 | Naoyuki Shigyo, Hirobumi Kawashima, Seiji Yasuda |
Design of ESD Protection Device Using Statistical Methods. |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
ESD, TCAD, Statistical methods, Hypothesis test, DOE |
56 | Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang |
Chip-level charged-device modeling and simulation in CMOS integrated circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
56 | Seth Robertson, Eric V. Siegel, Matthew Miller, Salvatore J. Stolfo |
Surveillance Detection in High Bandwidth Environments. |
DISCEX (1) |
2003 |
DBLP DOI BibTeX RDF |
|
54 | Mehdi Sagheb-Tehrani |
Expert systems development: some issues of design process. |
ACM SIGSOFT Softw. Eng. Notes |
2005 |
DBLP DOI BibTeX RDF |
expert systems (ES), expert systems development (ESD), knowledge engineer (KEN), information technology (IT), design process |
46 | David Alvarez, Michel J. Abou-Khalil, Christian Russ, Kiran V. Chatty, Robert Gauthier 0002, D. Kontos, Junjun Li, Christopher Seguin, Ralph Halbach |
Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant. |
Microelectron. Reliab. |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Jon Appleton |
Wendy Carlos: Clockwork Orange, Sonic Seasonings, Tales of Heaven and Hell Compact discs, 1998 (reissues), ESD 81362/81382/81352; available from East Side Digital, 530 North 3rd St., Minneapolis, Minnesota 55401, USA; telephone (612) 375-0233; fax (612) 375-9580; electronic mail esd@noside.com; World Wide Web http: //www.noside.com/esd/wendycarlos.html. |
Comput. Music. J. |
2000 |
DBLP DOI BibTeX RDF |
|
46 | James Harley |
The Residents: Wormwood: Curious Stories from the Bible Compact disc, 1998, East Side Digital, ESD 81332; available from East Side Digital, 530 North 3rd St., Minneapolis, Minnesota 55401, USA; telephone (612) 375-0233; fax (612) 375-9580; electronic mail esd@noside.com; World Wide Web www.noside.com/esd/. |
Comput. Music. J. |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Pui-In Mak, Ka-Hou Ao Ieong, Rui Paulo Martins |
An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Linda Hole, Oliver M. Williams |
The emotion sampling device (ESD). |
BCS HCI (2) |
2007 |
DBLP DOI BibTeX RDF |
emotion sampling device, mobile devices, experience, interface design, affect, event-based, appraisal |
43 | Markus P. J. Mergens, Geert Wybo, Bart Keppens, Benjamin Van Camp, Frederic De Ranter, Koen G. Verhaege, John Armer, Phillip Jozwiak, Christian C. Russ |
ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Yuanzhong (Paul) Zhou, Duane Connerney, Ronald Carroll, Timwah Luk |
Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC Models. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Ming-Dou Ker, Wei-Jen Chang, Wen-Yu Lo |
Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
43 | R. Zhan, H. Feng, Q. Wu, G. Chen, X. Guan, A. Z. Wang |
A new algorithm for ESD protection device extraction based on subgraph isomorphism. |
APCCAS (2) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Joseph C. Bernier, Gregg D. Croft, W. R. Young |
A process independent ESD design methodology. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
42 | Xiongfei Meng, Resve A. Saleh, Karim Arabi |
Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
42 | Jianxin Pang, Rong Zhang, Lu Lu 0001, Zhengkai Liu |
Image Quality Assessment Based on Energy of Structural Distortion. |
PCM |
2007 |
DBLP DOI BibTeX RDF |
structural distortion, inner product, Image quality assessment, image structure |
42 | Xiongfei Meng, Resve A. Saleh, Karim Arabi |
Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Gem Stapleton, John Howse, John Taylor 0001, Simon J. Thompson |
What Can Spider Diagrams Say? |
Diagrams |
2004 |
DBLP DOI BibTeX RDF |
|
42 | Ronald Leenes, Jörgen Svensson |
Size Matters - Electronic Service Delivery by Municipalities? |
EGOV |
2002 |
DBLP DOI BibTeX RDF |
|
42 | Tung X. Bui, Melvin F. Shakun |
Introduction to the Negotiation Support System minitrack. |
HICSS |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Sourabh Khandelwal, D. Bavi |
ASM-ESD - A comprehensive physics-based compact model for ESD Diodes. |
IRPS |
2022 |
DBLP DOI BibTeX RDF |
|
31 | Jian-Hsing Lee, Yeh-Jen Huang, Li-Yang Hong, Li-Fan Chen, Yeh-Ning Jou, Shin-Cheng Lin, Walter Wohlmuth, Chih-Cherng Liao, Ching-Ho Li, Shoa-Chang Huang, Ke-Horng Chen |
Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection. |
IRPS |
2022 |
DBLP DOI BibTeX RDF |
|
31 | Ashish Joglekar, Gaurav Bhandari, Rajesh Sundaresan |
ESD wrist strap-based EDA sensor cum ESD strap integrity monitor. |
IECON |
2021 |
DBLP DOI BibTeX RDF |
|
31 | Jian Liu 0027, Divya Acharya, Nathaniel Peachey |
Triggering Optimization on NAND ESD Clamp and Its ESD Protection IO Scheme for CMOS Designs. |
IRPS |
2020 |
DBLP DOI BibTeX RDF |
|
31 | Feilong Zhang 0001, Chenkun Wang, Fei Lu 0004, Qi Chen 0008, Cheng Li, X. Shawn Wang, Daguang Li, Albert Z. Wang |
A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
31 | Shih-Hung Chen |
Esd Challenges in Advanced Finfet and Gaa Nanowire cmos Technologies: Designing Diode Based ESD Protection in Advanced State of the Art Technologies. |
CICC |
2019 |
DBLP DOI BibTeX RDF |
|
31 | Horaira Abu, Salem Abdennadher, Benoit Provost, Harry Muljono |
Augmenting ESD and EOS physical analysis with per pin ESD and leakage DFT. |
ISQED |
2018 |
DBLP DOI BibTeX RDF |
|
31 | Minoh Son, Changkun Park |
Cell-Based ESD Diodes with a Zigzag-Shaped Layout to Enhance the ESD Survival Level. |
J. Circuits Syst. Comput. |
2017 |
DBLP DOI BibTeX RDF |
|
31 | Zhixing Lv, Nan Yan, Bingliang Bao |
Pin-pin ESD protection for electro-explosive device under severe human body ESD. |
Microelectron. Reliab. |
2017 |
DBLP DOI BibTeX RDF |
|
31 | Akram A. Salman, Farzan Farbiz, Ann Concannon, Hal Edwards, Gianluca Boselli |
Improved inductive-system-level IEC ESD performance for automotive applications using mutual ballasted ESD protection technique. |
Microelectron. Reliab. |
2016 |
DBLP DOI BibTeX RDF |
|
31 | Jian Cao 0002, Zhenxu Ye, Yuan Wang 0001, Guangyi Lu, Xing Zhang 0002 |
A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network. |
ASICON |
2015 |
DBLP DOI BibTeX RDF |
|
31 | Nicolas Monnereau, Fabrice Caignet, David Trémouilles, Nicolas Nolhier, Marise Bafleur |
Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation. |
Microelectron. Reliab. |
2013 |
DBLP DOI BibTeX RDF |
|
31 | Chih-Ting Yeh, Ming-Dou Ker |
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit. |
Microelectron. Reliab. |
2013 |
DBLP DOI BibTeX RDF |
|
31 | Lingli Jiang, Hang Fan, Ming Qiao, Bo Zhang 0027, Zhaoji Li |
ESD characterization of a 190V LIGBT SOI ESD power clamp structure for plasma display panel applications. |
Microelectron. Reliab. |
2013 |
DBLP DOI BibTeX RDF |
|
31 | Ningyuan Yin, Liji Wu, Tengfei Zhai, Xiangmin Zhang, Rui Zhu |
A novel ESD device for Whole-Chip ESD protection network of TPMS mixed signal SoC. |
ASICON |
2013 |
DBLP DOI BibTeX RDF |
|
31 | Zitao Shi, Xin Wang 0031, Albert Z. Wang, Yuhua Cheng |
A 5kV ESD-protected 2.4GHz PA in 180nm RFCMOS optimized by ESD-PA co-design technique. |
ASICON |
2013 |
DBLP DOI BibTeX RDF |
|
31 | Chih-Ting Yeh, Ming-Dou Ker |
Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. |
VLSI-DAT |
2013 |
DBLP DOI BibTeX RDF |
|
31 | Chih-Ting Yeh, Ming-Dou Ker |
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection. |
IEEE J. Solid State Circuits |
2010 |
DBLP DOI BibTeX RDF |
|
31 | Tommaso Cilento, M. Schenkel, C. Yun, R. Mishra, Junjun Li, Kiran V. Chatty, Robert Gauthier 0002 |
Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology. |
Microelectron. Reliab. |
2010 |
DBLP DOI BibTeX RDF |
|
31 | Haipeng Zhang, Liang Zhang, Dejun Wang, Guohua Liu, Mi Lin, Xiaoyan Niu, Lingyan Fan |
Negative ESD robustness of a novel anti-ESD TGFPTD SOI LDMOS. |
APCCAS |
2010 |
DBLP DOI BibTeX RDF |
|
31 | Wolfgang Stadler, Tilo Brodbeck, Reinhold Gärtner, Harald Gossner |
Do ESD fails in systems correlate with IC ESD robustness? |
Microelectron. Reliab. |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Shih-Hung Chen, Ming-Dou Ker |
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs. |
IEEE Trans. Circuits Syst. II Express Briefs |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Ming-Dou Ker, Cheng-Cheng Yen |
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test. |
IEEE J. Solid State Circuits |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Steven Thijs, Mototsugu Okushima, Jonathan Borremans, Philippe Jansen, Dimitri Linten, Mirko Scholz, Piet Wambacq, Guido Groeseneken |
Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications. |
CICC |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Shih-Hung Chen, Chih-Ting Yeh |
Active ESD protection design against cross-power-domain ESD stresses in CMOS integrated circuits. |
APCCAS |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Ming-Dou Ker, Wei-Jen Chang |
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology. |
Microelectron. Reliab. |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Shih-Hung Chen, Ming-Dou Ker |
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits. |
Microelectron. Reliab. |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Ming-Dou Ker, Kun-Hsien Lin |
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology. |
IEEE J. Solid State Circuits |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Steven H. Voldman |
A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I - ESD. |
Microelectron. Reliab. |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Yong-Ha Song, Choong-Kyun Kim, Moo-Young Park, Bum-Suk Kye, Jeongil Seo, Dong-Soo Cho, Taek-Soo Kim, Gab-soo Han |
A study of an abnormal ESD failure mechanism and threshold voltage caused by ESD current zapping sequence. |
Microelectron. Reliab. |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Junjun Li, Sopan Joshi, Ryan Barnes, Elyse Rosenbaum |
Compact modeling of on-chip ESD protection devices using Verilog-A. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Maurits Ortmanns, N. Unger, André Rocke, Marcus Gehrke, Hans-Jürgen Tiedtke |
A retina stimulator ASIC with 232 electrodes, custom ESD protection and active charge balancing. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Elyse Rosenbaum, Sami Hyvonen |
On-chip ESD protection for RF I/Os: devices, circuits and models. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Sebastian Magierowski, Rafal Dlugosz, Adam Dabrowski |
3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protection. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
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