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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 353 publication records. Showing 353 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
67 | Jaber A. Abu-Qahouq, Wisam Al-Hoor, Liangbin Yao, Issa Batarseh |
Drive voltage optimization controller to improve efficiency. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
64 | Sol M. Shatz, Khanh Mai, Christopher Black, Shengru Tu |
Design and Implementation of a Petri Net Based Toolkit for Ada Tasking Analysis. |
IEEE Trans. Parallel Distributed Syst. |
1990 |
DBLP DOI BibTeX RDF |
Ada tasking analysis, analysis framework, tasking-oriented toolkit for the Ada language, TOTAL, front-end translator subsystem, FETS, back-end information display subsystem, Ada-net reachability graphs, Petri net, Petri nets, Ada, software tools, query, toolkit, utility, BIDS, Ada tasking |
56 | Kiichi Tachi, Sylvain Barraud, Kuniyuki Kakushima, Hiroshi Iwai, Sorin Cristoloveanu, Thomas Ernst 0005 |
Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs. |
Microelectron. Reliab. |
2011 |
DBLP DOI BibTeX RDF |
|
47 | Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Mohanram |
Graphene tunneling FET and its applications in low-power circuit design. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
graphene nanoribbons, tunneling fets, low-power |
37 | Niharika Thakuria, Atanu K. Saha, Sandeep Krishna Thirumala, Daniel Schulman, Saptarshi Das, Sumeet Kumar Gupta |
Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications. |
DRC |
2020 |
DBLP DOI BibTeX RDF |
|
37 | Shubham Sahay, Mamidala Jagadesh Kumar |
Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs. |
IEEE Access |
2017 |
DBLP DOI BibTeX RDF |
|
37 | Manuel Porcel de Soto, José M. de la Rosa 0001 |
Simulation-based comparison of CNT-FETs and G-FETs from a circuit designer's perspective. |
ISCAS |
2015 |
DBLP DOI BibTeX RDF |
|
35 | Kartik Mohanram, Jing Guo |
Graphene nanoribbon FETs: technology exploration and CAD. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
35 | John A. Chandy, Faquir C. Jain |
Multiple Valued Logic Using 3-State Quantum Dot Gate FETs. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
multiple-valued logic, quantum dots |
35 | Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram |
Technology exploration for graphene nanoribbon FETs. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
graphene nanoribbons, variability, defects |
35 | Guochi Huang, Tae-Sung Kim, Byung-Sung Kim, Mingyan Yu, Yizheng Ye |
Post linearization of CMOS LNA using double cascade FETs. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Arijit Raychowdhury, Kaushik Roy 0001 |
A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs. |
ISMVL |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama |
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. |
ISMVL |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Kaushik Roy 0001, Jaydeep P. Kulkarni, Sumeet Kumar Gupta |
Device/circuit interactions at 22nm technology node. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
22 nm technology node, DG MOSFETs, scaling, SRAM, transistor sizing, FinFETs |
34 | Jia-Jun Wong, Siu-Yeung Cho |
Facial emotion recognition by adaptive processing of tree structures. |
SAC |
2006 |
DBLP DOI BibTeX RDF |
facial emotion tree structures, probabilistic based neural networks, neural networks, tree structures |
34 | John E. Savage |
Computing with Electronic Nanotechnologies. |
CIAC |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Shahid H. Bokhari, Matthew A. Glaser, Harry F. Jordan, Yves Lansac, Jon R. Sauer, Bart Van Zeghbroeck |
Parallelizing a DNA Simulation Code for the Cray MTA-2. |
CSB |
2002 |
DBLP DOI BibTeX RDF |
|
34 | R. Murali, Lihui Wang, Blanca Austin, James D. Meindl |
Low-power circuit advantages of the scaled accumulation FET. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Richard Martel, V. Derycke, Jörg Appenzeller, Shalom J. Wind, Phaedon Avouris |
Carbon nanotube field-effect transistors and logic circuits. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
FET, SWNT, Schottky barrier, field-effect transistor, circuits, carbon nanotube, nanoelectronics, logic gate, inverter, semiconductor |
31 | Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy 0001 |
Analysis of super cut-off transistors for ultralow power digital logic circuits. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
carbon nanotube FETs, tunneling transistors |
19 | M. Balasubbareddy, K. Sivasankaran |
Impact of Device-to-Device Thermal Interference Due to Self-Heating on the Performance of Stacked Nanosheet FETs. |
IEEE Access |
2024 |
DBLP DOI BibTeX RDF |
|
19 | V. Bharath Sreenivasulu, Aruna Kumari Neelam, Asisa Kumar Panigrahy, Lokesh Vakkalakula, Jawar Singh, Shiv Govind Singh |
Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications. |
IEEE Access |
2024 |
DBLP DOI BibTeX RDF |
|
19 | Rinku Rani Das, Rajalekshmi TR, Sruthi Pallathuvalappil, Alex Pappachen James |
FETs for Analog Neural MACs. |
IEEE Access |
2024 |
DBLP DOI BibTeX RDF |
|
19 | Adelcio M. de Souza, Daniel R. Celino, Regiane Ragi, Murilo Araújo Romero |
Analytical Model for Cylindrical Junctionless Nanowire FETs. |
LASCAS |
2024 |
DBLP DOI BibTeX RDF |
|
19 | Om Maheshwari, Dev Vyas, Nihar Ranjan Mohapatra |
K-means Clustering with ANN based Classification to Predict Current-Voltage Characteristics of Advanced FETs. |
VLSID |
2024 |
DBLP DOI BibTeX RDF |
|
19 | Vivek Kumar, Nischal Anand, Rohit Rai, Sneha Chauhan, Jyoti Patel |
Unveiling Thermal Cross Talk in 5nm Gate-All-Around Stacked Nanosheet FETs: A Machine Learning Perspective. |
VLSID |
2024 |
DBLP DOI BibTeX RDF |
|
19 | Sagarika Dash, Yiming Li 0005, Wen-Li Sung |
A Hybrid 1D-CNN-LSTM Technique for WKF-Induced Variability of Multi-Channel GAA NS- and NF-FETs. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Ki Ryung Nam, Kwang Soo Kim, Woo Young Choi |
Electrical Characterization by Counter-Doped Pocket Design in Tunnel FETs. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Jae Won Lim, Changhyun Yoo, Kiron Park, Jongwook Jeon |
Self-Heating and Corner Rounding Effects on Time Dependent Dielectric Breakdown of Stacked Multi-Nanosheet FETs. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Shengzhe Yan, Zhaori Cong, Nianduan Lu, Jinshan Yue, Qing Luo |
Recent progress in InGaZnO FETs for high-density 2T0C DRAM applications. |
Sci. China Inf. Sci. |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Xinhao Li, Huilong Zhu, Zhenzhen Kong, Qi Wang 0041, Yongkui Zhang, Zhenhua Wu |
On the SRAM with comb-shaped nano FETs advancing to 3 nm node and beyond. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Nikolaos Mavredakis, Anibal Pacheco-Sanchez, Wei Wei, Emiliano Pallecchi, Henri Happy, David Jiménez |
Straightforward bias- and frequency-dependent small-signal model extraction for single-layer graphene FETs. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
19 | John Daniel, Zheng Sun, Xuejian Zhang, Yuanqiu Tan, Neil Dilley, Zhihong Chen, Jörg Appenzeller |
Experimental demonstration of an integrated on-chip p-bit core utilizing stochastic Magnetic Tunnel Junctions and 2D-MoS2 FETs. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Moinul Shahidul Haque, Md Moniruzzaman, Seungdeog Choi, Sangshin Kwak, Ahmed H. Okilly, Jeihoon Baek |
A Fast Loss Model for Cascode GaN-FETs and Real-Time Degradation-Sensitive Control of Solid-State Transformers. |
Sensors |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Nicolò Zagni, Francesco Maria Puglisi, Paolo Pavan, Muhammad Ashraful Alam |
Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges. |
Proc. IEEE |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Tamanna Nazeer, Sheikh Aamir Ahsan |
NITSRI-2D: A Surface Potential Based SPICE Compatible Model for pH-Sensitive FETs Based on 2-D Materials. |
ESSDERC |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Utpreksh Patbhaje, Rupali Verma, Jeevesh Kumar, Ansh, Mayank Shrivastava |
Unveiling Field Driven Performance Unreliabilities Governed by Channel Dynamics in MoSe2 FETs. |
IRPS |
2023 |
DBLP DOI BibTeX RDF |
|
19 | L. Panarella, Ben Kaczer, Quentin Smets, Devin Verreck, Tom Schram, Daire Cott, Dennis Lin, Stanislav Tyaginov, I. Asselberghs, Cesar J. Lockhart de la Rosa, Gouri Sankar Kar, Valeri Afanas'ev |
Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs. |
IRPS |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Seongkyung Kim, Hyerim Park, Eunyu Choi, Young Han Kim, Dahyub Kim, Hyewon Shim, Shin-Young Chung, Paul Jung |
Reliability Assessment of 3nm GAA Logic Technology Featuring Multi-Bridge-Channel FETs. |
IRPS |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Mislav Matic, Mirko Poljak |
Transport Properties and Device Performance of Quasi-One-Dimensional MoS2 FETs. |
MIPRO |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Zhuocheng Zhang, Zehao Lin, Chang Niu, Mengwei Si, Muhammad Ashraful Alam, Peide D. Ye |
Ultrahigh Bias Stability of ALD In2O3 FETs Enabled by High Temperature O2 Annealing. |
VLSI Technology and Circuits |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Xiaolin Wang, Zijie Zheng, Qiwen Kong, Leming Jiao, Kaizhen Han, Chen Sun 0010, Zuopu Zhou, Long Liu, Yuye Kang, Gan Liu, Dong Zhang, Xiao Gong |
First Demonstration of BEOL-Compatible MFMIS Fe-FETs with 3D Multi-Fin Floating Gate: In-situ ALD-deposited MFM, LCH of 50 nm, > 2×109 Endurance, and 58.3% Area Saving. |
VLSI Technology and Circuits |
2023 |
DBLP DOI BibTeX RDF |
|
19 | N. Breil, B.-C. Lee, J. Avila Avendano, J. Jewell, M. Vellaikal, E. Newman, E. M. Bazizi, A. Pal, L. Liu, Oleg Gluschenkov, A. Greene, S. Mochizuki, Nicolas Loubet, B. Colombeau, B. Haran |
Contact Cavity Shaping and Selective SiGe: B Low-Temperature Epitaxy Process Solution for sub 10-9 Ω.cm2 Contact Resistivity in Nonplanar FETs. |
VLSI Technology and Circuits |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Jih-Chao Chiu, Eknath Sarkar, Yuan-Ming Liu, Yu-Ciao Chen, Yu-Cheng Fan, C. W. Liu |
First Demonstration of a-IGZO GAA Nanosheet FETs Featuring Achievable SS=61mV/dec, Ioff<10-7 μA/μm, DIBL =44mV/V, Positive VT, and Process Temp. of 300 °C. |
VLSI Technology and Circuits |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Wei-Xiang You, Cheng-Yin Wang, Yih Wang, Tsung-Yung Jonathan Chang, Szuya Sandy Liao |
Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs. |
VLSI Technology and Circuits |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Yi Han, Jingxuan Sun, Jin Hee Bae, Detlev Grützmacher, Joachim Knoch, Qing-Tai Zhao |
High Performance 5 nm Si Nanowire FETs with a Record Small SS = 2.3 mV/dec and High Transconductance at 5.5 K Enabled by Dopant Segregated Silicide Source/Drain. |
VLSI Technology and Circuits |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Shinichi Takagi |
Reservoir computing utilizing ferroelectric-gate-insulator FETs and capacitors. |
ICICDT |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Shinichi Takagi, Kasidit Toprasertpong, Eishin Nako, Zeyu Wang, Rikuo Suzuki, Shin-Yi Min, Mitsuru Takenaka, Ryosho Nakane |
Reservoir Computing Utilizing Ferroelectric-Gate-Insulator FETs and Capacitors. |
ICICDT |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Xiao Yu |
Disturb-Free Operation Scheme and Application for Multilevel Cell Ferroelectric FETs NAND Array. |
ICICDT |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Xinze Li, Yuxuan Wu, Qiao Teng, Ying Sun, Xiao Gong, Guillaume Besnard, Christophe Maleville, Olivier Weber, Rui Zhang, Bing Chen, Dawei Gao, Ran Cheng |
Investigation of Random Telegraph Noise in Advanced Silicon-On-Insulator N-FETs: The Impact of Back Bias, Strain, and Hot Carrier Stress. |
ICICDT |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Ankit Kumar, Arnab Pal, Kamyar Parto, Wei Cao, Kaustav Banerjee |
Exploration and Exploitation of Strain Engineering in 2D-FETs. |
DRC |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi |
Negative capacitance FETs for energy efficient and hardware secure logic designs. |
Microelectron. J. |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Adelcio M. de Souza, Daniel R. Celino, Regiane Ragi, Murilo Araújo Romero |
Fully analytical compact model for the Q-V and C-V characteristics of cylindrical junctionless nanowire FETs. |
Microelectron. J. |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Ajit Kumar, Pramod Kumar Tiwari, J. N. Roy |
Subthreshold model of asymmetric GAA junctionless FETs with scaled equivalent oxide thickness. |
Microelectron. J. |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Yasmine Elogail, Fritz Berkmann, Caterina J. Clausen, Inga A. Fischer, Linda A. Hänel, Daniel Schwarz, Jörg Schulze |
Investigation of Ge-Based P-Channel Planar-Doped Barrier FETs integrated on Si. |
Microelectron. J. |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Daniel Lizzit, David Esseni |
Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Dejin Zhou, Hongliang Lu, Shu Yuan, Ningye He, Yuan Xu, Rengxia Ning, Zhenhai Chen, Wei Huang |
A 20MHz 4A gate driver with 5.5 to 24V output drive voltage for wide bandgap FETs. |
IEICE Electron. Express |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Sanjay Das, Arun Govindankutty, Shan Deng, Kai Ni 0004, Sumitha George |
Adaptable Multi-level Voltage to Binary Converter Using Ferroelectric FETs. |
ISVLSI |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Asifa Amin, Aarti Rathi, Sujit K. Singh, Abhisek Dixit, Oscar Huerta-Gonzalez, P. Srinivasan 0002, Fernando Guarin |
Deep Cryogenic Temperature TDDB in 45-nm PDSOI N-channel FETs for Quantum Computing Applications. |
IRPS |
2022 |
DBLP DOI BibTeX RDF |
|
19 | L. Fursin, P. Losee, Akin Akturk |
Investigation of Terrestrial Neutron Induced Failure Rates in Silicon Carbide JFET Based Cascode FETs. |
IRPS |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Masaharu Kobayashi |
Monolithic 3D Integration of Oxide Semiconductor FETs and Memory Devices for AI Acceleration (Invited). |
IRPS |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Kookjin Lee, Ben Kaczer, Anastasiia Kruv, Mario Gonzalez, Geert Eneman, Oguzhan O. Okudur, Alexander Grill, Jacopo Franco, Andrea Vici, Robin Degraeve, Ingrid De Wolf |
Significant Enhancement of HCD and TDDB in CMOS FETs by Mechanical Stress. |
IRPS |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Michiel Vandemaele, Ben Kaczer, Stanislav Tyaginov, Erik Bury, Adrian Vaisman Chasin, Jacopo Franco, Alexander Makarov, Hans Mertens, Geert Hellings, Guido Groeseneken |
Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs. |
IRPS |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Nilotpal Choudhury, Ayush Ranjan, Souvik Mahapatra |
Decoupling of NBTI and Pure HCD Contributions in p-GAA SNS FETs Under Mixed VG/VD Stress. |
IRPS |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Theresia Knobloch, Yury Yu. Illarionov, Tibor Grasser |
Finding Suitable Gate Insulators for Reliable 2D FETs. |
IRPS |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Vasilis Siomos, Giacomo Tarroni, Jonathan Passerat-Palmbach |
FeTS Challenge 2022 Task 1: Implementing FedMGDA + and a New Partitioning. |
BrainLes@MICCAI (2) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Sadegh Kamaei, Ali Saeidi, Xia Liu, Carlotta Gastaldi, Clara Moldovan, Jürgen Brugger, Adrian M. Ionescu |
Fully integrated Si: HfO2 Negative Capacitance 2D-2D WSe2/SnSe2 Subthermionic Tunnel FETs. |
ESSCIRC |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Zijie Zheng, Chen Sun 0010, Leming Jiao, Dong Zhang, Zuopu Zhou, Xiaolin Wang, Gan Liu, Qiwen Kong, Yue Chen, Kai Ni, Xiao Gong |
Boosting the Memory Window of the BEOL-Compatible MFMIS Ferroelectric/ Anti-Ferroelectric FETs by Charge Injection. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Pai-Ying Liao, Sami Alajlouni, Mengwei Si, Zhuocheng Zhang, Zehao Lin, Jinhyun Noh, Calista Wilk, Ali Shakouri, Peide D. Ye |
Thermal Studies of BEOL-compatible Top-Gated Atomically Thin ALD In2O3 FETs. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Zehao Lin, Mengwei Si, Peide D. Ye |
Ultra-Fast Operation of BEOL-Compatible Atomic-Layer-Deposited In2O3 Fe-FETs: Achieving Memory Performance Enhancement with Memory Window of 2.5 V and High Endurance > 109 Cycles without VT Drift Penalty. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Jingrui Guo, Ying Sun, Lingfei Wang, Xinlv Duan, Kailiang Huang, Zhaogui Wang, Junxiao Feng, Qian Chen, Shijie Huang, Lihua Xu, Di Geng, Guangfan Jiao, Shihui Yin, Zhengbo Wang, Weiliang Jing, Ling Li, Ming Liu |
Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Yiju Zhao, Youngki Yoon, Lan Wei |
A Multi-Level Simulation of GeH FETs: From Nanomaterial and Device Characteristics to Circuit Performance Optimization. |
NANOARCH |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Yannick Raffel, Ricardo Olivo, Maximilian Lederer, Franz Müller 0001, R. Hoffmann, Tarek Ali, Konstantin Mertens, Luca Pirro, Maximilian Drescher, Sven Beyer, Thomas Kämpfe, Konrad Seidel, Lukas M. Eng, J. Heitmann |
Endurance improvements and defect characterization in ferroelectric FETs through interface fluorination. |
IMW |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Reena Elangovan, Ashish Ranjan 0001, Niharika Thakuria, Sumeet Kumar Gupta, Anand Raghunathan |
Energy Efficient Cache Design with Piezoelectric FETs. |
ISLPED |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Venu Birudu, Siva Sankar Yellampalli, Ramesh Vaddi |
Design and Exploration of Negative Capacitance FETs for Energy Efficient SRAM based In-Memory XNOR/Input and Weight Product Operation for Deep Neural Networks. |
iSES |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Aruru Sai Kumar, M. Deekshana, V. Bharath Sreenivasulu, Rajendra Prasad Somineni, D. Kanthi Sudha |
Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs. |
ICCCNT |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Anirban Kar, Swapna Sarker, Avirup Dasgupta, Yogesh Singh Chauhan |
Impact of Corner Rounding on Quantum Confinement in GAA Nanosheet FETs for Advanced Technology Nodes. |
DRC |
2022 |
DBLP DOI BibTeX RDF |
|
19 | L. Panarella, Quentin Smets, Devin Verreck, Tom Schram, Daire Cott, I. Asselberghs, Ben Kaczer |
Analysis of BTI in 300 mm integrated dual-gate WS2 FETs. |
DRC |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Jun-Sik Yoon, Seunghwan Lee, Hyeok Yun, Rock-Hyun Baek |
Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Jinsu Jeong, Jun-Sik Yoon, Rock-Hyun Baek |
Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Mamidala Karthik Ram, Neha Tiwari, Dawit Burusie Abdi, Sneh Saurabh |
Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Saambhavi Baskaran, Jack Sampson |
Evaluation of Tradeoffs in the Design of FPGA Fabrics Using Electrostrictive 2-D FETs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Chandrasekar Lakshumanan, Kumar Prasannajit Pradhan |
Memoryless non-linearity in B-Substitution doped and undoped graphene FETs: A comparative investigation. |
IET Circuits Devices Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Guodong Yin, Yi Cai 0003, Juejian Wu, Zhengyang Duan, Zhenhua Zhu, Yongpan Liu, Yu Wang 0002, Huazhong Yang, Xueqing Li |
Enabling Lower-Power Charge-Domain Nonvolatile In-Memory Computing With Ferroelectric FETs. |
IEEE Trans. Circuits Syst. II Express Briefs |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Mohammad Khaleqi Qaleh Jooq, Mohammad Hossein Moaiyeri, Khalil Tamersit |
Ultra-Compact Ternary Logic Gates Based on Negative Capacitance Carbon Nanotube FETs. |
IEEE Trans. Circuits Syst. II Express Briefs |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Vinay Vashishtha, Lawrence T. Clark |
Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node. |
Microelectron. J. |
2021 |
DBLP DOI BibTeX RDF |
|
19 | V. Bharath Sreenivasulu, Vadthiya Narendar |
Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes. |
Microelectron. J. |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Vandana Devi Wangkheirakpam, Brinda Bhowmick, Puspa Devi Pukhrambam |
Noise behavior of vertical tunnel FETs under the influence of interface trap states. |
Microelectron. J. |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Weixing Huang, Huilong Zhu, Yongkui Zhang, Zhenhua Wu, Kunpeng Jia, Xiaogen Yin, Yangyang Li, Chen Li, Xuezheng Ai, Qiang Huo, Junfeng Li |
Investigation of negative DIBL effect for ferroelectric-based FETs to improve MOSFETs and CMOS circuits. |
Microelectron. J. |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Guodong Yin, Yi Cai 0003, Juejian Wu, Zhengyang Duan, Zhenhua Zhu, Yongpan Liu, Yu Wang 0002, Huazhong Yang, Xueqing Li |
Enabling Lower-Power Charge-Domain Nonvolatile In-Memory Computing with Ferroelectric FETs. |
CoRR |
2021 |
DBLP BibTeX RDF |
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19 | Sarthak Pati, Ujjwal Baid, Maximilian Zenk, Brandon Edwards, Micah J. Sheller, G. Anthony Reina, Patrick Foley, Alexey Gruzdev, Jason Martin, Shadi Albarqouni, Yong Chen, Russell Taki Shinohara, Annika Reinke, David Zimmerer, John B. Freymann, Justin S. Kirby, Christos Davatzikos, Rivka R. Colen, Aikaterini Kotrotsou, Daniel S. Marcus, Mikhail Milchenko, Arash Nazeri, Hassan M. Fathallah-Shaykh, Roland Wiest, András Jakab, Marc-André Weber, Abhishek Mahajan, Lena Maier-Hein, Jens Kleesiek, Bjoern H. Menze, Klaus H. Maier-Hein, Spyridon Bakas |
The Federated Tumor Segmentation (FeTS) Challenge. |
CoRR |
2021 |
DBLP BibTeX RDF |
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19 | David Esseni, Riccardo Fontanini, Daniel Lizzit, Marco Massarotto, Francesco Driussi, Mirko Loghi |
Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies. |
CoRR |
2021 |
DBLP BibTeX RDF |
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19 | Amita Rawat, Krishna K. Bhuwalka, Philippe Matagne, Bjorn Vermeersch, Hao Wu, Geert Hellings, Julien Ryckaert, Changze Liu |
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. |
ESSDERC |
2021 |
DBLP DOI BibTeX RDF |
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19 | Daniel Lizzit, David Esseni |
Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation. |
ESSDERC |
2021 |
DBLP DOI BibTeX RDF |
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19 | P. Srinivasan 0002, Fernando Guarin, Shafi Syed, Joris Angelo Sundaram Jerome, Wen Liu, Sameer H. Jain, Dimitri Lederer, Stephen Moss, Paul Colestock, Anirban Bandyopadhyay, Ned Cahoon, Byoung Min, Martin Gall |
RF Reliability of SOI-based Power Amplifier FETs for mmWave 5G Applications. |
IRPS |
2021 |
DBLP DOI BibTeX RDF |
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19 | Nilotpal Choudhury, Tarun Samadder, Ravi Tiwari, Huimei Zhou, Richard G. Southwick, Miaomiao Wang 0006, Souvik Mahapatra |
Analysis of Sheet Dimension (W, L) Dependence of NBTI in GAA-SNS FETs. |
IRPS |
2021 |
DBLP DOI BibTeX RDF |
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19 | Amita Rawat, Krishna K. Bhuwalka, Philippe Matagne, Bjorn Vermeersch, Hao Wu, Geert Hellings, Julien Ryckaert, Changze Liu |
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. |
ESSCIRC |
2021 |
DBLP DOI BibTeX RDF |
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19 | Yusuke Hatakenaka, Kazuhiro Umetani, Masataka Ishihara, Eiji Hiraki, Hiroshi Tadano |
Parasitic Inductance Design for Preventing Oscillatory False Triggering of Parallel-Connected GaN-FETs. |
IECON |
2021 |
DBLP DOI BibTeX RDF |
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19 | David E. Root, Jianjun Xu, Masaya Iwamoto |
Thermal Resistance Formulation and Analysis of III-V FETs Based on DC Electrical Data. |
BCICTS |
2021 |
DBLP DOI BibTeX RDF |
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19 | Chi-Yo Huang, Ying-Ting Kuo, Liang-Chieh Wang, Yi-Hao Hsiao, Chia-Lee Yang |
Technology Roadmapping for the GAA-FETs Based on the Methods of Patent Mining, Fuzzy Knapsack Problem, and Fuzzy Competence Set Expansion. |
iFUZZY |
2021 |
DBLP DOI BibTeX RDF |
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