Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
89	Vaughn Betz, Jonathan Rose	Automatic generation of FPGA routing architectures from high-level descriptions.	FPGA	2000	DBLP DOI BibTeX RDF
83	Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers	Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
77	Huandong Wang, Xiang Gao, Yunji Chen, Dan Tang, Weiwu Hu	A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	loongson, multi-fpga, fpga, evaluation, verification, emulation
73	Husain Parvez, Zied Marrakchi, Habib Mehrez	Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	asif, fpga, architecture, application specific, cad
69	Nicholas Weaver, John R. Hauser, John Wawrzynek	The SFRA: a corner-turn FPGA architecture.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA CAD, FPGA design study, FPGA optimization, FPGA architecture
68	Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong	Performance benefits of monolithically stacked 3D-FPGA.	FPGA	2006	DBLP DOI BibTeX RDF	3D monolithically stacked, FPGA, performance analysis
68	Ian Kuon, Aaron Egier, Jonathan Rose	Design, layout and verification of an FPGA using automated tools.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
64	Nathaniel Couture, Kenneth B. Kent	Periodic licensing of FPGA based intellectual property.	FPGA	2006	DBLP DOI BibTeX RDF
62	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj	3D configuration caching for 2D FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching
62	Yohei Matsumoto, Hanpei Koike, Akira Masaki	FPGAs with multidimensional mesh topology.	FPGA	2006	DBLP DOI BibTeX RDF
60	Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong 0001, Xu Cheng 0001	FPGA prototyping of an amba-based windows-compatible SoC.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, microsoft windows, amba, x86
58	Fei Li 0003, Deming Chen, Lei He 0001, Jason Cong	Architecture evaluation for power-efficient FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA power model, low power design, FPGA architecture
57	Jianzhong Shi, Akash Randhar, Dinesh Bhatia	Macro Block Based FPGA Floorplanning.	VLSI Design	1997	DBLP DOI BibTeX RDF	macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design
56	Alastair M. Smith, Steven J. E. Wilton, Joydip Das	Wirelength modeling for homogeneous and heterogeneous FPGA architectural development.	FPGA	2009	DBLP DOI BibTeX RDF	fpga modeling, wirelength estimation, fpga, architecture design
56	Yan Lin 0001, Fei Li 0003, Lei He 0001	Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd
56	Yangyang Pan, Tong Zhang 0002	DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dram-based fpga, memory stacking, 3d integration
56	Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh	Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dynamic inspection, reconfigurable microprocessors, fpga
56	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
56	Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003	Intel® atomTM processor core made FPGA-synthesizable.	FPGA	2009	DBLP DOI BibTeX RDF	intel atom, synthesizable core, fpga, emulator
56	Wei Mark Fang, Jonathan Rose	Modeling routing demand for early-stage FPGA architecture development.	FPGA	2008	DBLP DOI BibTeX RDF	model, FPGA, routing, architecture
56	Mingjie Lin, Abbas El Gamal	A routing fabric for monolithically stacked 3D-FPGA.	FPGA	2007	DBLP DOI BibTeX RDF	3D monolithically stacked, FPGA, performance analysis, routing architecture
56	Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy	Power-aware RAM mapping for FPGA embedded memory blocks.	FPGA	2006	DBLP DOI BibTeX RDF	embedded memory block, FPGA, dynamic power
56	Fei Li 0003, Yan Lin 0001, Lei He 0001, Jason Cong	Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, low power, power efficient, dual-Vdd, dual-Vt
53	Jason Cong, Kirill Minkovich	Optimality study of logic synthesis for LUT-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	optimization, logic synthesis, technology mapping, Boolean logic, FPGA lookup table
53	Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers	A quantitative analysis of the speedup factors of FPGAs over processors.	FPGA	2004	DBLP DOI BibTeX RDF	performance, FPGA, analysis, VHDL, reconfigurable computing
52	Lerong Cheng, Yan Lin 0001, Lei He 0001	Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA power model, FPGA architecture
52	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.	FPGA	2009	DBLP DOI BibTeX RDF	eembc, soft, viram, fpga, adaptable, vector, data parallel, processor, simd
52	Liu Ling, Neal Oliver, Bhushan Chitlur, Qigang Wang, Alvin Chen, Wenbo Shen, Zhihong Yu, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Dong Liu, Prabhat Gupta	High-performance, energy-efficient platforms using in-socket FPGA accelerators.	FPGA	2009	DBLP DOI BibTeX RDF	in-socket accelerator, fpga, agility
52	Server Kasap, Khaled Benkrid, Ying Liu 0003	A high performance fpga-based implementation of position specific iterated blast.	FPGA	2009	DBLP DOI BibTeX RDF	psi-blast, fpga, blast, handel c
52	Roto Le, Sherief Reda, R. Iris Bahar	High-performance, cost-effective heterogeneous 3D FPGA architectures.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, heterogeneous, 3d ic, switch box, through silicon via
52	Amin Ansari, Keyvan Amiri	Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trains.	FPGA	2008	DBLP DOI BibTeX RDF	deinterleaver, pulse train, FPGA, parallel architecture
52	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	A novel FPGA logic block for improved arithmetic performance.	FPGA	2008	DBLP DOI BibTeX RDF	6.2 compressor, carry-chain, compressor tree, multi-operand addition, FPGA, arithmetic circuits
52	Haoyu Song 0001, John W. Lockwood	Efficient packet classification for network intrusion detection using FPGA.	FPGA	2005	DBLP DOI BibTeX RDF	BV, tree bitmap, FPGA, reconfigurable hardware, packet classification, TCAM, NIDS
52	Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose	Automatic transistor and physical design of FPGA tiles from an architectural specification.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
52	Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, Russell P. Kraft, John F. McDonald 0001	A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology.	FPGA	2003	DBLP DOI BibTeX RDF	basic cell, FPGA, CML, SiGe
51	Rahul Bhattacharya, Santosh Biswas, Siddhartha Mukhopadhyay	FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	ams testing, concurrent test development, behavioral modeling
51	Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis	A novel methodology for designing high-performance and low-energy FPGA routing architecture.	FPGA	2006	DBLP DOI BibTeX RDF
51	Brian Schoner, John D. Villasenor, Steve Molloy, Rajeev Jain	Techniques for FPGA Implementation of Video Compression Systems.	FPGA	1995	DBLP DOI BibTeX RDF
49	Yee Jern Chong, Sri Parameswaran	Flexible multi-mode embedded floating-point unit for field programmable gate arrays.	FPGA	2009	DBLP DOI BibTeX RDF	dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
49	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Yield enhancements of design-specific FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	design-specific FPGA, interconnect faults, interconnect utilization, yield enhancement, yield prediction, structured ASIC, FPGA interconnect
49	Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang	Computation reuse in domain-specific optimization of signal recognition.	FPGA	2009	DBLP DOI BibTeX RDF	computation reuse, signal recognition, fpga
49	Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai	A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	simulator, FPGA, prototype, multiprocessor, multicore, emulator
49	Tong Liu 0007, Wei-Kang Huang, Fabrizio Lombardi	Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays.	FPGA	1995	DBLP DOI BibTeX RDF	constant testability, FPGA, testing, manufacturing
49	Nathan Woods	Integrating FPGAs in high-performance computing: the architecture and implementation perspective.	FPGA	2007	DBLP DOI BibTeX RDF	compute acceleration, high-performance computinghigh-performance computing, reconfigurable computing, co-processor
49	Michael J. Wirthlin, Misha Burich, Andrew Guyler, Brian Von Herzen	High-level languages: the future or a passing fad?	FPGA	2007	DBLP DOI BibTeX RDF	high-level design languages, RTL design
49	Yujia Jin, William Plishker, Kaushik Ravindran, Nadathur Satish, Kurt Keutzer	Soft multiprocessor systems for network applications (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
49	Deepak Rautela, Rajendra S. Katti	Efficient utilization of heterogeneous routing resources for FPGAs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
48	Sunwoo Kim, Won Woo Ro	FPGA implementation of highly parallelized decoder logic for network coding (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, network coding, fpga implementation, galois field arithmetic
48	Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan	CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA accelerators, c-to-gates, FPGA, high-performance computing, reconfigurable computing
48	Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek	Post-placement C-slow retiming for the xilinx virtex FPGA.	FPGA	2003	DBLP DOI BibTeX RDF	C-slow retiming, FPGA CAD, FPGA optimization, retiming
48	Janette Frigo, Maya B. Gokhale, Dominique Lavenier	Evaluation of the streams-C C-to-FPGA compiler: an applications perspective.	FPGA	2001	DBLP DOI BibTeX RDF	FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler
47	Yi Shan, Bo Wang 0067, Jing Yan, Yu Wang 0002, Ningyi Xu, Huazhong Yang	FPMR: MapReduce framework on FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA framework, RankBoost, MapReduce
47	Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox	FPGA technology mapping with encoded libraries andstaged priority cuts.	FPGA	2009	DBLP DOI BibTeX RDF	priority cuts, fpga, synthesis, technology mapping
47	Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck, Wendy McDougald, Don Dewitt	FPGA-based front-end electronics for positron emission tomography.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, localization, timing, positron emission tomography
47	Bowei Zhang, Guochang Gu, Lin Sun, Yanxia Wu	32-bit floating-point FPGA gaussian elimination.	FPGA	2009	DBLP DOI BibTeX RDF	fpga., floating-point, gaussian elimination
47	Mingjie Lin	The amorphous FPGA architecture.	FPGA	2008	DBLP DOI BibTeX RDF	amorphous, FPGA, architecture, performance analysis
47	Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun	A practical FPGA-based framework for novel CMP research.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA-based emulation, transactional memory, chip multi-processor
47	Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev	64-bit floating-point FPGA matrix multiplication.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, matrix multiplication, floating-point
47	Tom Kean	Cryptographic rights management of FPGA intellectual property cores.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA, cryptography, intellectual property, rights management
47	J. Dido, N. Géraudie, L. Loiseau, O. Payeur, Yvon Savaria, D. Poirier	A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs.	FPGA	2002	DBLP DOI BibTeX RDF	data-path optimization, floating-point/fixed-point conversion, hardware division, hyardware optimization, FPGA, floating-point, video-processing
47	Sunita Chandrasekaran, Shilpa Shanbagh, Douglas L. Maskell	A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpgas, bioinformatics, sequence alignment, data dependency analysis, smith-waterman algorithm
47	Joshua Noseworthy, Miriam Leeser	Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic.	FPGA	2006	DBLP DOI BibTeX RDF
47	Jong-Ru Guo, Chao You, Michael Chu, Robert W. Heikaus, Kuan Zhou, Okan Erdogan, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald 0001	The gigahertz FPGA: design consideration and applications.	FPGA	2004	DBLP DOI BibTeX RDF
47	Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller 0006	Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger.	FPGA	2004	DBLP DOI BibTeX RDF
47	Piyush Kumar Shukla, Sanjay Silakari, Sarita Singh Bhadoria, Anuj Garg	Multi-User FPGA - An Efficient Way of Managing Expensive FPGA Resources Using TCP/IP, Wi-Max/ Wi-Fi in a Secure Network Environment.	ITNG	2008	DBLP DOI BibTeX RDF	Wi-Fi/ Wi-Max, NLOS, FPGA, AES, DES, Camellia, TDM
46	Walid A. Najjar	Compiling code accelerators for FPGAs.	CASES	2007	DBLP DOI BibTeX RDF	FPGA code acceleration
46	Russell Tessier	Incremental Compilation for Logic Emulation.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	virtual wire, scheduling, partitioning, incremental, logic emulation
45	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA redundancy, interconnect faults, fault tolerance, yield enhancement, interconnect model, yield prediction, catastrophic faults, FPGA interconnect
45	Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu	Towards scalable placement for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, convex optimization, quadratic placement, bipartite matching
45	Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani	Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller.	FPGA	2009	DBLP DOI BibTeX RDF	adc, sd card, fpga, real-time, multiplexing, data acquisition, fft
45	Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig	Performance and power of cache-based reconfigurable computing.	FPGA	2009	DBLP DOI BibTeX RDF	c-to-gates, c-to-hardware, co-processor accelerators, fpga, caches
45	Chen Dong 0003, Scott Chilstedt, Deming Chen	FPCNA: a field programmable carbon nanotube array.	FPGA	2009	DBLP DOI BibTeX RDF	cnt-based lut, discretized ssta, variation aware cad, fpga, nanoelectronics
45	Robin Pottathuparambil, Ron Sass	A parallel/vectorized double-precision exponential core to accelerate computational science applications.	FPGA	2009	DBLP DOI BibTeX RDF	exponential core, fpga, cordic
45	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne	Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	field programmable counter array (FPCA), FPGA
45	Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran	When FPGAs are better at floating-point than microprocessors.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, floating-point, arithmetic
45	Andy Gean Ye, Jonathan Rose	Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits.	FPGA	2005	DBLP DOI BibTeX RDF	datapath regularity, reconfigurable fabric, FPGA architecture, routing architecture, area efficiency
45	Randy Huang, John Wawrzynek, André DeHon	Stochastic, spatial routing for hypergraphs, trees, and meshes.	FPGA	2003	DBLP DOI BibTeX RDF	spatial routing, FPGA, reconfigurable computing, detail routing
45	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
45	Abdel Ejnioui, N. Ranganathan	Routing on Switch Matrix Multi-FPGA Systems.	VLSI Design	2000	DBLP DOI BibTeX RDF	switch routing, Field programmable arrays, Multi-FPGA systems, Global routing, FPGA architecture, Interconnection structure
44	Russell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy	Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
44	Ivo Bolsens	Challenges and Opportunities for FPGA Platforms.	FPL	2002	DBLP DOI BibTeX RDF
44	Massoud Pedram, Bahman S. Nobandegani, Bryan Preas	Design and analysis of segmented routing channels for row-based FPGA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
43	Abdel Ejnioui, N. Ranganathan	Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems.	FPGA	1999	DBLP DOI BibTeX RDF	layout synthesis, integer programming, FPGA architecture, interconnect optimization, branch-and-price, FPGA routing
43	Marcus Dutton, David C. Keezer	An architecture for graphics processing in an FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, scalability, architecture, flexibility, gpu
43	Jonathan M. Johnson, Michael J. Wirthlin	Voter insertion algorithms for FPGA designs using triple modular redundancy.	FPGA	2010	DBLP DOI BibTeX RDF	scc, tmr, voter insertion, fpga, algorithm, reliability, synchronization
43	Donglai Dai, Aniruddha S. Vaidya, Roy Saharoy, Seungjoon Park, Dongkook Park, Hariharan L. Thantry, Ralf Plate, Elmar Maas, Akhilesh Kumar, Mani Azimi	FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, routing algorithm, on-chip interconnect, router architecture
43	Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici	Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture.	FPGA	2010	DBLP DOI BibTeX RDF	conjugate gradient (CG), finite-element modeling (FEM), field-programmable gate array (FPGA)
43	Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu 0006, Kirill Minkovich, Bo Yuan, Yi Zou	Accelerating Monte Carlo based SSTA using FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, monte carlo, SSTA
43	Jason Cong, Kirill Minkovich	LUT-based FPGA technology mapping for reliability (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	logic synthesis, error analysis, windowing, technology mapping, don't cares, fpga lookup table
43	Gaurav Mittal, David Zaretsky, Prithviraj Banerjee	Streaming implementation of a sequential decompression algorithm on an FPGA.	FPGA	2009	DBLP DOI BibTeX RDF	fix., fpga, system-on-chip, binary translation, hardware-software co-design, streaming architecture
43	Seunghun Jin, Dongkyun Kim, Thien Cong Pham, Jae Wook Jeon	FPGA implementation of real-time skin color detection with mean-based surface flattening.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, hardware design, skin detection
43	Michalis Vavouras, Kyprianos Papadimitriou, Ioannis Papaefstathiou	Implementation of a genetic algorithm on a virtex-ii pro FPGA.	FPGA	2009	DBLP DOI BibTeX RDF	multiplier blocks, genetic algorithm, fpga, fitness functions
43	Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose	VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, architecture, cad
43	Antonino Tumeo, Christian Pilato, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	HW/SW methodologies for synchronization in FPGA multiprocessors.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, synchronization, multiprocessors
43	Luis Miguel Contreras-Medina, René de Jesús Romero-Troncoso, Jose de Jesus Rangel-Magdaleno, Jesus Roberto Millan-Almaraz	FPGA based multiple-channel vibration analyzer for industrial applications with reconfigurable post-processing capabilities for automatic failure detection on machinery.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, embedded systems, vibration analysis
43	N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung	Measuring and modeling FPGA clock variability.	FPGA	2008	DBLP DOI BibTeX RDF	within-die variability, modeling, FPGA, process variation, clock skew
43	Jason Cong, Wei Jiang	Pattern-based behavior synthesis for FPGA resource reduction.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, pattern, behavior synthesis
43	Jose de Jesus Rangel-Magdaleno, René de Jesús Romero-Troncoso, Luis Miguel Contreras-Medina, Arturo Garcia-Perez	FPGA implementation of a novel algorithm for on-line bar breakage detection on induction motors.	FPGA	2008	DBLP DOI BibTeX RDF	bar breakage, FPGA, embedded systems
43	Kevin Camera, Robert W. Brodersen	An integrated debugging environment for FPGA computing platforms.	FPGA	2008	DBLP DOI BibTeX RDF	simulation, FPGA, design, verification
43	Keith So	Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals.	FPGA	2008	DBLP DOI BibTeX RDF	lexicographic search, negotiated congestion, timing-driven routing, FPGA