Search results for "FPGAs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
66	Sudip K. Nag, Rob A. Rutenbar	Performance-driven simultaneous place and route for island-style FPGAs.	ICCAD	1995	DBLP DOI BibTeX RDF	Xilinx 4000-series FPGAs, island-style FPGAs, performance-driven simultaneous placement/routing, place and route tools, FPGAs, field programmable gate arrays, logic CAD, network routing, circuit layout CAD, industrial designs, circuit layout
61	Jason Cong, Songjie Xu	Performance-driven technology mapping for heterogeneous FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
57	Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins	Compiling and Optimizing Image Processing Algorithms for FPGAs.	CAMP	2000	DBLP DOI BibTeX RDF	SA-C, language features, SA-C algorithms, performance numbers, image processing routines, Annapolis Microsystems WildForce board, Xilinx 4036XL FPGAs, FPGAs, VHDL, optimizing compiler, high-level language, data flow graphs, data flow graphs, image processing algorithms
53	Vinay Verma, Shantanu Dutt, Vishal Suthar	Efficient on-line testing of FPGAs with provable diagnosabilities.	DAC	2004	DBLP DOI BibTeX RDF	built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability
52	Bernard Girau	Digital Hardware Implementation of 2D Compatible Neural Networks.	IJCNN (3)	2000	DBLP DOI BibTeX RDF
49	Toshinori Sueyoshi	Basic Knowledge to Understand FPGAs.	Principles and Structures of FPGAs	2018	DBLP DOI BibTeX RDF
49	Jeffrey B. Goeders, Graham M. Holland, Lesley Shannon, Steven J. E. Wilton	Systems-on-Chip on FPGAs.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
49	Hugo A. Andrade, Stephan Ahrends, Simon Hogg	Making FPGAs Accessible with LabVIEW.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
49	Frank Hannig	A Quick Tour of High-Level Synthesis Solutions for FPGAs.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
48	Yajun Ran, Malgorzata Marek-Sadowska	Crosstalk noise in FPGAs.	DAC	2003	DBLP DOI BibTeX RDF	FPGAs, noise, crosstalk, switch box
47	Chandra Mulpuri, Scott Hauck	Runtime and quality tradeoffs in FPGA placement and routing.	FPGA	2001	DBLP DOI BibTeX RDF	fast CAD for FPGAs, FPGAs, routing, computer-aided design, placement
44	Jason Cong, Hui Huang 0001, Xin Yuan 0005	Technology mapping and architecture evalution for k/m-macrocell-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	FPGA, technology mapping, CPLD, PLD
44	Andrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña	Power Consumption Management on FPGAs.	CONIELECOMP	2005	DBLP DOI BibTeX RDF	Genetic Algorithms, Field Programmable Gate Array, Power Consumption, Partial Reconfiguration, Circuit Design
44	Young-Su Kwon, Bong-Il Park, Chong-Min Kyung	SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture.	ICCD	2003	DBLP DOI BibTeX RDF
44	Jason Cong, Hui Huang 0001, Xin Yuan 0005	Technology mapping for k/m-macrocell based FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
43	Katarzyna Leijten-Nowak, Jef L. van Meerbergen	An FPGA architecture with enhanced datapath functionality.	FPGA	2003	DBLP DOI BibTeX RDF	adder inverting property, application-domain tuning, logic block architectures, FPGAs, DSP, symmetry
42	Steve Trimberger	Security in SRAM FPGAs.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	security, FPGAs, reverse-engineering, encryption, bitstream
42	Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan	Thermal characterization and optimization in platform FPGAs.	ICCAD	2006	DBLP DOI BibTeX RDF	Virtex4, platform FPGAs, thermal floorplan, placement, temperature, thermal
40	Christophe Bobda, Nils Steenbock	A Rapid Prototyping Environment for Distributed Reconfigurable Systems.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
40	Bernard Girau	Building a 2D-Compatible Multilayer Neural Network.	IJCNN (2)	2000	DBLP DOI BibTeX RDF
39	Masahiro Iida	What Is an FPGA?	Principles and Structures of FPGAs	2018	DBLP DOI BibTeX RDF
39	Masahiro Iida	Design Methodology.	Principles and Structures of FPGAs	2018	DBLP DOI BibTeX RDF
39	Tomonori Izumi, Yukio Mitsuyama	Design Flow and Design Tools.	Principles and Structures of FPGAs	2018	DBLP DOI BibTeX RDF
39	Kentaro Sano, Hiroki Nakahara	Hardware Algorithms.	Principles and Structures of FPGAs	2018	DBLP DOI BibTeX RDF
39	Tsutomu Maruyama, Yoshiki Yamaguchi, Yasunori Osana	Programmable Logic Devices (PLDs) in Practical Applications.	Principles and Structures of FPGAs	2018	DBLP DOI BibTeX RDF
39	Motoki Amagasaki, Yuichiro Shibata	FPGA Structure.	Principles and Structures of FPGAs	2018	DBLP DOI BibTeX RDF
39	Masato Motomura, Masanori Hariyama, Minoru Watanabe	Advanced Devices and Architectures.	Principles and Structures of FPGAs	2018	DBLP DOI BibTeX RDF
39	Moritz Schmid, Christian Schmitt 0003, Frank Hannig, Gorker Alp Malazgirt, Nehir Sönmez, Arda Yurdakul, Adrián Cristal	Big Data and HPC Acceleration with Vivado HLS.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
39	Hayden Kwok-Hay So, Cheng Liu	FPGA Overlays.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
39	Deshanand P. Singh, Peter Yiannacouras	OpenCL.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
39	Andreas Agne, Marco Platzner, Christian Plessl, Markus Happe, Enno Lübbers	ReconOS.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
39	Dirk Koch, Daniel Ziener, Frank Hannig	FPGA Versus Software Programming: Why, When, and How?	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
39	João M. P. Cardoso, Markus Weinhardt	High-Level Synthesis.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
39	Walid A. Najjar, Jason R. Villarreal, Robert J. Halstead	ROCCC 2.0.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
39	Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich	HIPAcc.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
39	Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Dean Brown, Jason Helge Anderson	LegUp High-Level Synthesis.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
39	Jason Cong, Muhuan Huang, Peichen Pan, Yuxin Wang, Peng Zhang 0007	Source-to-Source Optimization for HLS.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
39	Kermin Fleming, Michael Adler	The LEAP FPGA Operating System.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
39	Oriol Arcas-Abella, Nehir Sönmez	Bluespec SystemVerilog.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
39	Tobias Becker, Oskar Mencer, Georgi Gaydadjiev	Spatial Programming with OpenSPL.	FPGAs for Software Programmers	2016	DBLP DOI BibTeX RDF
38	David Sheldon, Frank Vahid	Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	BRAM, high-throughput design, pattern counting, redesigning circuit, FPGA, design patterns, stream, memory, ASIC
38	Luca Sterpone, Massimo Violante	A new decompression system for the configuration process of SRAM-based FPGAS.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	configuration mechanisms, compression algorithm, SRAM-based FPGA
38	Owen Callanan, David Gregg, Andy Nisbet, Mike Peardon	High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD.	FPL	2006	DBLP DOI BibTeX RDF
38	Stefan Mohl	Innovative technologies I - Using FPGAs in supercomputers: breaking with reconfigurable computing.	SC	2006	DBLP DOI BibTeX RDF
38	Young-Su Kwon, C.-M. Kyung	ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
38	André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica	What is the right model for programming and using modern FPGAs?	FPGA	2004	DBLP DOI BibTeX RDF
38	Adam Donlin, Patrick Lysaght, Brandon Blodget, Gerd Troeger	A Virtual File System for Dynamically Reconfigurable FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
37	Mark I. Parsons, Francis W. Wray	Programming FPGAs - Programming FPGAs: challenges and successes.	SC	2006	DBLP DOI BibTeX RDF
37	John Marty Emmert, Akash Randhar, Dinesh Bhatia	Fast Floorplanning for FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
37	Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch	A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
36	Jason Lee, Lesley Shannon	Predicting the performance of application-specific NoCs implemented on FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	performance, FPGAs, topologies, heterogeneous, NoCs, homogeneous, application-specific, routability
36	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
36	Quang Dinh, Deming Chen, Martin D. F. Wong	A routing approach to reduce glitches in low power FPGAs.	ISPD	2009	DBLP DOI BibTeX RDF	glitch reduction, path balancing, fpgas, routing, low power
36	Gang Zhou, Harald Michalik, László Hinsenkamp	Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	AES-GCM, pipelined Karatsuba multiplier, FPGAs, finite field arithmetic
36	Stephen Neuendorffer, Kees A. Vissers	Streaming Systems in FPGAs.	SAMOS	2008	DBLP DOI BibTeX RDF	digital convergence, FPGAs, dataflow
36	David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee	Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	scheduling, optimizations, FPGAs, compilers, binary translation, chaining, hardware synthesis
36	Pedro C. Diniz, Joonseok Park	Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures.	FCCM	2003	DBLP DOI BibTeX RDF	Custom Computing, Data search and Data Reorganization Engines, Hardware support for Pointer Operations, Field-Programmable- Gate-Arrays (FPGAs)
36	Marco Platzner, Bernhard Rinner, Reinhold Weiss	A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs.	PDP	1995	DBLP DOI BibTeX RDF	distributed computer architecture, multi-DSP, application-specific computer architecture, constraint-check-function, performance, FPGAs, parallel architectures, computer architecture, digital simulation, hardware design, special purpose computers, design strategies, qualitative simulation
36	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
36	Stanley Habib, Quan Xu	Technology mapping algorithms for sequential circuits using look-up table based FPGAS.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table
34	Balasubramanian Sethuraman	Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip.	FPL	2006	DBLP DOI BibTeX RDF
34	Christophe Bobda, Nils Steenbock	Singular Value Decomposition on Distributed Reconfigurable Systems.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
34	Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray 0002	Reconfigurable PDA for the Visually Impaired Using FPGAs.	ReConFig	2008	DBLP DOI BibTeX RDF	FPGAs, embedded systems, Assistive technology, system on a chip
34	Bin Zhou, David Hwang	Implementations and Optimizations of Pipeline FFTs on Xilinx FPGAs.	ReConFig	2008	DBLP DOI BibTeX RDF	Pipeline FFTs, FPGAs
34	Xiaofang Wang, Swetha Thota	Design and Implementation of a Resource-Efficient Communication Architecture for Multiprocessors on FPGAs.	ReConFig	2008	DBLP DOI BibTeX RDF	FPGAs, multiprocessor, network-on-chip
33	Chen Chen 0018, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Efficient FPGAs using nanoelectromechanical relays.	FPGA	2010	DBLP DOI BibTeX RDF	CMOS-NEM FPGA, nanoelectromechanical relay
33	Laurent Sauvage, Sylvain Guilley, Yves Mathieu	Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	EMA, security, FPGA, DPA, SCA, cartography
33	Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin	Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	scheduling, placement, Reconfigurable computing, leakage, partially dynamical reconfiguration
33	Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau	Measuring and modeling variabilityusing low-cost FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	variability
33	Victor Dumitriu, Dennis Marcantonio, Lev Kirischian	Run-Time Component Relocation in Partially-Reconfigurable FPGAs.	CSE (2)	2009	DBLP DOI BibTeX RDF
33	Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert	Architectural Modifications to Enhance the Floating-Point Performance of FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
33	Nan Guan, Qingxu Deng, Zonghua Gu 0001, Wenyao Xu, Ge Yu 0001	Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	reconfigurable devices, FPGA, Real-time scheduling
33	Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie 0001, Vijaykrishnan Narayanan	Thermal-aware reliability analysis for platform FPGAs.	ICCAD	2008	DBLP DOI BibTeX RDF
33	Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro	Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	reliability, fault tolerant systems, SEU, SRAM-based FPGA
33	Reza M. Rad, Mohammad Tehranipoor	Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	performance, FPGA, reliability, CMOS, Nanotechnology
33	Shilpa Bhoj, Dinesh Bhatia	Thermal Modeling and Temperature Driven Placement for FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
33	Luca Sterpone, Massimo Violante	A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	transient fault injection, FPGA, reliability, place and route
33	Lei Cheng 0001, Martin D. F. Wong	Floorplan Design for Multimillion Gate FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
33	Suresh Srinivasan, Narayanan Vijaykrishnan	Variation Aware Placement for FPGAs.	ISVLSI	2006	DBLP DOI BibTeX RDF
33	François-Xavier Standaert, François Macé, Eric Peeters, Jean-Jacques Quisquater	Updates on the Security of FPGAs Against Power Analysis Attacks.	ARC	2006	DBLP DOI BibTeX RDF
33	Suhap Sahin, Yasar Becerikli, Suleyman Yazici	Neural Network Implementation in Hardware Using FPGAs.	ICONIP (3)	2006	DBLP DOI BibTeX RDF
33	Rajarshi Mukherjee, Seda Ogrenci Memik	Evaluation of dual VDD fabrics for low power FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
33	K. Scott Hemmert, Keith D. Underwood	An Analysis of the Double-Precision Floating-Point FFT on FPGAs.	FCCM	2005	DBLP DOI BibTeX RDF	IEEE floating point, FPGA, FFT, Fast Fourier Transform, reconfigurable computing
33	Thomas J. Wollinger, Jorge Guajardo, Christof Paar	Security on FPGAs: State-of-the-art implementations and attacks.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	cryptographic applications, security, FPGA, Cryptography, reverse engineering, attacks, reconfigurable hardware
33	Paul Kohlbrenner, Kris Gaj	An embedded true random number generator for FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	TRNG, FPGA, random numbers, RNG, cryptographic
33	Mike Hutton	Architecture and CAD for FPGAs.	SBCCI	2004	DBLP DOI BibTeX RDF
33	Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-wook Jang	Energy-efficient signal processing using FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	energy efficient design techniques, matrix multiplicaiton, FPGA, FFT, performance estimation
33	Adrian J. Hilton, Gemma Townson, Jon G. Hall	FPGAs in critical hardware/software systems.	FPGA	2003	DBLP DOI BibTeX RDF
33	Thomas J. Wollinger, Christof Paar	How Secure Are FPGAs in Cryptographic Applications?	FPL	2003	DBLP DOI BibTeX RDF	security, FPGA, cryptography, attacks, reconfigurable hardware
33	Herman Schmit	Extra-dimensional Island-Style FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
33	Charles E. Stroud, Keshia N. Leach, Thomas A. Slaughter	BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study.	ITC	2003	DBLP DOI BibTeX RDF
33	Shantanu Dutt, Vinay Verma, Hasan Arslan	A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Bump-and-refit (B&R) paradigm, ECO (engineering change order), bumping cost, incremental routing, switchbox, field programmable gate arrays, dynamic programming, global routing, detailed routing
33	Channakeshav, Kuan Zhou, Jong-Ru Guo, Chao You, Bryan S. Goda, Russell P. Kraft, John F. McDonald 0001	Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques.	FPL	2002	DBLP DOI BibTeX RDF
33	Bryan S. Goda, Russell P. Kraft, Steven R. Carlough, Thomas W. Krawczyk Jr., John F. McDonald 0001	Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs.	FPL	2001	DBLP DOI BibTeX RDF
33	John Marty Emmert, Jason A. Cheatham	On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router .	DFT	2001	DBLP DOI BibTeX RDF
33	Chi-Feng Wu, Cheng-Wen Wu	Testing Interconnects of Dynamic Reconfigurable FPGAs.	ASP-DAC	1999	DBLP DOI BibTeX RDF
33	Paul S. Graham, Brent E. Nelson	Frequency-Domain Sonar Processing in FPGAs and DSPs.	FCCM	1998	DBLP DOI BibTeX RDF
33	Jason Cong, Songjie Xu	Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
33	Maya B. Gokhale, D. Gomersall	High level compilation for fine grained FPGAs.	FCCM	1997	DBLP DOI BibTeX RDF
32	John Woodfill, Brian Von Herzen	Real-time stereo vision on the PARTS reconfigurable computer.	FCCM	1997	DBLP DOI BibTeX RDF	powerful scalable reconfigurable computer, PARTS engine, real-time stereo vision, Xilinx 4025 FPGAs, partial torus, concurrent SRAM access, standard PCI card, stereo vision algorithm, stereo disparity computation, RISC-equivalent operations, 1 Mbyte, images, SRAMs, stereo image processing, personal computer, workstation, memory access