Search results for "FPRM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
111	Bogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja	Fast Optimization of Fixed-Polarity Reed-Muller Expansions over GF(5).	ISMVL	2004	DBLP DOI BibTeX RDF
102	Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko	Experiments on FPRM Expressions for Partially Symmetric Logic Functions.	ISMVL	2000	DBLP DOI BibTeX RDF	fixed polarity Reed-Muller expression, symmetric functions, MVL functions
89	Lun Li, Mitchell A. Thornton, Marek A. Perkowski	A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form.	ISMVL	2006	DBLP DOI BibTeX RDF
80	Yinshui Xia, B. Ali, A. E. A. Almaini	Area and power optimization of FPRM function based circuits.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
55	Dragan Jankovic, Radomir S. Stankovic	Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multiple-Valued Logic Functions.	ISMVL	2002	DBLP DOI BibTeX RDF	fixed polarity, FPRM, tabular technique, logic synthesis, multi-valued logic
36	Yichen Wang, Lunyao Wang	Power optimization for FPRM logic using approximate computing technique.	ASICON	2019	DBLP DOI BibTeX RDF
36	Mingbo Wang, Pengjun Wang, Qiang Fu, Huihong Zhang	Delay and area optimization for FPRM circuits based on MSPSO algorithm.	ASICON	2017	DBLP DOI BibTeX RDF
36	Apangshu Das, Sambhu Nath Pradhan	Thermal aware FPRM based AND-XOR network synthesis of logic circuits.	ReTIS	2015	DBLP DOI BibTeX RDF
36	Fei Sun, Pengjun Wang, Haizhen Yu	Best polarity searching for ternary FPRM logic circuit area based on whole annealing genetic algorithm.	ASICON	2013	DBLP DOI BibTeX RDF
36	Yinshui Xia, Xunwei Wu, A. E. A. Almaini	Power Minimization of FPRM Functions Based on Polarity Conversion.	J. Comput. Sci. Technol.	2003	DBLP DOI BibTeX RDF
33	Rolf Drechsler, Michael Theobald, Bernd Becker 0001	Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	two-level AND/EXOR forms, FPRM, OFDD, minimization of FPRMs, Logic synthesis
22	Osnat Keren, Ilya Levin, Radomir S. Stankovic	Use of gray decoding for implementation of symmetric functions.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
22	Hafizur Rahaman 0001, Debesh K. Das	Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA.	ASP-DAC	2005	DBLP DOI BibTeX RDF
22	Bogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja	Spectra Generation for Fixed-Polarity Reed-Muller Transform over GF(5).	ISMVL	2004	DBLP DOI BibTeX RDF
22	Dragan Jankovic, Radomir S. Stankovic, Claudio Moraga	Optimization of GF(4) Expressions Using the Extended Dual Polarity Property.	ISMVL	2003	DBLP DOI BibTeX RDF	quaternary function, GF(4) expression, dual polarity, optimization
22	Ugur Kalay, Douglas V. Hall, Marek A. Perkowski	A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	AND-EXOR realizations, Reed-Muller expressions, single stuck-at fault model, easily testable combinational networks, self-testable circuits, Built-in Self-Test (BIST), test pattern generation, Design for Testing (DFT), Universal test set
22	Bogdan J. Falkowski, Chip-Hong Chang	Optimization of partially-mixed-polarity Reed-Muller expansions.	ISCAS (1)	1999	DBLP DOI BibTeX RDF