Search results for "Fault"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
74	Naim Ben-Hamida, Khaled Saab 0001, David Marche, Bozena Kaminska	A perturbation based fault modeling and simulation for mixed-signal circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	analog circuit fault simulation, perturbation fault model, fault abstraction, structural fault modeling, perturbation estimation, fault observation, hierarchical analog fault simulator, complexity, test generation, CMOS, mixed-signal circuits, mixed analogue-digital integrated circuits, functional fault modeling, physical defects
63	Sung-Ming Yen, Sang-Jae Moon, JaeCheol Ha	Hardware Fault Attackon RSA with CRT Revisited.	ICISC	2002	DBLP DOI BibTeX RDF	Computational fault, Memory access fault, Cryptography, Side channel attack, Factorization, Chinese remainder theorem (CRT), Transient fault, Permanent fault, Physical cryptanalysis, Hardware fault cryptanalysis
60	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
58	Sung-Ming Yen, Seungjoo Kim, Seongan Lim, Sang-Jae Moon	RSA Speedup with Residue Number System Immune against Hardware Fault Cryptanalysis.	ICISC	2001	DBLP DOI BibTeX RDF	Fault infective CRT, Fault tolerance, Cryptography, Fault detection, Side channel attack, Factorization, Chinese remainder theorem (CRT), Residue number system, Physical cryptanalysis, Hardware fault cryptanalysis
58	Robert H. Klenke, James H. Aylor, Joseph M. Wolf	An analysis of fault partitioning algorithms for fault partitioned ATPG.	VTS	1996	DBLP DOI BibTeX RDF	fault partitioning algorithm, VLSI device, detected fault broadcasting, preprocessing time, parallel processing, parallel processing, VLSI, fault diagnosis, integrated circuit testing, ATPG, automatic testing, dynamic load balancing, NP complete problem, digital system, test vector generation
58	Hyungill Kim, Sungyoung Lee, Byeong-Soo Jeong	An improved feasible shortest path real-time fault-tolerant scheduling algorithm.	RTCSA	2000	DBLP DOI BibTeX RDF	feasible shortest path real time fault tolerant scheduling algorithm, real time single processor environment, queue based scheduling techniques, feasible shortest path algorithm, linear time heuristics, FSP algorithm, optimal fault tolerant schedules, LTH algorithm, real time scheduling performance, backup scheduling, minimum inter-fault time, primary tasks, fault tolerant schedule, backup schedules, scheduling, fault tolerance, real-time systems, computational complexity, fault tolerant computing, queueing theory, time complexity, timing constraints, system performance, greedy heuristics, time interval, real time computer systems
57	Michael S. Hsiao, Janak H. Patel	A new architectural-level fault simulation using propagation prediction of grouped fault-effects.	ICCD	1995	DBLP DOI BibTeX RDF	architectural-level fault simulation, propagation prediction, grouped fault-effects, fault effects, intelligent propagation prediction, automated behavioral simulation, ALFSIM, Architectural Level Fault Simulation, gate level fault simulation, VLSI, fault diagnosis, circuit analysis computing, stuck at faults, integrated circuit design, deterministic algorithm, data types, symbolic data, architectural level
56	Catherine Stringfellow, Anneliese Amschler Andrews	Deriving a Fault Architecture to Guide Testing.	Softw. Qual. J.	2002	DBLP DOI BibTeX RDF	fault-architecture, software testing, fault-proneness
56	Sumit Ghosh, Tapan J. Chakraborty	On behavior fault modeling for digital designs.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	fault coverage correlation, fault model, fault simulation, stuck-at fault, behavior model
55	Itsuo Takanami, Masaru Sato, Yun Ping Yang	A Fault-Value Injection Approach for Multiple-Weight-Fault Tolerance of MNNs.	IJCNN (3)	2000	DBLP DOI BibTeX RDF	multi-layered neural network, weight fault, fault-tolerance, fault injection
55	John R. Samson Jr., Wilfrido Alejandro Moreno, Fernando J. Falquez	Validating fault tolerant designs using laser fault injection (LFI).	DFT	1997	DBLP DOI BibTeX RDF	fault tolerant designs validation, laser fault injection, VHSIC technology, in situ testing, transient error conditions, VLSI, faults, automated testing, transient, VLSI technology
54	Sudip Chakrabarti, Abhijit Chatterjee	Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal Circuits.	ARVLSI	1999	DBLP DOI BibTeX RDF	fault diagnosis, analog, Design automation, mixed-signal, fault isolation
54	Irith Pomeranz, Sudhakar M. Reddy	Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
52	Tse-Yun Feng, Yanggon Kim	Fault-diagnosis for a class of distributed control multistage interconnection networks.	FTDCS	1995	DBLP DOI BibTeX RDF	distributed control multistage interconnection networks, multiple disjoint paths, input/output terminals, fault-diagnosis method, self-routing tags, fault-location procedure, performance evaluation, fault-tolerance, fault-diagnosis, fault tolerant computing, multistage interconnection networks, fault location, redundant paths
52	Kwang-Ting Cheng	Transition fault testing for sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
52	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	cell fault model (CFM), fault simulation, test pattern generation, stuck-at fault model
50	Zoltán Pap, Gyula Csopaki, Sarolta Dibuz	On FSM-Based Fault Diagnosis.	TestCom	2005	DBLP DOI BibTeX RDF	output fault, transfer fault, fault diagnosis, Finite state machine, fault localization
50	Irith Pomeranz, Sudhakar M. Reddy	Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis.	VLSI Design	2007	DBLP DOI BibTeX RDF
50	Steven Parkes, Prithviraj Banerjee, Janak H. Patel	A parallel algorithm for fault simulation based on PROOFS .	ICCD	1995	DBLP DOI BibTeX RDF	fault partitioning, dynamic partitioning schemes, compute intensive task, integrated circuit design process, rapid design turn around, ProperPROOFS, parallel extension, PROOFS fault simulation package, distributed method, fault redistribution, ISCAS-89 benchmark set, high performance serial fault simulation applications, parallel algorithms, parallel algorithm, parallel architectures, parallel architectures, fault diagnosis, logic testing, sequential circuits, sequential circuits, circuit analysis computing, logic partitioning
49	Yongning Tang, Ehab S. Al-Shaer, Raouf Boutaba	Active integrated fault localization in communication networks.	Integrated Network Management	2005	DBLP DOI BibTeX RDF
48	Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal	Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults.	VTS	2008	DBLP DOI BibTeX RDF	Diagnosis, ATPG, Fault Model, Fault Collapsing, Implication Graph
48	Zbigniew Kalbarczyk, Ravishankar K. Iyer, Gregory L. Ries, Jaqdish U. Patel, Myeong S. Lee, Yuxiao Xiao	Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation.	IEEE Trans. Software Eng.	1999	DBLP DOI BibTeX RDF	Hierarchical simulation, accurate fault modeling, dependability evaluation, fault dictionaries
48	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
47	Pablo F. Castro, T. S. E. Maibaum	Reasoning about System-Degradation and Fault-Recovery with Deontic Logic.	Methods, Models and Tools for Fault Tolerance	2009	DBLP DOI BibTeX RDF	Fault-Tolerance, Formal Specification, Software Design, Deontic Logics
47	Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita	Test sequence compaction for sequential circuits with reset states.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
47	Sung-Ming Yen, Seungjoo Kim, Seongan Lim, Sang-Jae Moon	RSA Speedup with Chinese Remainder Theorem Immune against Hardware Fault Cryptanalysis.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	fault infective CRT, fault tolerance, cryptography, fault detection, side channel attack, factorization, Chinese Remainder Theorem (CRT), residue number system, physical cryptanalysis, hardware fault cryptanalysis, denial of service attack
47	Jie Wu 0001, Dajin Wang	Fault-Tolerant and Deadlock-Free Routing in 2-D Meshes Using Rectilinear-Monotone Polygonal Fault Blocks.	ICPP	2002	DBLP DOI BibTeX RDF	fault tolerance, fault models, virtual channels, Deadlock-free routing, deterministic routing, turn models
47	K. Vijayananda	Distributed fault detection in communication protocols using extended finite state machines.	ICPADS	1996	DBLP DOI BibTeX RDF	distributed fault detection, run-time fault detection, coding defects, memory problems, protocol faults, vocabulary faults, sequencing faults, parallel decomposition method, multiple observers, distributed fault detection mechanism, fault tolerant computing, finite state machines, transport protocols, encoding, communication protocols, fault coverage, extended finite state machines
47	Nabanita Das 0001, Jayasree Dattagupta	A fault location technique and alternate routing in Benes network.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	fault location technique, single switch fault, recirculation, source-destination path, routing technique, exact locations, multiple switch fault detection, one bit test vectors, equivalent fault set, fault diagnosis, fault tolerant computing, reconfiguration, reconfigurable architectures, multistage interconnection networks, multistage interconnection networks, network routing, Benes network, rearrangeable network, alternate routing
46	Hsien-Sheng Hsiao, Yeh-Hao Chin, Wei-Pang Yang	Reaching Fault Diagnosis Agreement under a Hybrid Fault Model.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	fault diagnosis agreement, mixed fault model, Byzantine agreement, fault-tolerant distributed system, hybrid fault model
46	Liting Han, James F. Peters	Rough Neural Fault Classification of Power System Signals.	Trans. Rough Sets	2008	DBLP DOI BibTeX RDF	Power system faults, knowledge-based fault recognition, rough membership, rough neuron, rough neural network, classification, classify fusion
45	Sandeep S. Kulkarni, Ali Ebnenasir	Complexity Issues in Automated Synthesis of Failsafe Fault-Tolerance.	IEEE Trans. Dependable Secur. Comput.	2005	DBLP DOI BibTeX RDF	Fault-tolerance, formal methods, distributed programs, program synthesis, automatic addition of fault-tolerance
45	Hermann Kopetz	On the Fault Hypothesis for a Safety-Critical Real-Time System.	ASWSD	2004	DBLP DOI BibTeX RDF	Fault-Hypothesis, Error-Containment, State Repair, Fault-tolerance, Error Detection, Safety-Critical Systems
45	Klaus Echtle, Irene Eusgeld	A Genetic Algorithm for Fault-Tolerant System Design.	LADC	2003	DBLP DOI BibTeX RDF	analysis of fault-tolerant behaviour, genetic algorithm, Fault tolerance, fault model, fitness function
45	Cristian Constantinescu	Teraflops Supercomputer: Architecture and Validation of the Fault Tolerance Mechanisms.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	fault/error detection coverage, fault-tolerant computing, validation, fault injection, Supercomputing
45	Wilfried Daehn	Fault simulation using small fault samples.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	confidence level, sampling, fault simulation, Bayesian estimation
45	Miaomiao Zhang, Zhiming Liu 0001, Charles Morisset, Anders P. Ravn	Design and Verification of Fault-Tolerant Components.	Methods, Models and Tools for Fault Tolerance	2009	DBLP DOI BibTeX RDF	Fault-tolerance, model checking, abstraction, real-time embedded systems
45	Anders Lyhne Christensen, Rehan O'Grady, Mauro Birattari, Marco Dorigo	Fault detection in autonomous robots based on fault injection and learning.	Auton. Robots	2008	DBLP DOI BibTeX RDF	Model-free, Learning, Mobile robots, Fault detection, Fault injection
45	J.-R. Chang, Kuei-Hu Chang, S.-H. Liao, Ching-Hsue Cheng 0001	The reliability of general vague fault-tree analysis on weapon systems fault diagnosis.	Soft Comput.	2006	DBLP DOI BibTeX RDF	Vague fault tree analysis, Vague fault tree decision support systems (VFTDSS), Reliability analysis, Military application, Vague sets
45	Dajin Wang	A Rectilinear-Monotone Polygonal Fault Block Model for Fault-Tolerant Minimal Routing in Mesh.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	fault tolerance, interconnection network, mesh, fault model, Adaptive routing
44	Ameet Bagwe, Rubin A. Parekhji	Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis
43	Mohamed Kaâniche, Jean-Claude Laprie, Jean-Paul Blanquart	Dependability Engineering of Complex Computing Systems.	ICECCS	2000	DBLP DOI BibTeX RDF	dependability engineering, complex computing systems, development model, system creation process, classical development steps, dependability processes, fault prevention, fault forecasting, supporting processes, system creation activity, fault tolerance, software reliability, certification, quality assurance, dependable systems, checklist, fault removal
43	Sandeep S. Kulkarni, Ali Ebnenasir	Enhancing The Fault-Tolerance of Nonmasking Programs.	ICDCS	2003	DBLP DOI BibTeX RDF	Fault-tolerance, Formal methods, Program transformation, Distributed programs, Program synthesis, Automatic addition of fault-tolerance
42	Anita Borg, Wolfgang Blau, Wolfgang Oberle, Wolfgang Graetsch	Fault Tolerance in Distributed UNIX.	Fault-Tolerant Distributed Computing	1986	DBLP DOI BibTeX RDF
42	Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken	DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF	DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing
42	Shalini Yajnik, Niraj K. Jha	Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	concurrent fault location, fault diagnosis, concurrent error detection, transient faults, graceful degradation, Algorithm-based fault tolerance
42	Hisashi Kondo, Kwang-Ting Cheng	Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG.	ICCAD	1996	DBLP DOI BibTeX RDF	Selective IDDQ, Pseudo Stuck-at Fault, Sequential ATPG, Vector compaction, Test, Fault model, IDDQ, Leakage Fault
42	Michel Renovell, P. Huc, Yves Bertrand	Serial transistor network modeling for bridging fault simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	serial transistor network modeling, voting model, biased voting model, relative transistor strength, SPICE pre-simulation, fault simulation procedure, CMOS logic, fault diagnosis, logic testing, integrated circuit testing, digital simulation, circuit analysis computing, CMOS logic circuits, SPICE, integrated circuit modelling, bridging fault simulation
42	Linas Laibinis, Elena Troubitsyna, Sari Leppänen	Formal Reasoning about Fault Tolerance and Parallelism in Communicating Systems.	Methods, Models and Tools for Fault Tolerance	2009	DBLP DOI BibTeX RDF	fault tolerance, UML, B Method, communicating systems, parallel execution, service-oriented development
42	Andrey Berlizev, Nicolas Guelfi	Fault Tolerance Requirements Analysis Using Deviations in the CORRECT Development Process.	Methods, Models and Tools for Fault Tolerance	2009	DBLP DOI BibTeX RDF	fault-tolerant systems development, Semi-formal methodology, UML, MDE, integrated approaches, deviations
42	Christophe Clavier, Benedikt Gierlichs, Ingrid Verbauwhede	Fault Analysis Study of IDEA.	CT-RSA	2008	DBLP DOI BibTeX RDF	Collision Fault Analysis, Ineffective Fault Analysis, Random Fault Model, IDEA, Differential Fault Analysis
42	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Improving accuracy in path delay fault coverage estimation.	VLSI Design	1996	DBLP DOI BibTeX RDF	fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time
42	Jean Arlat, Martine Aguera, Louis Amat, Yves Crouzet, Jean-Charles Fabre, Jean-Claude Laprie, Eliane Martins, David Powell	Fault Injection for Dependability Validation: A Methodology and Some Applications.	IEEE Trans. Software Eng.	1990	DBLP DOI BibTeX RDF	dependability validation, fault-tolerance mechanisms, hardware/software prototype, validation-directed design process, general pin-level fault injection tool, MESSALINE, centralized computerized interlocking system, railway control applications, dependable communication system, ESPRIT Delta-4 Project, distributed system, fault tolerant computing, distributed processing, software tools, program verification, computer communications software, railways, fault-tolerant computing systems, validation methodology
42	Gabriel M. Silberman, Ilan Y. Spillinger	Using functional fault simulation and the difference fault model to estimate implementation fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
41	Robert Schaefer	Systems of systems and coordinated atomic actions.	ACM SIGSOFT Softw. Eng. Notes	2005	DBLP DOI BibTeX RDF
41	Ravishankar K. Iyer, Zbigniew Kalbarczyk, Mahesh Kalyanakrishnan	Measurement-based Analysis of Networked System Availability.	Performance Evaluation	2000	DBLP DOI BibTeX RDF
41	Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal	Compaction-based test generation using state and fault information.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	compaction-based test generation, newly-traversed state information, newly-detected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation
41	Scott Dawson, Farnam Jahanian, Todd Mitton	Fault injection experiments on real-time protocols using ORCHESTRA.	HASE	1996	DBLP DOI BibTeX RDF	fault injection experiments, ORCHESTRA software fault injection environment, Unix sockets, Real Time Mach, fault injection mechanism, timing intrusiveness, fault tolerance, software fault tolerance, timing behavior, real time protocols, operating system support
41	Salvatore Pontarelli, Gian Carlo Cardarilli, A. Malvoni, Marco Ottavi, Marco Re, Adelio Salsano	System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology.	DFT	2001	DBLP DOI BibTeX RDF	FPSLIC, fault recover, fault tolerance, FPGA, System On Chip, reconfiguration, fault detection
41	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns
41	Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch	Fault modeling and fault equivalence in CMOS technology.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	test generation, Fault modeling, fault collapsing, fault equivalence
41	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	delay fault detectabilities, fault grading, STAFAN, transition observabilities, fanout stems, fanout free region, gate line transition controllabilities, VLSI, fault diagnosis, logic testing, logic testing, statistical analysis, fault coverage, benchmark circuits, statistical estimation
41	Yinong Chen, Klaus Echtle, Winfried Görke	Testing Fault-Tolerant Protocols by Heristic Fault Injection.	Fault-Tolerant Computing Systems	1991	DBLP DOI BibTeX RDF
41	Sandeep S. Kulkarni, Ali Ebnenasir	Automated Synthesis of Multitolerance.	DSN	2004	DBLP DOI BibTeX RDF	Fault-tolerance, Formal methods, Distributed programs, Program synthesis, Automatic addition of fault-tolerance
41	Irith Pomeranz, Sudhakar M. Reddy	A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy.	DATE	2008	DBLP DOI BibTeX RDF
41	Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman	z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
41	Shung-Chih Chen, Jer-Min Jou	Diagnostic fault simulation for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
41	Tein-Hsiang Lin, Kang G. Shin	An Optimal Retry Policy Based on Fault Classification.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	optimal retry policy, fault characteristics, mission lifetime, system status, Bayesian decision problem, prior distributions, fault-related parameter updating, temporal fault type, fault parameter estimation, optimal retry period, mean task completion time minimization, fault tolerant computing, parameter estimation, fault detection, error detection, decision theory, system recovery, Bayes methods, minimisation, error recovery, transient faults, failure analysis, intermittent faults, permanent faults, fault classification
41	Bapiraju Vinnakota, Niraj K. Jha	Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	fault-tolerant multiprocessor systems, algorithm-basedmultiprocessor systems, algorithm-based faulttolerance, low-overhead system-level error detection, fault location scheme, ABFTsystems, design procedure, data element sharing, ABFT system design, reliability, fault diagnosis, fault tolerant computing, multiprocessing systems, fault location, system recovery, concurrent error detection, parallelarchitectures
40	Emmanuel Touloupis, James A. Flint, Vassilios A. Chouliaras, David D. Ward	Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	fault modeling and simulation, fault tolerance, fault injection, soft error, SEU, microprocessor test
40	LingWei Chu, Shihong Zou, Shiduan Cheng, Wendong Wang	Active probing based Internet service fault management in uncertain and noisy environment.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	bipartite Bayesian network, service management, fault management, active probing, binary symmetric channel
40	Kanupriya Gulati, Sunil P. Khatri	Towards acceleration of fault simulation using graphics processing units.	DAC	2008	DBLP DOI BibTeX RDF	graphics processing units, fault simulation
40	Jean Arlat, Alain Costes, Yves Crouzet, Jean-Claude Laprie, David Powell	Fault Injection and Dependability Evaluation of Fault-Tolerant Systems.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	fault tolerance process, fault occurrence process, distributed fault-tolerant architecture, Esprit Delta-4 Project, fault tolerant computing, distributed processing, fault injection, fault-tolerant systems, test sequence, dependability evaluation, dependability measures
40	Sreejit Chakravarty, Yiming Gong	Voting model based diagnosis of bridging faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	MOS logic circuits, voting model based diagnosis, fault list, stuck-at fault dictionary, fault dropping rules, time efficiency, fault diagnosis, logic testing, combinational circuits, combinational circuits, bridging faults, diagnosis algorithm, space efficiency, majority logic, compact data structure
40	Fayçal Bessayah, Ana R. Cavalli, Eliane Martins	A formal approach for specification and verification of fault injection process.	ICIS	2009	DBLP DOI BibTeX RDF	fault specification, formal methods, fault injection, trace analysis, security testing, time specification
40	Shantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger	Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays.	ICCAD	1999	DBLP DOI BibTeX RDF	FPGA defect/fault tolerance, dynamic fault reconfiguration, incremental circuit rerouting, reconfiguration time, track overhead
40	Salvador Mir, Marcelo Lubaszewski, Bernard Courtois	Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	analog ATPG, fault diagnosis, fault-based testing, analog BIST
40	Jan Torben Weinkopf, Klaus Harbich, Erich Barke	Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models.	FPL	2006	DBLP DOI BibTeX RDF
40	Shahrzad Mirkhani, Zainalabedin Navabi	Enhancing Fault Simulation Performance by Dynamic Fault Clustering.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
40	David M. Horan, Richard A. Guinee	A Novel Pulse Echo Correlation Tool for Transmission Path Testing and Fault Finding using Pseudorandom Binary Sequences.	DFT	2005	DBLP DOI BibTeX RDF
40	Irith Pomeranz, Sudhakar M. Reddy	Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Diagnostic fault simulation, diagnostic test generation, fault diagnosis, fault collapsing, fault equivalence, fault dominance
40	Elisabeth Ball, Michael J. Butler	Event-B Patterns for Specifying Fault-Tolerance in Multi-agent Interaction.	Methods, Models and Tools for Fault Tolerance	2009	DBLP DOI BibTeX RDF
39	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
39	Yuanyuan Yang 0001, Jianchao Wang	Fault-Tolerant Rearrangeable Permutation Network.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	losing-contact fault, Fault tolerance, routing, cluster computing, fault model, permutation, switching networks, Clos networks, rearrangeable
39	Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers	Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	static faults, fault models, fault coverage, memory tests, dynamic faults, fault primitives
39	Hailong Cui, Sharad C. Seth, Shashank K. Mehta	Modeling Fault Coverage of Random Test Patterns.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	fault-coverage prediction, cost-benefit analysis of fault simulation, variance of fault coverage, BIST, probabilistic model
39	Sung-Ming Yen, Sang-Jae Moon, JaeCheol Ha	Permanent Fault Attack on the Parameters of RSA with CRT.	ACISP	2003	DBLP DOI BibTeX RDF	Computational fault, Cryptography, Side channel attack, Factorization, Chinese remainder theorem (CRT), Permanent fault, Physical cryptanalysis, Hardware fault cryptanalysis
39	Allen P. Nikora, John C. Munson	The Effects of Fault Counting Methods on Fault Model Quality.	COMPSAC	2004	DBLP DOI BibTeX RDF	defect content estimation techniques, software measurement, software modeling, fault prediction
39	Wee Teck Ng, Peter M. Chen	The Systematic Improvement of Fault Tolerance in the Rio File Cache.	FTCS	1999	DBLP DOI BibTeX RDF	write-back file cache, reliable memory, software fault injection
39	Anish Arora, Sandeep S. Kulkarni	Designing Masking Fault-Tolerance via Nonmasking Fault-Tolerance.	IEEE Trans. Software Eng.	1998	DBLP DOI BibTeX RDF	Masking and nonmasking fault-tolerance, stepwise design formal methods, distributed systems, component based design, detectors, correctors
39	Kam Hong Shum	Fault tolerant cluster computing through replication.	ICPADS	1997	DBLP DOI BibTeX RDF	fault tolerant cluster computing, runtime overhead, fault tolerance schemes, checkpoint states, fault tolerant model, Fujitsu AP3000 multi-processor machine, performance evaluation, replication, workstation clusters, workstation cluster, fault recovery, resource consumption, program termination
39	Minesh B. Amin, Bapiraju Vinnakota	Data parallel fault simulation.	ICCD	1995	DBLP DOI BibTeX RDF	data parallel fault simulation, compute intensive problem, fault simulation time, fault set partitioning technique, low cost parallel resource, logic gate level, parallel programming, fault diagnosis, logic testing, logic CAD, circuit analysis computing, workstations, logic partitioning, multiple processors
39	Marcelo M. de Azevedo, Nader Bagherzadeh, Shahram Latifi	Fault-diameter of the star-connected cycles interconnection network.	HICSS (2)	1995	DBLP DOI BibTeX RDF	star-connected cycles interconnection network, maximum diameter, fault-free, fixed constant, fault tolerance, reliability, graph theory, parallel architectures, fault tolerant computing, graph, multiprocessor interconnection networks, vertex connectivity, fault-diameter
39	Michel Renovell, P. Huc, Yves Bertrand	The concept of resistance interval: a new parametric model for realistic resistive bridging fault.	VTS	1995	DBLP DOI BibTeX RDF	electric resistance, resistance interval, intrinsic resistance, logic behavior, 0 to 500 ohm, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, fault detection, automatic testing, fault coverage, bridging faults, parametric model, logic gates, logic gates, resistive bridging fault, faulty behavior
39	Michael H. Woodbury, Kang G. Shin	Measurement and Analysis of Workload Effects on Fault Latency in Real-Time Systems.	IEEE Trans. Software Eng.	1990	DBLP DOI BibTeX RDF	workload effects, fault latency, control computer systems, multiple latent faults, coverage failure, synthetic work generator, hardware fault injector, NASA Airlab, software engineering, real-time systems, real-time systems, fault tolerant computing, multiprocessing systems, program testing, system recovery, control systems, recovery mechanisms, fault-tolerant multiprocessor
39	Jonathan Ezekiel, Alessio Lomuscio	Combining fault injection and model checking to verify fault tolerance in multi-agent systems.	AAMAS (1)	2009	DBLP BibTeX RDF	fault tolerance, model checking, fault injection, epistemic logic
39	Yue-Shan Chang, Chih-Jen Lo, Ming-Tsung Hsu, Jiun-Hua Huang	Fault Estimation and Fault Map Construction on Cluster-based Wireless Sensor Network.	SUTC (2)	2006	DBLP DOI BibTeX RDF	fault estimation, fault map, wireless Sensor network, Bayesian Belief Network
39	Sung-Ming Yen, Dongryeol Kim, Sang-Jae Moon	Cryptanalysis of Two Protocols for RSA with CRT Based on Fault Infection.	FDTC	2006	DBLP DOI BibTeX RDF	Factorization attack, Fault infective CRT, Cryptography, Chinese remainder theorem (CRT), Residue number system, Hardware fault cryptanalysis
39	Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar	Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments.	DFT	1997	DBLP DOI BibTeX RDF	Alternative Graphs, Malicious Fault List, VHDL, Fault Injection
39	Timothy K. Tsai, Ravishankar K. Iyer	Measuring Fault Tolerance with the FTAPE Fault Injection Tool.	MMB	1995	DBLP DOI BibTeX RDF	fault tolerance measurement, stress-based injection, fault injection, workload generator