Search results for "Fetch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
129	Ayose Falcón, Alex Ramírez, Mateo Valero	A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors.	HPCA	2004	DBLP DOI BibTeX RDF
121	Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson	Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE).	LCTES	2009	DBLP DOI BibTeX RDF	l0/filter cache, lookahead instruction fetch engine (life), tagless hit instruction cache (th-ic)
120	Pierre Michaud, André Seznec, Stéphan Jourdan	Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	instruction-level parallelism, branch prediction, superscalar processors, instruction fetch
103	Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt	Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism.	MICRO	1997	DBLP DOI BibTeX RDF	high bandwidth fetch mechanisms, wide issue machines, inactive issue, speculative execution, trace cache, partial matching
93	Minxuan Zhang, Caixia Sun	Enhancing DCache Warn Fetch Policy for SMT Processors.	ISPA	2005	DBLP DOI BibTeX RDF	L2 cache miss, I-fetch Policy, Fetch Priority, Resource Allocation, SMT
93	Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye	Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings.	MICRO	1996	DBLP DOI BibTeX RDF	TINKER experimental testbed, compressed encodings, compressed instruction encoding, i-fetch hardware, instruction fetch mechanisms, instruction words, multiple instruction issue, silo cache, parallel architectures, trace-driven simulations, instruction cache, VLIW architectures
83	Oliverio J. Santana, Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero	A low-complexity fetch architecture for high-performance superscalar processors.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	fetch architecture, instruction stream, high performance, Branch prediction, low complexity
83	Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas	Optimization of Instruction Fetch for Decision Support Workloads.	ICPP	1999	DBLP DOI BibTeX RDF	High performance fetch, databases, profiling, compiler optimization, trace cache
82	Michele Co, Dee A. B. Weikle, Kevin Skadron	Evaluating trace cache energy efficiency.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	fetch engine energy efficiency, Trace cache
82	Alex Ramírez, Oliverio J. Santana, Josep Lluís Larriba-Pey, Mateo Valero	Fetching instruction streams.	MICRO	2002	DBLP DOI BibTeX RDF	Systems Application Architecture
74	Stijn Eyerman, Lieven Eeckhout	Memory-level parallelism aware fetch policies for simultaneous multithreading processors.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	Fetch Policy, Simultaneous Multithreading (SMT), Memory-Level Parallelism (MLP)
74	Daniel Chaver, Miguel A. Rojas, Luis Piñuel, Manuel Prieto 0001, Francisco Tirado, Michael C. Huang 0001	Energy-aware fetch mechanism: trace cache and BTB customization.	ISLPED	2005	DBLP DOI BibTeX RDF	adaptive, profiling, instruction fetch
74	Caixia Sun, Hong-Wei Tang, Minxuan Zhang	A Fetch Policy Maximizing Throughput and Fairness for Two-Context SMT Processors.	APPT	2005	DBLP DOI BibTeX RDF
74	Osman S. Unsal, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz	Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy Reduction.	Interaction between Compilers and Computer Architectures	2004	DBLP DOI BibTeX RDF
74	Paramjit S. Oberoi, Gurindar S. Sohi	Out-of-Order Instruction Fetch Using Multiple Sequencers.	ICPP	2002	DBLP DOI BibTeX RDF
74	P.-H. Chang, Wen-mei W. Hwu	Forward semantic: a compiler-assisted instruction fetch method for heavily pipelined processors.	MICRO	1989	DBLP DOI BibTeX RDF
73	Oliverio J. Santana, Alex Ramírez, Mateo Valero	Enlarging Instruction Streams.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Superscalar processor design, branch prediction, code optimization, instruction fetch, access latency
73	Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero	Software Trace Cache.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	compiler optimizations, branch prediction, Pipeline processors, trace cache, instruction fetch
66	Aditya Dua, Nicholas Bambos, Jatinder Pal Singh	Performance tradeoffs in mobile computing: to fetch or not to fetch?	MOBIWAC	2007	DBLP DOI BibTeX RDF	mobile computing, dynamic programming, buffer management, tandem queues
65	Robert Yung	Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture.	MICRO	1996	DBLP DOI BibTeX RDF	UltraSPARC, fast cycle time, in-cache prediction, instruction fetch architecture, instruction fetch unit, lower cycle-per-instruction, predictive set-associative cache, prefetch and dispatch unit, trade-off decisions, computer architecture, microprocessor
65	Soner Önder, Jun Xu, Rajiv Gupta 0001	Caching and Predicting Branch Sequences for Improved Fetch Effectiveness.	IEEE PACT	1999	DBLP DOI BibTeX RDF	branch sequence prediction, sequence table, fetch bandwidth, speculative execution
65	Stephen Roderick Hines, Gary S. Tyson, David B. Whalley	Addressing instruction fetch bottlenecks by using an instruction register file.	LCTES	2007	DBLP DOI BibTeX RDF	L0/filter cache, instruction packing, instruction register file
65	Caixia Sun, Hong-Wei Tang, Minxuan Zhang	Controlling Performance of a Time-Criticial Thread in SMT Processors by Instruction Fetch Policy.	PDCAT	2006	DBLP DOI BibTeX RDF
65	Oliverio J. Santana, Alex Ramírez, Mateo Valero	Reducing Fetch Architecture Complexity Using Procedure Inlining.	Interaction between Compilers and Computer Architectures	2004	DBLP DOI BibTeX RDF
65	Juan C. Moure, Dolores Rexachs, Emilio Luque	Optimizing a Decoupled Front-End Architecture: The Indexed Fetch Target Buffer (iFTB).	Euro-Par	2003	DBLP DOI BibTeX RDF
65	Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose	Energy Efficient Co-Adaptive Instruction Fetch and Issue.	ISCA	2003	DBLP DOI BibTeX RDF
65	Gurindar S. Sohi, James E. Smith 0001, James R. Goodman	Restricted Fetch&Phi operations for parallel processing.	ICS	1989	DBLP DOI BibTeX RDF
64	Han-Xin Sun, Kun-Peng Yang, Yulai Zhao 0003, Dong Tong 0001, Xu Cheng 0001	CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	instruction TLB, instruction fetch unit, power-efficient design, computer architecture, dynamic voltage scaling, instruction cache
64	Glenn Reinman, Brad Calder, Todd M. Austin	Optimizations Enabled by a Decoupled Front-End Architecture.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	fetch architectures, branch prediction, Decoupled architectures, instruction prefetching
64	Afzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen	A Mathematical Model of Trace Cache.	ASAP	2002	DBLP DOI BibTeX RDF
57	Osman S. Unsal, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz	Cool-Fetch: Compiler-Enabled Power-Aware Fetch Throttling.	IEEE Comput. Archit. Lett.	2002	DBLP DOI BibTeX RDF	instruction Ievel parallelism, fetch-throttling, Low power design, compiler architecture interaction
56	Eric L. Hill, Mikko H. Lipasti	Stall cycle redistribution in a transparent fetch pipeline.	ISLPED	2006	DBLP DOI BibTeX RDF	pipeline gating, microarchitecture, dynamic power, instruction fetch
56	Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero	Improving Memory Latency Aware Fetch Policies for SMT Processors.	ISHPC	2003	DBLP DOI BibTeX RDF	fetch policy, long latency loads, load miss predictors, multithreading, SMT
56	Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt	Evaluation of Design Options for the Trace Cache Fetch Mechanism.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	High bandwidth fetch mechanisms, wide issue machines, speculative execution, instruction cache, trace cache
56	Emre Özer 0001, Ronald G. Dreslinski, Trevor N. Mudge, Stuart Biles, Krisztián Flautner	Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor.	SAMOS	2008	DBLP DOI BibTeX RDF	Real-time, Energy Efficiency, Caches, Embedded Processors, SMT
56	Stijn Eyerman, Lieven Eeckhout	A Memory-Level Parallelism Aware Fetch Policy for SMT Processors.	HPCA	2007	DBLP DOI BibTeX RDF
56	Bernhard Fechner	A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments.	PARELEC	2006	DBLP DOI BibTeX RDF
56	Juan L. Aragón, Alexander V. Veidenbaum	Energy-Effective Instruction Fetch Unit for Wide Issue Processors.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
56	Juan C. Moure, R. B. García, Dolores Rexachs, Emilio Luque	Improving Single-Thread Fetch Performance on a Multithreaded Processor.	DSD	2001	DBLP DOI BibTeX RDF
56	Carlos Navarro, Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero	On the Performance of Fetch Engines Running DSS Workloads.	Euro-Par	2000	DBLP DOI BibTeX RDF
56	Artur Klauser, Dirk Grunwald	Instruction Fetch Mechanisms for Multipath Execution Processors.	MICRO	1999	DBLP DOI BibTeX RDF
56	Glenn Reinman, Brad Calder, Todd M. Austin	Fetch Directed Instruction Prefetching.	MICRO	1999	DBLP DOI BibTeX RDF
55	Sreeram Duvvuru, Siamak Arya	Evaluation of a branch target address cache.	HICSS (1)	1995	DBLP DOI BibTeX RDF	branch target address cache evaluation, sequential flow, pipeline bubbles, branch penalty, cycles per instruction, multiple instruction issue processors, branch resolution scheme, target instruction fetch, unpredictable branches, fully predicated processor architecture, fetch stage, branch target caching policies, branch target address cache, register-relative branches, performance evaluation, interrupts, interrupt, program compilers, pipeline processing, cache storage, storage allocation, instructions, program control structures, cache sizes
55	Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau	A predictive decode filter cache for reducing power consumption in embedded processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Cache, embedded processors, power optimization
55	Afzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen	Trace Cache Performance Parameters.	ICCD	2002	DBLP DOI BibTeX RDF
51	David M. Martin Jr., Richard M. Smith, Michael Brittain, Ivan Fetch, Hailin Wu	The privacy practices of web browser extensions.	Commun. ACM	2001	DBLP DOI BibTeX RDF
47	Andi Ahmad Dahlan, Toshikazu Nishimura	Implementation of asynchronous predictive fetch to improve the performance of Ajax-enabled web applications.	iiWAS	2008	DBLP DOI BibTeX RDF	predictive fetch, performance, web application, Ajax
47	Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno	Reducing instruction fetch energy with backwards branch control information and buffering.	ISLPED	2003	DBLP DOI BibTeX RDF	loop buffer, low-power, instruction fetch
47	Hans Vandierendonck, André Seznec	Fetch Gating Control through Speculative Instruction Window Weighting.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
47	Nikola Vujic, Marc González 0001, Xavier Martorell, Eduard Ayguadé	Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture.	LCPC	2008	DBLP DOI BibTeX RDF	Cell BE Architecture, Modulo Scheduling, Pre-fetching, Software Cache
47	Hans Vandierendonck, André Seznec	Fetch Gating Control Through Speculative Instruction Window Weighting.	HiPEAC	2007	DBLP DOI BibTeX RDF
47	Chieh-Yih Wan, Andrew T. Campbell, Lakshman Krishnamurthy	Pump-slowly, fetch-quickly (PSFQ): a reliable transport protocol for sensor networks.	IEEE J. Sel. Areas Commun.	2005	DBLP DOI BibTeX RDF
47	Tzung-Rei Yang, Jong-Jiann Shieh	Dynamic Fetch Engine for Simultaneous Multithreaded Processors.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
47	Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir	Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch.	ISVLSI	2003	DBLP DOI BibTeX RDF
47	James H. Anderson, Yong-Jik Kim	Local-spin Mutual Exclusion Using Fetch-and-\phi Primitives.	ICDCS	2003	DBLP DOI BibTeX RDF
47	Heidi Pan, Krste Asanovic	Heads and tails: a variable-length instruction format supporting parallel fetch and decode.	CASES	2001	DBLP DOI BibTeX RDF
47	Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt	Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures.	MICRO	1996	DBLP DOI BibTeX RDF
47	Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel	Optimization of Instruction Fetch Mechanisms for High Issue Rates.	ISCA	1995	DBLP DOI BibTeX RDF
46	Muhammad Shaaban, Edward Mulrane	Improving trace cache hit rates using the sliding window fill mechanism and fill select table.	Memory System Performance	2004	DBLP DOI BibTeX RDF	branch promotion, fetch mechanisms, fill mechanisms, superscalar processors, cache performance, trace cache
38	Reoma Matsuo, Ryota Shioya, Hideki Ando	Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline.	IEEE Comput. Archit. Lett.	2019	DBLP DOI BibTeX RDF
38	Pengfei Wang 0010, Jens Krinke, Kai Lu, Gen Li 0002, Steve Dodier-Lazaro	How Double-Fetch Situations turn into Double-Fetch Vulnerabilities: A Study of Double Fetches in the Linux Kernel.	USENIX Security Symposium	2017	DBLP BibTeX RDF
38	Prithviraj Banerjee, Abhijeet Dugar	The Design, Analysis and Simulation of a Fault-Tolerant Interconnection Network Supporting the Fetch-and-Add Primitive.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	fault-tolerant interconnection network, fetch-and-add primitive, combining multistage interconnection network, 4*4 switches, four independent paths, scheduling, fault tolerant computing, multiprocessor interconnection networks, analytical models, network simulations, omega network
38	Caixia Sun, Hong-Wei Tang, Minxuan Zhang	Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
38	Abdelli Abdelkrim, Nadjib Badache	A semantic based pre-fetch scheme for SMIL presentation proxy-delivery.	MMM	2006	DBLP DOI BibTeX RDF
38	Ayose Falcón, Alex Ramírez, Mateo Valero	Effective Instruction Prefetching via Fetch Prestaging.	IPDPS	2005	DBLP DOI BibTeX RDF
38	Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss	Fetch Halting on Critical Load Misses.	ICCD	2004	DBLP DOI BibTeX RDF
38	Rafael R. dos Santos, Philippe Olivier Alexandre Navaux	Analysing a Multistreamed Superscalar Speculative Fetch Mechanism.	Euro-Par	1998	DBLP DOI BibTeX RDF
38	Freddy Gabbay, Avi Mendelson	The Effect of Instruction Fetch Bandwidth on Value Prediction.	ISCA	1998	DBLP DOI BibTeX RDF
37	Deze Zeng, Minyi Guo, Song Guo 0001, Mianxiong Dong, Hai Jin 0001	The Design and Evaluation of a Selective Way Based Trace Cache.	APPT	2009	DBLP DOI BibTeX RDF	instruction fetch unit design, selective way, energy efficient, computer architecture, trace cache
37	Wangyuan Zhang, Xin Fu, Tao Li 0006, José A. B. Fortes	An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures.	ISPASS	2007	DBLP DOI BibTeX RDF	thread-aware reliability optimization, microarchitecture vulnerability, simultaneous multithreaded architecture, semiconductor transient fault, microprocessor reliability, processor throughput, soft error vulnerability analysis, SPEC CPU 2000 benchmark, microarchitecture structure, microarchitecture reliability profile, fetch policy, thread-level parallelism, multithreading architecture
37	Yehuda Afek, Eran Shalom	Less Is More: Consensus Gaps Between Restricted and Unrestricted Objects.	DISC	2006	DBLP DOI BibTeX RDF	Consensus hierarchy, Common2, Bounded-use, Bounded-size, Long-lived, Fetch&Add, Queues, Stacks, Set, Wait-free, Swap
37	Saurabh Chheda, Osman S. Unsal, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz	Combining compiler and runtime IPC predictions to reduce energy in next generation architectures.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	fetch throttling, low power design, instruction level parallelism, compiler architecture interaction, adaptive voltage scaling
37	Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero	Tolerating Branch Predictor Latency on SMT.	ISHPC	2003	DBLP DOI BibTeX RDF	branch predictor delay, decoupled fetch, predictorpipelining, SMT
37	Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen	eXtended Block Cache.	HPCA	2000	DBLP DOI BibTeX RDF	fetch bandwidth, instruction cache, trace cache, Front-end
37	Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung	Design of Instruction Stream Buffer with Trace Support for X86 Processors.	ICCD	2000	DBLP DOI BibTeX RDF	instruction stream buffer, x86 architecture, multiple instruction fetch, superscalar processor, ILP, Trace cache
37	Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero	DIA: A Complexity-Effective Decoding Architecture.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
37	Chengmo Yang, Alex Orailoglu	Power-efficient instruction delivery through trace reuse.	PACT	2006	DBLP DOI BibTeX RDF	adaptive processor, low-power design, instruction delivery
37	Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero	Branch predictor guided instruction decoding.	PACT	2006	DBLP DOI BibTeX RDF	complexity-effective, instruction decoding, branch predictor
37	Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya	Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures.	ASP-DAC	2004	DBLP DOI BibTeX RDF
37	Hans Vandierendonck, Hans Logie, Koenraad De Bosschere	Trace Substitution.	Euro-Par	2003	DBLP DOI BibTeX RDF
37	P. Krishna Gummadi, Richard J. Dunn, Stefan Saroiu, Steven D. Gribble, Henry M. Levy, John Zahorjan	Measurement, modeling, and analysis of a peer-to-peer file-sharing workload.	SOSP	2003	DBLP DOI BibTeX RDF	multimedia workloads, modeling, peer-to-peer, measurement, Zipf's law
37	Chin-Tser Huang, Mohamed G. Gouda, E. N. Elnozahy	Convergence of IPsec in Presence of Resets.	ICDCS Workshops	2003	DBLP DOI BibTeX RDF
37	Nael B. Abu-Ghazaleh, Philip A. Wilsey	On the Structure of Concurrent Interpreters.	IPDPS	2002	DBLP DOI BibTeX RDF
37	Roni Rosner, Avi Mendelson, Ronny Ronen	Filtering Techniques to Improve Trace-Cache Efficiency.	IEEE PACT	2001	DBLP DOI BibTeX RDF
37	Eric Rotenberg, Steve Bennett, James E. Smith 0001	A Trace Cache Microarchitecture and Evaluation.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	multiple branch prediction, superscalar processors, Instruction cache, trace cache, instruction fetching
37	Simonjit Dutta, Manoj Franklin	Control Flow Prediction Schemes for Wide-Issue Superscalar Processors.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	Block-level prediction, multiple-issue processors, multiple-branch prediction, tree-level prediction, speculative execution, trace cache, instruction-level parallelism (ILP)
37	Glenn Reinman, Todd M. Austin, Brad Calder	A Scalable Front-End Architecture for Fast Instruction Delivery.	ISCA	1999	DBLP DOI BibTeX RDF
37	Sanjay J. Patel, Marius Evers, Yale N. Patt	Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing.	ISCA	1998	DBLP DOI BibTeX RDF
37	Brad Calder, Dirk Grunwald	Next Cache Line and Set Prediction.	ISCA	1995	DBLP DOI BibTeX RDF
28	Marcio Buss, Daniel Brand, Vugranam C. Sreedhar, Stephen A. Edwards	Flexible pointer analysis using assign-fetch graphs.	SAC	2008	DBLP DOI BibTeX RDF	summary-based analysis, static analysis, pointer analysis
28	Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Temporal instruction fetch streaming.	MICRO	2008	DBLP DOI BibTeX RDF
28	Ping Chao, Youn-Long Lin	A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding.	ISCAS	2008	DBLP DOI BibTeX RDF
28	Andrew Robinson, Jim D. Garside	Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	processors, memory bandwidth, power efficiency, registers
28	Michael L. Walters, Kerstin Dautenhahn, Sarah N. Woods, Kheng Lee Koay	Robotic etiquette: results from user studies involving a fetch and carry task.	HRI	2007	DBLP DOI BibTeX RDF	live interactions, human-robot interaction, social robot, personal spaces, user trials, social spaces
28	Prabhu Rajamani, Jatan P. Shah, Vadhiraj Sankaranarayanan, Rama Sangireddy	High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization.	IPCCC	2006	DBLP DOI BibTeX RDF
28	Ziqian Liu, Changjia Chen	Modeling Fetch-at-Most-Once Behavior in Peer-to-Peer File-Sharing Systems.	APWeb Workshops	2006	DBLP DOI BibTeX RDF
28	Stephen Hines, Gary S. Tyson, David B. Whalley	Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows.	MICRO	2005	DBLP DOI BibTeX RDF
28	Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández	DCache Warn: An I-Fetch Policy to Increase SMT Efficiency.	IPDPS	2004	DBLP DOI BibTeX RDF
28	Gregory A. Muthler, David Crowe, Sanjay J. Patel, Steven Lumetta	Instruction fetch deferral using static slack.	MICRO	2002	DBLP DOI BibTeX RDF
28	Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm	Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor.	ISCA	1996	DBLP DOI BibTeX RDF