Search results for "FinFETs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
82	Tamer Cakici, Keejong Kim, Kaushik Roy 0001	FinFET Based SRAM Design for Low Standby Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
62	Abhisek Dixit, Anirban Bandhyopadhyay, Nadine Collaert, Kristin De Meyer, Malgorzata Jurczak	Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack.	VLSI Design	2009	DBLP DOI BibTeX RDF
62	Brian Swahn, Soha Hassoun	METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs.	ISQED	2006	DBLP DOI BibTeX RDF
61	Yiming Li 0005, Chih-Hong Hwang, Shao-Ming Yu	Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors.	International Conference on Computational Science (4)	2007	DBLP DOI BibTeX RDF	computational statistics, SRAM, modeling and simulation, FinFET
42	Romain Ritzenthaler, Elena Capogreco, E. Dupuy, Hiroaki Arimura, J. P. Bastos, P. Favia, F. Sebaai, D. Radisic, V. T. H. Nguyen, G. Mannaert, B. T. Chan, V. Machkaoutsan, Y. Yoon, H. Itokawa, M. Yamaguchi, Y. Chen, Pierre Fazan, S. Subramanian, Alessio Spessot, E. Dentoni Litta, S. Samavedam, Naoto Horiguchi	High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
42	Sushant Mittal, Aneesh Nainani, M. C. Abraham, Saurabh Lodha, Udayan Ganguly	Enhanced Circuit Densities in Epitaxially Defined FinFETs (EDFinFETs) over FinFETs.	CoRR	2016	DBLP BibTeX RDF
41	Anish Muttreja, Niket Agarwal, Niraj K. Jha	CMOS logic design with independent-gate FinFETs.	ICCD	2007	DBLP DOI BibTeX RDF
41	Brian Swahn, Soha Hassoun	Electro-Thermal Analysis of Multi-Fin Devices.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
41	Sherif A. Tawfik, Volkan Kursun	Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations.	ISQED	2008	DBLP DOI BibTeX RDF
36	Kaushik Roy 0001, Jaydeep P. Kulkarni, Sumeet Kumar Gupta	Device/circuit interactions at 22nm technology node.	DAC	2009	DBLP DOI BibTeX RDF	22 nm technology node, DG MOSFETs, scaling, SRAM, transistor sizing, FinFETs
21	Qamar-Ud-Din Memon, Saif-Ur Rehman, Muhammad Adil Bashir, Noor Muhammad Memon, Mohd Anul Haq, Sultan Alharby, Ahmed Alhussen, Ateeq Ur Rehman 0002	An Efficient Technique to Simulate the AC/DC Parameters of Trigate FinFETs.	IEEE Access	2024	DBLP DOI BibTeX RDF
21	Elias de Almeida Ramos, Ricardo Reis 0001	Comparing the Effects of Process Variability in FinFETs and CNFETs.	LASCAS	2024	DBLP DOI BibTeX RDF
21	Ki-Sik Im	Impact of Fin Width on Low-Frequency Noise in AlGaN/GaN FinFETs: Evidence for Bulk Conduction.	IEEE Access	2023	DBLP DOI BibTeX RDF
21	Dhandeep Challagundla, Ignatius Bezzam, Riadul Islam	Design Automation of Series Resonance Clocking in 14-nm FinFETs.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
21	Huifan Zhang, Youliang Jing, Pingqiang Zhou	Machine Learning-Based Device Modeling and Performance Optimization for FinFETs.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
21	Chengxu Wang, Hao Yu, Yichen Wang, Zichong Zhang, Xiangshui Miao, Xingsheng Wang	Modeling and physical mechanism analysis of the effect of a polycrystalline-ferroelectric gate on FE-FinFETs.	Sci. China Inf. Sci.	2023	DBLP DOI BibTeX RDF
21	Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch	Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs.	IEEE Open J. Circuits Syst.	2023	DBLP DOI BibTeX RDF
21	Rashi Chaudhary, Rajesh Saha	Impact of self-heating on RF/analog and linearity parameters of DMG FinFETs in underlap and overlap configurations.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
21	Po-Chih Chen, Yi-Ting Wu, Meng-Hsueh Chiang	Performance Comparison of SRAM Designs Implemented with Silicon-On-Insulator Nanosheet Transistors and Bulk FinFETs.	ESSDERC	2023	DBLP DOI BibTeX RDF
21	Yiming Qu, Chu Yan, Xinwei Yu, Yaru Ding, Yi Zhao	GHz Cycle-to-Cycle Variation in Ultra-scaled FinFETs: From the Time-Zero to the Aging States.	IRPS	2023	DBLP DOI BibTeX RDF
21	Zuoyuan Dong, Zixuan Sun, Xin Yang, Xiaomei Li, Yongkang Xue, Chen Luo, Puyang Cai, Zirui Wang, Shuying Wang, Yewei Zhang, Chaolun Wang, Pengpeng Ren, Zhigang Ji, Xing Wu 0005, Runsheng Wang, Ru Huang	Catching the Missing EM Consequence in Soft Breakdown Reliability in Advanced FinFETs: Impacts of Self-heating, On-State TDDB, and Layout Dependence.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
21	Y. Kikuchi, M. Tomita, T. Hayashi, H. Chiba, T. Ogita, T. Okawa, K. Nishida, M. Sugimoto, D. Yoneyama, T. Umeki, H. Oishi, S. Miyake, K. Hiramatsu, H. Kumano, H. Kawashima, N. Yamada, M. Tamura, H. Ohnuma, K. Tatani	Noise Performance Improvements of 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Non-doped Pixel-FinFETs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
21	Jing-Yuan Wu, Mu-Yu Chen, Edward. Yi Chang	Inversion-Mode InGaAs FinFETs for Logic and RF Applications.	ASICON	2023	DBLP DOI BibTeX RDF
21	Jianwen Lin, Linlin Cai, Yutao Chen, Haoyu Zhang, Wangyong Chen	Machine Learning-Assisted Single-Event Transient Model of 12nm FinFETs for Circuit-Level Simulation.	ASICON	2023	DBLP DOI BibTeX RDF
21	Zhongjie Ren, Hsien-Chih Huang, Hanwool Lee, Clarence Chan, Henry C. Roberts, Xihang Wu, Aadil Wassem, Wenjuan Zhu, Xiuling Li	$\beta$-Ga2O3 FinFETs by MacEtch: temperature dependent I-V characteristics.	DRC	2023	DBLP DOI BibTeX RDF
21	Vibhu, Sparsh Mittal, Vivek Kumar	Machine Learning-based model for Single Event Upset Current Prediction in 14nm FinFETs.	VLSID	2023	DBLP DOI BibTeX RDF
21	Antonio Calomarde, Salvador Manich, Antonio Rubio 0001, Francisco Gámiz	Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact.	IEEE Access	2022	DBLP DOI BibTeX RDF
21	Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Y. Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi	Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
21	Rajat Butola, Yiming Li 0005, Sekhar Reddy Kola	Machine Learning Approach to Characteristic Fluctuation of Bulk FinFETs Induced by Random Interface Traps.	ISQED	2022	DBLP DOI BibTeX RDF
21	Surila Guglani, Avirup Dasgupta, Ming-Yen Kao, Chenming Hu, Sourajeet Roy	Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs.	DRC	2022	DBLP DOI BibTeX RDF
21	Shivendra Singh Parihar, Jun Z. Huang, Weike Wang, Kimihiko Imura, Yogesh Singh Chauhan	Self-Heating characterization and modeling of 5nm technology node FinFETs.	DRC	2022	DBLP DOI BibTeX RDF
21	Qamar D. Memon, Umer F. Ahmed, Muhammad Mansoor Ahmed	A Unified Depletion/Inversion Model for Heterojunction Trigate FinFETs DC Characteristics.	IEEE Access	2021	DBLP DOI BibTeX RDF
21	Huan Liu, Genquan Han, Jiuren Zhou, Yan Liu, Yue Hao	High mobility germanium-on-insulator p-channel FinFETs.	Sci. China Inf. Sci.	2021	DBLP DOI BibTeX RDF
21	Ravi Goel, Weike Wang, Yogesh Singh Chauhan	Improved modeling of flicker noise including velocity saturation effect in FinFETs and experimental validation.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
21	Câncio Monteiro, Yasuhiro Takahashi	Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices.	Sensors	2021	DBLP DOI BibTeX RDF
21	Jesús A. del Alamo, Xiaowei Cai, Xin Zhao, Alon Vardi, Jesús Grajal	Nanoscale InGaAs FinFETs: Band-to-Band Tunneling and Ballistic Transport.	ESSDERC	2021	DBLP DOI BibTeX RDF
21	Sachin Bhat, Mingyu Li, Sounak Shaun Ghosh, Sourabh Kulkarni, Csaba Andras Moritz	SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs beyond FinFETs.	ISVLSI	2021	DBLP DOI BibTeX RDF
21	Longda Zhou, Zhaohao Zhang, Hong Yang, Zhigang Ji, Qianqian Liu, Qingzhu Zhang, Eddy Simoen, Huaxiang Yin, Jun Luo, Anyan Du, Chao Zhao, Wenwu Wang 0006	A Fast DCIV Technique for Characterizing the Generation and Repassivation of Interface Traps Under DC/ AC NBTI Stress/Recovery Condition in Si p-FinFETs.	IRPS	2021	DBLP DOI BibTeX RDF
21	Hao Chang, Longda Zhou, Hong Yang, Zhigang Ji, Qianqian Liu, Eddy Simoen, Huaxiang Yin, Wenwu Wang 0006	Comparative Study on the Energy Distribution of Defects under HCD and NBTI in Short Channel p-FinFETs.	IRPS	2021	DBLP DOI BibTeX RDF
21	Dawei Wang, Tao Liu, Xin Sun, Kun Chen, Jingwen Yang, Chunlei Wu, Min Xu, David Wei Zhang	Channel Stress Engineering Through Source/Drain Recess Optimization and Its Process Variation Study for 5 nm-node FinFETs.	ASICON	2021	DBLP DOI BibTeX RDF
21	Joshua A. Perozek, Ahmad Zubair, Tomás Palacios	Small-Signal, High Frequency Performance of Vertical GaN FinFETs with fmax = 5.9 GHz.	DRC	2021	DBLP DOI BibTeX RDF
21	Jun-Sik Yoon, Rock-Hyun Baek	Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications.	IEEE Access	2020	DBLP DOI BibTeX RDF
21	Antonio Calomarde, Antonio Rubio 0001, Francesc Moll, Francisco Gámiz	Active Radiation-Hardening Strategy in Bulk FinFETs.	IEEE Access	2020	DBLP DOI BibTeX RDF
21	Michael A. Turi, José G. Delgado-Frias	Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
21	N. Praveen Kumar, B. Stephen Charles, V. Sumalatha	Implementation of cache memory and fir filter using FINFETs at 22 nm technology for SOC designs.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
21	Haiyan Ni, Jianping Hu, Xuqiang Zhang, Haotian Zhu	The Optimizations of Dual-Threshold Independent-Gate FinFETs and Low-Power Circuit Designs.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
21	Kirti Bhanushali, Chinmay Tembe, W. Rhett Davis	Development of a Predictive Process Design kit for15-nm FinFETs: FreePDK15.	CoRR	2020	DBLP BibTeX RDF
21	Talha Furkan Canan, Savas Kaya, Harsha Chenji, Avinash Karanth	Reconfigurable Gates with Sub-10nm Ambipolar SB-FinFETs for Logic Locking & Obfuscation.	MWSCAS	2020	DBLP DOI BibTeX RDF
21	Vinay C. Patil, Sandip Kundu	On Leveraging Multi-threshold FinFETs for Design Obfuscation.	ISVLSI	2020	DBLP DOI BibTeX RDF
21	Zhiqing Li, Baofu Zhu, Anindya Nath, Meng Miao, Alain Loiseau, You Li, Jeffrey B. Johnson, Souvick Mitra, Robert Gauthier 0002	Understanding ESD Induced Thermal Mechanism in FinFETs Through Predictive TCAD Simulation.	IRPS	2020	DBLP DOI BibTeX RDF
21	Yiming Qu, Jiwu Lu, Junkang Li, Zhuo Chen, Jie Zhang, Chunlong Li, Shiuh-Wuu Lee, Yi Zhao	In-Situ Monitoring of Self-Heating Effect in Aggressively Scaled FinFETs and Its Quantitative Impact on Hot Carrier Degradation Under Dynamic Circuit Operation.	IRPS	2020	DBLP DOI BibTeX RDF
21	Longda Zhou, Qingzhu Zhang, Hong Yang, Zhigang Ji, Zhaohao Zhang, Renren Xu, Huaxiang Yin, Wenwu Wang 0006	Comparative Study on the Energy Profile of NBTI-Related Defects in Si and Ferroelectric p-FinFETs.	IRPS	2020	DBLP DOI BibTeX RDF
21	Talha Furkan Canan, Savas Kaya, Avinash Karanth, Ahmed Louri	4-Input NAND and NOR Gates Based on Two Ambipolar Schottky Barrier FinFETs.	ICECS	2020	DBLP DOI BibTeX RDF
21	Ramin Rajaei, Yen-Kai Lin, Sayeef S. Salahuddin, Michael T. Niemier, Xiaobo Sharon Hu	Dynamic Memory and Sequential Logic Design using Negative Capacitance FinFETs.	ISCAS	2020	DBLP DOI BibTeX RDF
21	Ahmad Zubair, Joshua A. Perozek, John Niroula, O. Aktas, V. Odnoblyudov, Tomás Palacios	First Demonstration of GaN Vertical Power FinFETs on Engineered Substrate.	DRC	2020	DBLP DOI BibTeX RDF
21	Umer Farooq Ahmed, Muhammad Mansoor Ahmed	An analytical model to assess DC characteristics of independent gate Si FinFETs.	Turkish J. Electr. Eng. Comput. Sci.	2019	DBLP DOI BibTeX RDF
21	Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek	Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node.	IEEE Access	2019	DBLP DOI BibTeX RDF
21	Jun-Sik Yoon, Seunghwan Lee, Junjong Lee, Jinsu Jeong, Hyeok Yun, Bohyeon Kang, Rock-Hyun Baek	Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node.	IEEE Access	2019	DBLP DOI BibTeX RDF
21	Wen-Teng Chang, Shih-Wei Lin, Min-Cheng Chen, Wen-Kuan Yeh	Relationship of Channel and Surface Orientation to Mechanical and Electrical Stresses on N-Type FinFETs.	IEICE Trans. Electron.	2019	DBLP DOI BibTeX RDF
21	Umer F. Ahmed, Muhammad Mansoor Ahmed, Qamar D. Memon	Non-linear compact model for FinFETs output characteristics.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
21	Maneesha Rupakula, Junrui Zhang, Francesco Bellando, Fabien Wildhaber, Clarissa Convertino, Heinz Schmid, Kirsten E. Moselund, Adrian Mihai Ionescu	Monolithically integrated catalyst-free High Aspect Ratio InAs-On-Insulator (InAsOI) FinFETs for pH sensing.	ESSDERC	2019	DBLP DOI BibTeX RDF
21	Hai Jiang 0005, Hyun-Chul Sagong, Jinju Kim, Junekyun Park, Sangchul Shin, Sangwoo Pae	Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit.	IRPS	2019	DBLP DOI BibTeX RDF
21	M. Iqbal Mahmud, Amit Gupta, Maria Toledano-Luque, N. Rao Mavilla, J. Johnson, P. Srinivasan 0002, A. Zainuddin, S. Rao, Salvatore Cimino, Byoung Min, Tanya Nigam	Hot Carrier Reliability Improvement of Thicker Gate Oxide nFET Devices in Advanced FinFETs.	IRPS	2019	DBLP DOI BibTeX RDF
21	Alexander Makarov, Ben Kaczer, Philippe Roussel, Adrian Vaisman Chasin, Alexander Grill, Michiel Vandemaele, Geert Hellings, Al-Moatasem El-Sayed, Tibor Grasser, Dimitri Linten, Stanislav Tyaginov	Modeling the Effect of Random Dopants on Hot-Carrier Degradation in FinFETs.	IRPS	2019	DBLP DOI BibTeX RDF
21	Narendra Parihar, Uma Sharma, Richard G. Southwick, Miaomiao Wang 0006, James H. Stathis, Souvik Mahapatra	On the Frequency Dependence of Bulk Trap Generation During AC Stress in Si and SiGe RMG P-FinFETs.	IRPS	2019	DBLP DOI BibTeX RDF
21	Xiaoxiao Xu, Jianping Hu, Shengwei Ke	Negative Capacitance Dual-Threshold Independent Gate FinFETs.	ISCAS	2019	DBLP DOI BibTeX RDF
21	Anton Sorokin, Nikolay Ryzhenko	SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean Routing.	ACM Great Lakes Symposium on VLSI	2019	DBLP DOI BibTeX RDF
21	Ran Cheng, Ming Tian, Changfeng Wang, Zhimei Cai, Jie Zhang, Yan-Yan Zhang, Yi Zhao	Performance Investigation of Uniaxially Tensile Stressed Ge n-FinFETs Formed on Biaxially Strained GeOI Substrates And Its Impact On Ge CMOS Inverters.	ASICON	2019	DBLP DOI BibTeX RDF
21	U. Rana, D. P. Brunco, S. Raman, Dina H. Triyoso, M. W. Stoker, J. B. Johnson, Luigi Pantisano, K. D. Seo, M. Zhao, A. Reznicek, R. Krishnan, B. Moser, J. Freeman, L. Jang, Evgeny Kaganer	High Performance and Yield for Super Steep Retrograde Wells (SSRW) by Well Implant / Si-based Epitaxy on Advanced Technology FinFETs.	DRC	2019	DBLP DOI BibTeX RDF
21	T. Nagateja, Avireni Srinivasulu, Dipankar Pal	RF Harvesting System for Low-Power Applications Using FinFETs.	ICCE	2019	DBLP DOI BibTeX RDF
21	Armineh Arasteh, Mohammad Hossein Moaiyeri, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh	An energy and area efficient 4: 2 compressor based on FinFETs.	Integr.	2018	DBLP DOI BibTeX RDF
21	Tiansong Cui, Ji Li 0006, Yanzhi Wang, Shahin Nazarian, Massoud Pedram	An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes.	IEEE Trans. Emerg. Top. Comput.	2018	DBLP DOI BibTeX RDF
21	Scott R. Stiffler, Ravikumar Ramachandran, W. Kirklen Henson, Noah Zamdmer, Kevin McStay, Giuseppe La Rosa, Kevin M. Boyd, Sungjae Lee, Claude Ortolland, Paul C. Parries	Process technology for IBM 14-nm processor designs featuring silicon-on-insulator FinFETs.	IBM J. Res. Dev.	2018	DBLP DOI BibTeX RDF
21	Lei Shen, Shaoyan Di, Longxiang Yin, Xiaoyan Liu, Gang Du	Calibration of drift-diffusion model in quasi-ballistic transport region for FinFETs.	Sci. China Inf. Sci.	2018	DBLP DOI BibTeX RDF
21	Longxiang Yin, Lei Shen, Hai Jiang, Gang Du, Xiaoyan Liu	Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate.	Sci. China Inf. Sci.	2018	DBLP DOI BibTeX RDF
21	Roya Dibaj, Dhamin Al-Khalili, Maitham Shams	Gate Oxide Short Defect Model in FinFETs.	J. Electron. Test.	2018	DBLP DOI BibTeX RDF
21	Fu-Yuan Tuan, Chii-Wen Chen, Mu-Chun Wang, Wen-Shiang Liao, Shea-Jue Wang, Shou-Kong Fan, Wen-How Lan	Thermal stress probing the channel-length modulation effect of nano n-type FinFETs.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
21	Ivo Vogt, Tomonori Nakamura, B. Motamedi, Christian Boit	Device characterization of 16/14 nm FinFETs for reliability assessment with infrared emission spectra.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
21	Ivo Vogt, Tomonori Nakamura, Ingrid De Wolf, Christian Boit	Detection of failure mechanisms in 24-40 nm FinFETs with (spectral) photon emission techniques using InGaAs camera.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
21	Mariusz Zubert, Tomasz Raszkowski, Agnieszka Samson, Piotr Zajac	Methodology of determining the applicability range of the DPL model to heat transfer in modern integrated circuits comprised of FinFETs.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
21	Erry Dwi Kurniawan, Hao Yang, Chia-Chou Lin, Yung-Chun Wu	Effect of fin shape of tapered FinFETs on the device performance in 5-nm node CMOS technology.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
21	Clarissa Convertino, Cezar B. Zota, Daniele Caimi, Marilyne Sousa, L. Czornomaz	InGaAs FinFETs 3D Sequentially Integrated on FDSOI Si CMOS with Record Perfomance.	ESSDERC	2018	DBLP DOI BibTeX RDF
21	Theano A. Karatsori, K. Bennamane, Christoforos G. Theodorou, L. Czornomaz, Jean Fompeyrine, Cezar B. Zota, Clarissa Convertino, Gérard Ghibaudo	Static and Low Frequency Noise Characterization of InGaAs MOSFETs and FinFETs on Insulator.	ESSDERC	2018	DBLP DOI BibTeX RDF
21	Yunus Kelestemur, Soumyasanta Laha, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri	Sub-THz Tunable Push-Push Oscillators with FinFETs for Wireless NoCs.	MWSCAS	2018	DBLP DOI BibTeX RDF
21	Jacopo Franco, Ben Kaczer, Adrian Vaisman Chasin, Erik Bury, Dimitri Linten	Hot electron and hot hole induced degradation of SiGe p-FinFETs studied by degradation maps in the entire bias space.	IRPS	2018	DBLP DOI BibTeX RDF
21	Shaofeng Guo, Zhenghan Lin, Runsheng Wang, Zexuan Zhang, Zhe Zhang, Yangyuan Wang, Ru Huang	Investigation on the amplitude coupling effect of random telegraph noise (RTN) in nanoscale FinFETs.	IRPS	2018	DBLP DOI BibTeX RDF
21	I. K. Chen, S. C. Chen, S. Mukhopadhyay, D. S. Huang, J. H. Lee, Y. S. Tsai, Ryan Lu, Jun He	The physical mechanism investigation of off-state drain bias TDDB and its implication in advance HK/MG FinFETs.	IRPS	2018	DBLP DOI BibTeX RDF
21	Talha Furkan Canan, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri	10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs.	ICECS	2018	DBLP DOI BibTeX RDF
21	Venkatesh Srinivasan, Stephane Le Tuai, Tai-Cheng Lee	F2: FinFETs & FDSOI - A mixed signal circuit designer's perspective.	ISSCC	2018	DBLP DOI BibTeX RDF
21	Tingfeng Yang, Jianping Hu, Wenjing Bai	Analysis and Simulation of Negative Capacitance Independent Multi-Gate FinFETs.	ISCAS	2018	DBLP DOI BibTeX RDF
21	D. A. J. Millar, X. Li, U. Peralagu, M. J. Steer, I. M. Pavey, Guilherme Gaspar, M. Schmidt, P. K. Hurley, I. G. Thayne	High Aspect Ratio Junctionless InGaAs FinFETs Fabricated Using a Top-Down Approach.	DRC	2018	DBLP DOI BibTeX RDF
21	Ke Han, Guohui Qiao, Zhongliang Deng, Qingbo Li, Huashuai Xing	The optimal geometry parameters and impact of parasitic capacitance and resistance of sub-14nm SOI multi-fin FinFETs.	J. Intell. Fuzzy Syst.	2017	DBLP DOI BibTeX RDF
21	Shilpa Saxena, Rajesh Mehra	Low-power and high-speed 13T SRAM cell using FinFETs.	IET Circuits Devices Syst.	2017	DBLP DOI BibTeX RDF
21	Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar	Spacer engineering for performance enhancement of junctionless accumulation-mode bulk FinFETs.	IET Circuits Devices Syst.	2017	DBLP DOI BibTeX RDF
21	Nanditha P. Rao, Madhav P. Desai	Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs.	CoRR	2017	DBLP BibTeX RDF
21	Luca Donetti, Carlos Sampedro 0002, Francisco Javier García Ruiz, Andres Godoy, Francisco Gámiz	Three-dimensional multi-subband simulation of scaled FinFETs.	ESSDERC	2017	DBLP DOI BibTeX RDF
21	F. M. Bufler, Kenichi Miyaguchi, Thomas Chiarella, N. Horiguchi, Anda Mocuta	On the ballistic ratio in 14nm-Node FinFETs.	ESSDERC	2017	DBLP DOI BibTeX RDF
21	Wei-feng Lü, Mi Lin, Haipeng Zhang	Investigation on Gate Capacitances Fluctuation Due to Work-Function Variation in Metal-Gate FinFETs.	FSDM	2017	DBLP DOI BibTeX RDF
21	Haotian Zhu, Jianping Hu, Huishan Yang, Yang Xiong, Tingfeng Yang	A topology optimization method for low-power logic circuits with dual-threshold independent-gate FinFETs.	PATMOS	2017	DBLP DOI BibTeX RDF
21	Talha Furkan Canan, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri	Ultra-compact sub-10nm logic circuits based on ambipolar SB-FinFETs.	MWSCAS	2017	DBLP DOI BibTeX RDF