Search results for "Floorplan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
103	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu	Effective decap insertion in area-array SoC floorplan design.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	decap insertion, floorplan, Power supply noise
93	Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen	Twin binary sequences: a nonredundant representation for general nonslicing floorplan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
93	Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen	Twin binary sequences: a non-redundant representation for general non-slicing floorplan.	ISPD	2002	DBLP DOI BibTeX RDF
84	Claudia I. Horta, José A. Lima	Slicing and non-slicing, unified and rotation independent, algebraic representation of floorplans.	EUROMICRO	1997	DBLP DOI BibTeX RDF	floorplan area optimization problem, rectangle envelope, nonoverlapping basic rectangles, floorplan topology, formal algebraic specification, SETS notation, VLSI physical design layout, module dimensions, arbitrarily complex composite floorplans, rotation-invariant single-expression formalism, generalized wheels floorplans, slicing representation, nonslicing representation, unified representation, topology-dimensionless description, floorplanning problem algorithms, algebraic specification, line segments, relative positioning
82	Michael D. Moffitt, Aaron N. Ng, Igor L. Markov, Martha E. Pollack	Constraint-driven floorplan repair.	DAC	2006	DBLP DOI BibTeX RDF	constraints, floorplanning, legalization
82	Chih-Hung Lee, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh	An efficient hierarchical approach for general floorplan area minimization.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
81	Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham	Floorplan representations: Complexity and connections.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Baxter permutation, Floorplan representation, O-tree, mosaic floorplan, number of combinations, twin binary trees
81	P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya	VLSI floorplan generation and area optimization using AND-OR graph search.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI floorplan generation, AND-OR graph search, rectangular dualization, minimum-area floorplan, optimal sizing, heuristic search method, top-down first phase, search effort, bottom-up polynomial-time algorithm, nonslicible floorplans, VLSI, graph theory, circuit layout CAD, circuit optimisation, integrated circuit interconnections, aspect ratios, area optimization, adjacency graph
74	Shin-Ichi Nakano	Enumerating Floorplans with n Rooms.	ISAAC	2001	DBLP DOI BibTeX RDF	Graphs, Enumeration, Listing, Plane graphs
74	Jin-Tai Yan	An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
74	Qing Dong 0002, Bo Yang 0004, Jing Li 0072, Shigetoshi Nakatake	Incremental buffer insertion and module resizing algorithm using geometric programming.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	module resizing, floorplan, buffer insertion, geometric programming
72	Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov, Martha E. Pollack	Constraint-driven floorplan repair.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	constraints, Floorplanning, legalization
72	Chiu-Wing Sham, Evangeline F. Y. Young	Area reduction by deadspace utilization on interconnect optimized floorplan.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	area reduction, Floorplanning
64	Saurabh N. Adya, Igor L. Markov	Fixed-outline floorplanning: enabling hierarchical design.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
64	Zion Cien Shen, Chris C. N. Chu	Bounds on the number of slicing, mosaic, and general floorplans.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
61	Kenichi Ida, Yosuke Kimura	Floorplan Design Using Improved Genetic Algorithm.	ISMIS	2003	DBLP DOI BibTeX RDF
61	Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang	Hierarchical Floorplan Design on the Internet.	ASP-DAC	1999	DBLP DOI BibTeX RDF
61	H. Cai	On empty rooms in floorplan graphics: comments on a deficiency in two papers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
60	Chuan Lin 0002, Hai Zhou 0001, Chris C. N. Chu	A revisit to floorplan optimization by Lagrangian relaxation.	ICCAD	2006	DBLP DOI BibTeX RDF	floorplan, Lagrangian relaxation
53	Jackey Z. Yan, Chris Chu	DeFer: deferred decision making enabled fixed-outline floorplanner.	DAC	2008	DBLP DOI BibTeX RDF	deferred decision making, floorplanning, fixed outline
53	Maolin Tang, Alvin Sebastian	A Genetic Algorithm for VLSI Floorplanning Using O-Tree Representation.	EvoWorkshops	2005	DBLP DOI BibTeX RDF
53	Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan	PEPPER - a timing driven early floorplanner.	ICCD	1995	DBLP DOI BibTeX RDF	PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay
50	Zaichen Qian, Evangeline F. Y. Young	Multi-voltage floorplan design with optimal voltage assignment.	ISPD	2009	DBLP DOI BibTeX RDF	multi-voltage assignment optimization branch-and-bound
50	Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong	Heuristic power/ground network and floorplan co-design method.	ASP-DAC	2008	DBLP DOI BibTeX RDF
50	Maolin Tang	A New Greedy Algorithm for VLSI Floorplan Optimization.	CSSE (4)	2008	DBLP DOI BibTeX RDF
50	Chen-Wei Liu, Yao-Wen Chang	Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
50	Shih-Hsu Huang, Chu-Liao Wang, Man-Lin Huang	A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs.	EUC	2007	DBLP DOI BibTeX RDF	Reused Block, Modeling, Power Consumption, Voltage Drop
50	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
50	Chen-Wei Liu, Yao-Wen Chang	Floorplan and power/ground network co-synthesis for fast design convergence.	ISPD	2006	DBLP DOI BibTeX RDF	power/ground analysis, simulated annealing, floorplanning, IR drop, power integrity
50	Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo	Floorplan-aware decoupling capacitance budgeting on equivalent circuit model.	ISCAS	2006	DBLP DOI BibTeX RDF
50	Yongpan Liu, Huazhong Yang, Rong Luo, Hui Wang 0004	A Hierarchical Approach for Incremental Floorplan Based on Genetic Algorithms.	ICNC (3)	2005	DBLP DOI BibTeX RDF
50	Dongku Kang, Hunsoo Choo, Kaushik Roy 0001	Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed.	ICCD	2004	DBLP DOI BibTeX RDF
50	Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham	Revisiting floorplan representations.	ISPD	2001	DBLP DOI BibTeX RDF
50	D. F. Wong 0001, P. S. Sakhamuri	Efficient Floorplan Area Optimization.	DAC	1989	DBLP DOI BibTeX RDF
50	Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng	Bus via reduction based on floorplan revising.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	floorplan revising, via reduction, bus routing
50	Dipanjan Sengupta, Resve A. Saleh	Application-driven floorplan-aware voltage island design.	DAC	2008	DBLP DOI BibTeX RDF	dynamic programming, energy, floorplan, voltage island
50	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	Floorplan driven leakage power aware IP-based SoC design space exploration.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	floorplan, leakage power, temperature
50	Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Designing application-specific networks on chips with floorplan information.	ICCAD	2006	DBLP DOI BibTeX RDF	networks on chips, topology, floorplan, deadlock-free routing
42	Hushrav Mogal, Kia Bazargan	Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction.	ICCAD	2008	DBLP DOI BibTeX RDF
42	Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen	Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
42	Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao	Simultaneous floor plan and buffer-block optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
42	Xuliang Zhang, Yoji Kajitani	Space-planning: placement of modules with controlled empty area by single-sequence.	ASP-DAC	2004	DBLP DOI BibTeX RDF
42	Zahava Koren, Israel Koren	On the effect of floorplanning on the yield of large area integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
42	Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya	Geometric bipartitioning problem and its applications to VLSI.	VLSI Design	1996	DBLP DOI BibTeX RDF	geometric bipartitioning problem, layout design, rectilinear modules, staircase, monotone increasing, classical graph bisection problem, weighted permutation graph, integer edge weights, designated nodes, absolute value, edge weights, routing, computational complexity, VLSI, VLSI, graph theory, NP-complete, branch-and-bound, floorplan, heuristic algorithm, search problems, geometry, network routing, circuit layout CAD, hierarchical decomposition
42	Jin-Tai Yan	An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering.	ICCD	1995	DBLP DOI BibTeX RDF	cut-based algorithm, L-shaped channels, safe routing ordering, geometrical topology, floorplan graph, channel precedence graph, S-cuts, redundant L-cuts, balanced L-cuts, non-minimal L-cuts, non-critical L-cuts, critical L-cuts, computational complexity, time complexity, circuit layout CAD, line segments, precedence relations
40	Jia Wang 0003, Hai Zhou 0001	Linear constraint graph for floorplan optimization with soft blocks.	ICCAD	2008	DBLP DOI BibTeX RDF
40	Zhipeng Liu, Jinian Bian, Qiang Zhou 0001, Hui Dai	Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan.	ISVLSI	2007	DBLP DOI BibTeX RDF
40	Vyas Krishnan, Srinivas Katkoori	Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
40	Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu	Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity.	ISCAS	2007	DBLP DOI BibTeX RDF
40	Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou 0001, Qiang Wu	A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design.	ICESS	2005	DBLP DOI BibTeX RDF
40	Hayward H. Chan, Saurabh N. Adya, Igor L. Markov	Are floorplan representations important in digital design?	ISPD	2005	DBLP DOI BibTeX RDF	B*-tree, floorplanning, sequence pair, circuit layout
40	Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen	Wiring area optimization in floorplan-aware hierarchical power grids.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
40	Wing Seung Yuen, Evangeline F. Y. Young	Slicing floorplan with clustering constraint.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
40	Dongku Kang, Mark C. Johnson, Kaushik Roy 0001	Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan.	ICCD	2003	DBLP DOI BibTeX RDF
40	Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young	Congestion Estimation with Buffer Planning in Floorplan Design.	DATE	2002	DBLP DOI BibTeX RDF
40	Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003	GPE: A New Representation for VLSI Floorplan Problem.	ICCD	2002	DBLP DOI BibTeX RDF
40	Shih-Hsu Huang, Chu-Liao Wang	An effective floorplan-based power distribution network design methodology under reliability constraints.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
40	Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky	Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
40	Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong	Handling soft modules in general nonslicing floorplan usingLagrangian relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
40	Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang	On extending slicing floorplan to handle L/T-shaped modules andabutment constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
40	Xiaobo Hu 0001, Danny Z. Chen, Rajeshkumar S. Sambandam	Efficient list-approximation techniques for floorplan area minimization.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	k-link shortest paths, list approximation, floorplanning, area minimization
40	Wing Seung Yuen, Fung Yu Young	Slicing floorplan with clustering constraints.	ASP-DAC	2001	DBLP DOI BibTeX RDF
40	Gary K. H. Yeap, Majid Sarrafzadeh	A unified approach to floorplan sizing and enumeration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
40	James P. Cohoon, Shailesh U. Hegde, Worthy N. Martin, Dana S. Richards	Distributed genetic algorithms for the floorplan design problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
40	Cheng-Hsi Chen, Ioannis G. Tollis	Parallel algorithms for slicing floorplan designs.	SPDP	1990	DBLP DOI BibTeX RDF
40	Chang-Sheng Ying, Joshua Sook-Leung Wong, X. L. Hong, E. Q. Wang	Path search on rectangular floorplan.	EURO-DAC	1990	DBLP DOI BibTeX RDF
40	Yen-Tai Lai, Sany M. Leinwand	Algorithms for floorplan design via rectangular dualization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
39	Rory McInerney, Kurt Leeper, Troy Hill, Heming Chan, Bulent Basaran, Lance McQuiddy	Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor.	ISPD	2000	DBLP DOI BibTeX RDF	RC delay, routing, timing, estimation, microprocessors, floorplan, repeaters
32	De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang	Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	wire bonding, floorplanning, system-in-package
32	Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong	Incremental power optimization for multiple supply voltage design.	ISQED	2009	DBLP DOI BibTeX RDF
32	Song Chen 0001, Zheng Xu, Takeshi Yoshimura	A generalized V-shaped multilevel method for large scale floorplanning.	ISQED	2009	DBLP DOI BibTeX RDF
32	Chaomin Luo, Miguel F. Anjos, Anthony Vannelli	A nonlinear optimization methodology for VLSI fixed-outline floorplanning.	J. Comb. Optim.	2008	DBLP DOI BibTeX RDF	Circuit layout design, VLSI floorplanning, Facility layout, Combinatorial optimization, Global optimization, Convex programming
32	Sami Habib, Maytham Safar	Sensitivity Study of Sensors' Coverage within Wireless Sensor Networks.	ICCCN	2007	DBLP DOI BibTeX RDF
32	Vijay Sundaresan, Ranga Vemuri	A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning.	ISVLSI	2006	DBLP DOI BibTeX RDF
32	Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh	Layout driven data communication optimization for high level synthesis.	DATE	2006	DBLP DOI BibTeX RDF
32	Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai	Design space exploration for minimizing multi-project wafer production cost.	ASP-DAC	2006	DBLP DOI BibTeX RDF
32	Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto	On-chip thermal gradient analysis and temperature flattening for SoC design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
32	Jill H. Y. Law, Evangeline F. Y. Young	Multi-bend bus driven floorplanning.	ISPD	2005	DBLP DOI BibTeX RDF	bus planning, floorplanning, VLSI CAD
32	Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong	Bus-driven floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
32	Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang	Constrained floorplanning using network flows.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
32	Hai Zhou 0001, Jia Wang 0003	ACG-Adjacent Constraint Graph for General Floorplans.	ICCD	2004	DBLP DOI BibTeX RDF
32	Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang	Constrained "Modern" Floorplanning.	ISPD	2003	DBLP DOI BibTeX RDF	floorplanning, network flow, rectilinear polygons
32	Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong	Bus-Driven Floorplanning.	ICCAD	2003	DBLP DOI BibTeX RDF
32	Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh	Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
32	Parthasarathi Dasgupta, Peichen Pan, Subhas C. Nandy, Bhargab B. Bhattacharya	Monotone bipartitioning problem in a planar point set with applications to VLSI.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Complexity of algorithms, routing, very large scale integration (VLSI), partitioning, floorplanning
32	Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh	Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
32	Abhishek Ranjan, Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh	Fast floorplanning for effective prediction and construction.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
32	Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu	VLSI floorplanning with boundary constraints based on corner block list.	ASP-DAC	2001	DBLP DOI BibTeX RDF
32	Kia Bazargan, Samjung Kim, Majid Sarrafzadeh	Nostradamus: a floorplanner of uncertain designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
32	Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya	A unified approach to topology generation and optimal sizing of floorplans.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
32	Israel Koren, Zahava Koren	Yield and Routing Objectives in Floorplanning.	DFT	1998	DBLP DOI BibTeX RDF
32	Kazuhiko Eguchi, Junya Suzuki, Satoshi Yamane, Kenji Oshima	An Application of Genetic Algorithms to Floorplanning of VLSI.	Rough Sets and Current Trends in Computing	1998	DBLP DOI BibTeX RDF
31	Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee	Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling.	ASP-DAC	2007	DBLP DOI BibTeX RDF	wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances
31	Zhenyu (Peter) Gu, Jia Wang 0003, Robert P. Dick, Hai Zhou 0001	Incremental exploration of the combined physical and behavioral design space.	DAC	2005	DBLP DOI BibTeX RDF	high-level synthesis, floorplan, incremental
29	Toshihiko Takahashi, Ryo Fujimaki, Youhei Inoue	A (4n - 4)-Bit Representation of a Rectangular Drawing or Floorplan.	COCOON	2009	DBLP DOI BibTeX RDF
29	Sarah E. Murphy, Erik DeBenedictis, Peter M. Kogge	General floorplan for reversible quantum-dot cellular automata.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	reversible computing, quantum-dot cellular automata
29	Kristofer Vorwerk, Andrew A. Kennings, Doris T. Chen, Laleh Behjat	Floorplan repair using dynamic whitespace management.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	VLSI, placement, floorplanning, legalization
29	Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane	FABSYN: floorplan-aware bus architecture synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
29	Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee	A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design.	MICRO	2006	DBLP DOI BibTeX RDF
29	Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S. Ching	Block alignment in 3D floorplan using layered TCG.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	3D floorplanning, block alignment