Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
153 | Tung-Chieh Chen, Yao-Wen Chang |
Modern floorplanning based on fast simulated annealing. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
simulated annealing, floorplanning |
117 | Tung-Chieh Chen, Yao-Wen Chang |
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
94 | Jianzhong Shi, Akash Randhar, Dinesh Bhatia |
Macro Block Based FPGA Floorplanning. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design |
93 | Chaomin Luo, Miguel F. Anjos, Anthony Vannelli |
A nonlinear optimization methodology for VLSI fixed-outline floorplanning. |
J. Comb. Optim. |
2008 |
DBLP DOI BibTeX RDF |
Circuit layout design, VLSI floorplanning, Facility layout, Combinatorial optimization, Global optimization, Convex programming |
88 | Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee |
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances |
83 | Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001 |
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
piecewise-linear, performance, pipeline, interconnect, floorplanning |
77 | Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng |
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
77 | Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov |
Unification of partitioning, placement and floorplanning. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
72 | Bo-Shiun Wu, Tsung-Yi Ho |
Bus-pin-aware bus-driven floorplanning. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
bus planning, floorplanning |
72 | Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng |
Integrating dynamic thermal via planning with 3D floorplanning algorithm. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
3D floorplanning, thermal optimization, thermal via |
72 | Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang |
Constrained "Modern" Floorplanning. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
floorplanning, network flow, rectilinear polygons |
72 | Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang |
Multilevel floorplanning/placement for large-scale modules using B*-trees. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
multilevel framework, floorplanning, lagrangian relaxation |
72 | Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani |
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
floorplanning, routability, interconnect estimation |
72 | Maggie Zhiwei Kang, Wayne Wei-Ming Dai, Tom Dillinger, David P. LaPotin |
Delay bounded buffered tree construction for timing driven floorplanning. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
Total Wire Length, DBB-tree, SPT, Floorplanning, Buffer Insertion, Delay Bounds, Elmore Delay, MST |
70 | Jarrod A. Roy, Saurabh N. Adya, David A. Papa, Igor L. Markov |
Min-cut floorplacement. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
67 | Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001 |
Microarchitecture Configurations and Floorplanning Co-Optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
67 | Jason Cong, Jie Wei, Yan Zhang |
A thermal-driven floorplanning algorithm for 3D ICs. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
67 | Abhishek Ranjan, Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh |
Fast floorplanning for effective prediction and construction. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
66 | Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu |
Architecting voltage islands in core-based system-on-a-chip designs. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
multiple VDD, low-power, floorplanning, system-on-a-chip, voltage island |
62 | Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang |
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs. |
ISPD |
2009 |
DBLP DOI BibTeX RDF |
multiple-supply voltage designs, physical design, floorplanning, vlsi |
62 | Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani |
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
floorplanning, thermal, 3D IC |
62 | Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar |
Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
floorplanning, microarchitecture, transient analysis |
62 | Rong Liu, Sheqin Dong, Xianlong Hong |
Fixed-outline floorplanning based on common subsequence. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
common subsequence, floorplanning, fixed-outline |
62 | Meng-Chiou Wu, Rung-Bin Lin |
Reticle floorplanning of flexible chips for multi-project wafers. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
mask cost, multi-project wafer, reticle floorplanning, dicing |
62 | Jason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl |
An area-optimality study of floorplanning. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
area partitioning, block packing, optimality, benchmarking, placement, floorplanning, aspect ratios |
62 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Yici Cai, Chung-Kuan Cheng, Jun Gu |
An integrated floorplanning with an efficient buffer planning algorithm. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
floorplanning, buffer insertion, routability |
62 | Xiaoping Tang, D. F. Wong 0001 |
Floorplanning with alignment and performance constraints. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
floorplanning, longest common subsequence, sequence pair |
60 | Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao |
Simultaneous floor plan and buffer-block optimization. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
57 | Bei Yu 0001, Sheqin Dong, Satoshi Goto, Song Chen 0001 |
Voltage-island driven floorplanning considering level-shifter positions. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
convex network flow, level shifter assignment, voltage assignment, white space redistribution, voltage-island |
57 | Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou 0001, Xianlong Hong, Qiang Zhou 0001 |
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
57 | Hua Xiang 0001, Liang Deng, Li-Da Huang, Martin D. F. Wong |
OPC-Friendly Bus Driven Floorplanning. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
57 | Minsik Cho, Hongjoong Shin, David Z. Pan |
Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
57 | Yan Feng, Dinesh P. Mehta |
Heterogeneous Floorplanning for FPGAs. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
57 | Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu |
LFF algorithm for heterogeneous FPGA floorplanning. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
57 | Maolin Tang, Alvin Sebastian |
A Genetic Algorithm for VLSI Floorplanning Using O-Tree Representation. |
EvoWorkshops |
2005 |
DBLP DOI BibTeX RDF |
|
57 | Meng-Chiou Wu, Rung-Bin Lin |
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
57 | Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang |
Constrained floorplanning using network flows. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
57 | Thomas Lengauer, Rolf Müller |
Robust and accurate hierarchical floorplanning with integrated global wiring. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
52 | Song Chen 0001, Takeshi Yoshimura |
A stable fixed-outline floorplanning method. |
ISPD |
2007 |
DBLP DOI BibTeX RDF |
floorplanning, sequence pair, fixed-outline |
52 | Mario R. Casu, Luca Macchiarulo |
Floorplanning for throughput. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
systems-on-chip, throughput, floorplanning, wire pipelining |
52 | Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang |
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
Interconnect-Driven Floorplanning, Performance Optimization |
52 | Israel Koren, Zahava Koren |
Incorporating Yield Enhancement into the Floorplanning Process. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
memory ICs, routing complexity, redundancy, microprocessor, Floorplanning, yield |
52 | Pradeep Prabhakaran, Prithviraj Banerjee |
Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
timing driven synthesis, High-level synthesis, floorplanning |
48 | Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh |
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. |
IEEE International Workshop on Rapid System Prototyping |
1999 |
DBLP DOI BibTeX RDF |
3-D floorplanning, Reconfigurable computing, floorplanning |
47 | Minsik Cho, David Z. Pan |
Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin |
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Dae Hyun Kim 0004, Sung Kyu Lim |
Bus-aware microarchitectural floorplanning. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Maolin Tang, Xin Yao 0001 |
A Memetic Algorithm for VLSI Floorplanning. |
IEEE Trans. Syst. Man Cybern. Part B |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh |
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Hushrav Mogal, Kia Bazargan |
Microarchitecture floorplanning for sub-threshold leakage reduction. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Chunta Chu, Xinyi Zhang, Lei He 0001, Tong Jing |
Temperature aware microprocessor floorplanning considering application dependent power load. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Peter G. Sassone, Sung Kyu Lim |
Traffic: a novel geometric algorithm for fast wire-optimized floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Jason Cong, Michail Romesis, Joseph R. Shinnerl |
Fast floorplanning by look-ahead enabled recursive bipartitioning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Vijay Sundaresan, Ranga Vemuri |
A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Yong Zhan, Yan Feng, Sachin S. Sapatnekar |
A fixed-die floorplanning algorithm using an analytical approach. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Zhaojun Wo, Israel Koren, Maciej J. Ciesielski |
Yield-aware Floorplanning. |
DSD |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Jason Cong, Michail Romesis, Joseph R. Shinnerl |
Fast floorplanning by look-ahead enabled recursive bipartitioning. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Lei Cheng 0001, Liang Deng, Martin D. F. Wong |
Floorplanning for 3-D VLSI design. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani |
Fixed-outline floorplanning with constraints through instance augmentation. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003, Hsin-Hsien Ho |
Modem floorplanning with abutment and fixed-outline constraints. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Wei-Lun Hung, Yuan Xie 0001, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin |
Thermal-Aware Floorplanning Using Genetic Algorithms. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Shinn-Ying Ho, Shinn-Jang Ho, Yi-Kuang Lin, W. C.-C. Chu |
An orthogonal simulated annealing algorithm for large floorplanning problems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
47 | Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Xu Xu 0001, Alexander Zelikovsky |
Multi-project reticle floorplanning and wafer dicing. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
multi-project wafers, reticle design, wafer dicing |
47 | Martin D. F. Wong |
Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
47 | Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani |
Integrated floorplanning with buffer/channel insertion for bus-based designs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
47 | Matthew Moe, Herman Schmit |
Floorplanning of pipelined array modules using sequence pairs. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
pipelined array, floorplan, sequence pair |
47 | Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh |
Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
47 | Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani |
Consistent floorplanning with hierarchical superconstraints. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
47 | Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh |
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
47 | I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong 0001 |
Integrated power supply planning and floorplanning. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
47 | John Marty Emmert, Akash Randhar, Dinesh Bhatia |
Fast Floorplanning for FPGAs. |
FPL |
1998 |
DBLP DOI BibTeX RDF |
|
47 | Chang-Sheng Ying, Joshua Sook-Leung Wong |
An analytical approach to floorplanning for hierarchical building blocks layout [VLSI]. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1989 |
DBLP DOI BibTeX RDF |
|
46 | Jackey Z. Yan, Natarajan Viswanathan, Chris Chu |
Handling complexities in modern large-scale mixed-size placement. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
incremental placement, mixed-size design, floorplanning |
46 | Natarajan Viswanathan, Min Pan, Chris C. N. Chu |
FastPlace: an analytical placer for mixed-mode designs. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
mixed-mode placement, floorplanning, analytical placement |
46 | Su-Wei Wu, Yao-Wen Chang |
Efficient power/ground network analysis for power integrity-driven design methodology. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
footnotesize floorplanning, power/ground network |
42 | De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang |
Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
wire bonding, floorplanning, system-in-package |
42 | David Cuesta, José Luis Ayala, José Ignacio Hidalgo, Massimo Poncino, Andrea Acquaviva, Enrico Macii |
Thermal-aware floorplanning exploration for 3D multi-core architectures. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
3D, floorplanning, MPSoC, temperature |
42 | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
T-trees: A tree-based representation for temporal and three-dimensional floorplanning. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
temporal floorplanning, Reconfigurable computing, partially dynamical reconfiguration |
42 | Jyh-Perng Fang, Yang-Lang Chang, Chih-Chia Chen, Wen-Yew Liang, Tung-Ju Hsieh, Muhammad T. Satria, Chin-Chuan Han |
A Parallel Simulated Annealing Approach for Floorplanning in VLSI. |
ICA3PP |
2009 |
DBLP DOI BibTeX RDF |
FFA, Parallel Computing, Simulated Annealing, OpenMP, Floorplanning |
42 | Jinzhu Chen, Guolong Chen, Wenzhong Guo |
A Discrete PSO for Multi-objective Optimization in VLSI Floorplanning. |
ISICA |
2009 |
DBLP DOI BibTeX RDF |
discrete PSO, MOP, floorplanning |
42 | Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin, Wen-Nai Cheng |
Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
crosstalk reduction, full-chip routing, gridless routing, implicit connection graph-based router, non-slicing floorplanning, detailed routing |
42 | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
Temporal floorplanning using the three-dimensional transitive closure subGraph. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
temporal floorplanning, Reconfigurable computing, partially dynamical reconfiguration |
42 | Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani |
How does partitioning matter for 3D floorplanning? |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
partitioning, floorplanning, 3D IC, wire length |
42 | Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu |
Optimal cell flipping in placement and floorplanning. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
flipping, placement, floorplanning, orientation, wirelength |
42 | Jill H. Y. Law, Evangeline F. Y. Young |
Multi-bend bus driven floorplanning. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
bus planning, floorplanning, VLSI CAD |
42 | Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar |
Microarchitecture-aware floorplanning using a statistical design of experiments approach. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
floorplanning, microarchitecture, wire pipelining |
42 | Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim |
Profile-guided microarchitectural floorplanning for deep submicron processor design. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
microarchitectural planning, computer architecture, floorplanning |
42 | Jingcao Hu, Yangdong Deng, Radu Marculescu |
System-Level Point-to-Point Communication Synthesis using Floorplanning Information. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
System-leve design, low-power, floorplanning, Communication synthesis, point-to-point communication |
42 | Swanwa Liao, Mario Alberto López, Dinesh P. Mehta |
Constrained polygon transformations for incremental floorplanning. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
floorplanning, incremental design, rectilinear polygons |
42 | Takayuki Yamanouchi, Kazuo Tamakashi, Takashi Kambe |
Hybrid floorplanning based on partial clustering and module restructuring. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
slicing structure, clustering, placement, floorplanning |
42 | Susmita Sur-Kolay, Bhargab B. Bhattacharya |
Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning. |
FSTTCS |
1988 |
DBLP DOI BibTeX RDF |
plane triangulated graphs, rectangular duals, slicing structures, algorithms, floorplanning, VLSI layout |
40 | Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang |
MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Lei Cheng 0001, Martin D. F. Wong |
Floorplan Design for Multimillion Gate FPGAs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Lei Cheng 0001, Martin D. F. Wong |
Floorplan design for multi-million gate FPGAs. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Kia Bazargan, Samjung Kim, Majid Sarrafzadeh |
Nostradamus: a floorplanner of uncertain designs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Kia Bazargan, Samjung Kim, Majid Sarrafzadeh |
Nostradamus: a floorplanner of uncertain design. |
ISPD |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Song Chen 0001, Zheng Xu, Takeshi Yoshimura |
A generalized V-shaped multilevel method for large scale floorplanning. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
37 | Tilen Ma, Evangeline F. Y. Young |
TCG-based multi-bend bus driven floorplanning. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Pradeep Fernando, Srinivas Katkoori |
An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Love Singhal, Elaheh Bozorgzadeh |
Novel Multi-Layer floorplanning for Heterogeneous FPGAs. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|