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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6026 occurrences of 2178 keywords
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Results
Found 12513 publication records. Showing 12509 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
68 | Paul E. Hasler, Bradley A. Minch, Chris Diorio |
Adaptive Circuits Using pFET Floating-Gate Devices. |
ARVLSI |
1999 |
DBLP DOI BibTeX RDF |
|
68 | Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu |
Generation of tenacious tests for small gate delay faults in combinational circuits. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage |
60 | Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera |
Statistical modeling of gate-delay variation with consideration of intra-gate variability. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
60 | Paul E. Hasler, Paul D. Smith |
An autozeroing floating-gate amplifier with gain adaptation. |
ISCAS (2) |
1999 |
DBLP DOI BibTeX RDF |
|
58 | Narender Hanchate, Nagarajan Ranganathan |
Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
Game theory, gate sizing, transmission lines, crosstalk noise, interconnect models, interconnect delay |
57 | Hari Ananthan, Kaushik Roy 0001 |
A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
leakage distribution, multiple-gate, tri-gate, process variations, finFET, double-gate |
56 | Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001 |
Constructing Current-Based Gate Models Based on Existing Timing Library. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
55 | A. Madan, S. C. Bose, P. J. George, Chandra Shekhar 0001 |
Evaluation of Device Parameters of HfO2/SiO2/Si Gate Dielectric Stack for MOSFETs. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
Direct Tunneling, gate leakage current, high-K gate stack, MOSFETs |
54 | Omid Mirmotahari, Yngvar Berg |
Proposal for a Bidirectional Gate Using Pseudo Floating-Gate. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
floating-gate (FG), multiple-valued logic (MVL), bidirectional |
53 | Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang |
Nanoscale CMOS circuit leakage power reduction by double-gate device. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
double-gate device, short-channel effect, leakage power |
53 | Vijay Sundararajan, Keshab K. Parhi |
Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution. |
ARVLSI |
1999 |
DBLP DOI BibTeX RDF |
Gate-resizing, Buffer-redistribution, near-optimal, library-specific, optimal, low-power |
53 | Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang |
On Designing of 4-Valued Memory with Double-Gate TFT. |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit |
52 | Shinichi Kato, Minoru Watanabe |
Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI. |
SAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
51 | Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee |
Explicit gate delay model for timing evaluation. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
pre-characterize, delay model, explicit |
51 | Shinya Kubota, Minoru Watanabe |
A nine-context programmable optically reconfigurable gate array with semiconductor lasers. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
holographic memory, optically reconfigurable gate arrays, field programmable gate arrays |
50 | Yoko Sakai, Yoriko Mawatari, Kiyonari Yamasaki, Ko-ichiroh Shohda, Akira Suyama |
Construction of AND Gate for RTRACS with the Capacity of Extension to NAND Gate. |
DNA |
2009 |
DBLP DOI BibTeX RDF |
molecular computer, logic gate |
50 | Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang |
A comparison of via-programmable gate array logic cell circuits. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
logic cell, via-programmable gate arrays |
49 | Keijiro Nakamura |
Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks. |
IEEE Trans. Computers |
1979 |
DBLP DOI BibTeX RDF |
number of inversions, Gate-minimum network, inverse edge, MOS complex gate, negative function, negative gate |
49 | Puneet Gupta 0001, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma |
Eyecharts: constructive benchmarking of gate sizing heuristics. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
dynamic programming, benchmarking, gate sizing |
49 | Zhuo Gao, Ji Luo 0003, Hu Huang 0001, Wei Zhang, Joseph B. Bernstein |
Reliable Laser Programmable Gate Array Technology. |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
Laser Programmable Gate Array (LPGA), Laser Field-Programmable Gate Array (LFPGA), MakeLink technology, laser-induced/laser programmable anti-fuse, digital ASIC design, low electrical resistance anti-fuse, Field-Programmable Gate Array (FPGA) |
47 | Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester |
Gate-length biasing for runtime-leakage control. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Mariam Momenzadeh, Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi |
Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy 0001 |
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
double-gate devices, quantum effect, stacking effect, estimation, SRAM, gate leakage, subthreshold leakage |
47 | Amir Fijany, Farrokh Vatan, Mohammad M. Mojarradi, Nikzad Benny Toomarian, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Pierre Gentil |
The G4-FET: a universal and programmable logic gate. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
G4-FET, programmable gate, universal logic gate, full adder |
47 | Minsik Ahn, Chang-Ho Lee, Joy Laskar |
CMOS High Power SPDT Switch using Multigate Structure. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
45 | Hafizur Rahaman 0001, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya |
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
Missing-gate faults, quantum computing, reversible logic, testable design, universal test set |
45 | Vishal Khandelwal, Ankur Srivastava 0001 |
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. |
ISPD |
2007 |
DBLP DOI BibTeX RDF |
post-silicon tunability, variability, stochastic optimization, timing optimization, gate sizing |
45 | Samir Roy, Biswajit Saha |
Minority Gate Oriented Logic Design with Quantum-Dot Cellular Automata. |
ACRI |
2006 |
DBLP DOI BibTeX RDF |
Nano-computing, Minority Gate, Quantum-dot Cellular Automata |
45 | Debjit Sinha, Hai Zhou 0001, Chris C. N. Chu |
Optimal gate sizing for coupling-noise reduction. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
coupling-noise, gate-sizing, lattice theory, fixpoint |
45 | Zbigniew Palmowski, Sabine Schlegel, Onno J. Boxma |
A Tandem Queue with a Gate Mechanism. |
Queueing Syst. Theory Appl. |
2003 |
DBLP DOI BibTeX RDF |
gate mechanism, batch customers, access networks, tandem queue, collision resolution |
44 | Ghassan Al Hayek, Chantal Robach |
On the Adequacy of Deriving Hardware Test Data from the Behavioral Specification. |
EUROMICRO |
1996 |
DBLP DOI BibTeX RDF |
hardware test data, behavioral fault modeling, gate-level strategies, high-level fault detection, gate-level fault detection, design automation tools, generated test set, gate-level fault coverage, hardware description languages, hardware description languages, behavioral specification |
44 | Udo Mahlstedt, Jürgen Alt, Matthias Heinitz |
CURRENT: a test generation system for IDDQ testing. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults |
43 | Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy 0001 |
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram |
Dominant critical gate identification for power and yield optimization in logic circuits. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
low-vt, process variations, yield |
43 | Rafik S. Guindi, Farid N. Najm |
Design Techniques for Gate-Leakage Reduction in CMOS Circuits. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Shuo Huang, Omar Wing |
Gate matrix partitioning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1989 |
DBLP DOI BibTeX RDF |
|
43 | Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng |
Automatic synthesis of gate-level timed circuits with choice. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates |
42 | Mao Nakajima, Daisaku Seto, Minoru Watanabe |
A 937.5 ns multi-context holographic configuration with a 30.75 mus retention time. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Feng Liu, Jin He 0003, Yue Fu, Jinhua Hu, Wei Bian, Yan Song, Xing Zhang 0002, Mansun Chan |
Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
double-gate MOSFET, drain current, compact model |
41 | Ming-Hui Wang, Qun Wan, Zhisheng You |
A gate size estimation algorithm for data association filters. |
Sci. China Ser. F Inf. Sci. |
2008 |
DBLP DOI BibTeX RDF |
data association filter, gate size, optimal estimation |
41 | Fatih Hamzaoglu, Mircea R. Stan |
Circuit-level techniques to control gate leakage for sub-100nm CMOS. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
low power, MTCMOS, gate leakage, domino circuits |
41 | Tetsuya Uemura, Toshio Baba |
Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
tunnel transistor, multiple-valued T-gate, D-FF, NDR |
41 | L. F. Fuller, C. Kraaijenvanger |
Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
educational aids, p-well CMOS gate array, student run factory, microelectronic engineering program, wafer fabrication, logic design, integrated circuit design, integrated circuit design, CMOS logic circuits, logic arrays, teaching tool, integrated circuit manufacture, integrated circuit manufacturing, electronic engineering education |
40 | Chi-Shong Wang, Chingwei Yeh |
Performance-driven technology mapping with MSG partition and selective gate duplication. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
gate duplication, maximal super-gate, super-gate, dynamic programming, partition, matching, logic synthesis, directed acyclic graph, Technology mapping, covering |
40 | Yulius Denny Prabowo, Erick Fernando, Jullend Gate |
Evaluation of IT Governance with BAI Domain at Senior High School Using Cobit 5. |
ICIMTech |
2023 |
DBLP DOI BibTeX RDF |
|
40 | Renato Juliano Martins, Emil Marinov, M. Aziz Ben Youssef, Christina Kyrou, Mathilde Joubert, Constance Colmagro, Valentin Gâté, Colette Turbil, Pierre-Marie Coulon, Daniel Turover, Samira Khadir, Massimo Giudici, Charalambos Klitis, Marc Sorel, Patrice Genevet |
Metasurface-enhanced Light Detection and Ranging Technology. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
40 | James Gate, Iain A. Stewart |
The expressibility of fragments of Hybrid Graph Logic on finite digraphs. |
J. Appl. Log. |
2013 |
DBLP DOI BibTeX RDF |
|
40 | Benjamin Lefaudeux, Gwennael Gate, Fawzi Nashashibi |
Extended occupation grids for non-rigid moving objects tracking. |
ITSC |
2011 |
DBLP DOI BibTeX RDF |
|
40 | James Gate, Iain A. Stewart |
Frameworks for Logically Classifying Polynomial-Time Optimisation Problems. |
CSR |
2010 |
DBLP DOI BibTeX RDF |
|
40 | Gwennael Gate, Amaury Breheret, Fawzi Nashashibi |
Centralized fusion for fast people detection in dense environment. |
ICRA |
2009 |
DBLP DOI BibTeX RDF |
|
40 | Gwennael Gate, Fawzi Nashashibi |
An approach for robust mapping, detection, tracking and classification in dynamic environments. |
ICAR |
2009 |
DBLP BibTeX RDF |
|
40 | Gwennael Gate, Amaury Breheret, Fawzi Nashashibi |
Fast Pedestrian Detection in Dense Environment with a Laser Scanner and a Camera. |
VTC Spring |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Minoru Watanabe, Fuminori Kobayashi |
A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. |
ARC |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Minoru Watanabe, Fuminori Kobayashi |
A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III |
A novel approach for variation aware power minimization during gate sizing. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Kaushik Roy 0001, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici |
Double-Gate SOI Devices for Low-Power and High-Performance Applications. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Venkataraman Mahalingam, N. Ranganathan |
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Minoru Watanabe, Fuminori Kobayashi |
An Improved Dynamic Optically Reconfigurable Gate Array. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Minoru Watanabe, Fuminori Kobayashi |
An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
VGTA: Variation Aware Gate Timing Analysis. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
39 | David N. Abramson, Jordan D. Gray, Christopher M. Twigg, Paul E. Hasler |
Characteristics and programming of floating-gate pFET switches in an FPAA crossbar network. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Jing Huang 0001, Mariam Momenzadeh, Mehdi Baradaran Tahoori, Fabrizio Lombardi |
Design and characterization of an and-or-inverter (AOI) gate for QCA implementation. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
defect characterization, test, QCA |
39 | Ashok K. Murugavel, N. Ranganathan |
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka |
Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike, Hirokazu Yonezawa, Yoshiyuki Kawakami |
GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
Hot Carrier Effect, Gate level modeling, Gate level simulation, Circuit reliability simulation, VLSI |
38 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Design of Variable Input Delay Gates for Low Dynamic Power Circuits. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Minoru Watanabe, Fuminori Kobayashi |
A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip |
36 | Sheng Wei 0001, Saro Meguerdichian, Miodrag Potkonjak |
Gate-level characterization: foundations and hardware security applications. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
gate-level characterization, hardware Trojan horse, thermal conditioning, manufacturing variability |
36 | Lei Cheng 0001, Deming Chen, Martin D. F. Wong |
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Input vector control, gate replacement, leakage reduction |
36 | Lei Cheng 0001, Liang Deng, Deming Chen, Martin D. F. Wong |
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
gate replacement, input vector control, leakage reduction |
36 | Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand |
Delay Testing Viability of Gate Oxide Short Defects. |
J. Comput. Sci. Technol. |
2005 |
DBLP DOI BibTeX RDF |
gate oxide short (GOS), VLSI, delay testing, defect |
36 | Lin Yuan, Gang Qu 0001 |
Enhanced leakage reduction Technique by gate replacement. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
MLV, gate replacement, leakage reduction |
36 | Amit Agarwal 0001, Kaushik Roy 0001 |
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
diode, low leakage cache, SRAM, gate leakage |
36 | Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown |
Efficient techniques for gate leakage estimation. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
pattern-dependent, pattern-independent, estimation, leakage, gate leakage |
36 | Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj |
Post-route gate sizing for crosstalk noise reduction. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
crosstalk noise repair, gate sizing |
36 | Jaume Segura 0001, Carol de Benito, Antonio Rubio 0001, Charles F. Hawkins |
A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors. |
J. Electron. Test. |
1996 |
DBLP DOI BibTeX RDF |
fault modeling, physical defects, gate oxide short |
36 | Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru |
An iterative gate sizing approach with accurate delay evaluation. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
delay evaluation, linear program, iteration, gate sizing |
36 | Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama |
Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
quantum interference devices, MOS logic circuits, quantum device model, super pass gate, multiple-valued digital systems, VLSI devices, super pass transistor, multiple-valued VLSI systems, multiple-signal-level detection, multiple-valued universal logic module, multiple-valued image processing system, NMOS circuit, VLSI, multivalued logic circuits, semiconductor device models |
36 | R. Burgess, C. Wouters |
PARAGON: a new package for gate matrix layout synthesis. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
cell generation, gate-matrix layout, routing, simulated annealing, optimisation, placement, logic synthesis, physical design |
36 | Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun |
Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
static noise margin distribution, robust operation, active power, standby power distribution, double gate MOSFET, process variations, Cache memory |
36 | Yun Ye, Frank Liu 0001, Sani R. Nassif, Yu Cao 0001 |
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
atomistic simulations, line-edge roughness, non-rectangular gate, random dopant fluctuations, threshold variation, predictive modeling, SPICE simulation |
36 | Rafail Lashevsky, K. Takaara, M. Souma |
The efficiency of neuron-MOS transistors in threshold logic. |
Soft Comput. |
1999 |
DBLP DOI BibTeX RDF |
Neuron MOS-transistors, threshold gate with alterable parameters, threshold logic |
36 | Irith Pomeranz, Sudhakar M. Reddy |
Functional test generation for delay faults in combinational circuits. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation |
35 | Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy 0001 |
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Michael Walter Payton, Fat Duen Ho |
A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy 0001 |
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Himanshu Thapliyal, Nagarajan Ranganathan |
Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Vishal Khandelwal, Ankur Srivastava 0001 |
Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw |
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
Parameterized Non-Gaussian Variational Gate Timing Analysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Debjit Sinha, Hai Zhou 0001 |
Gate-size optimization under timing constraints for coupling-noise reduction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang |
Switching-activity driven gate sizing and Vth assignment for low power design. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001 |
Statistical gate delay calculation with crosstalk alignment consideration. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Narender Hanchate, Nagarajan Ranganathan |
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
34 | K. Narasimhulu, V. Ramgopal Rao |
Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Jayashree Sridharan, Tom Chen 0001 |
Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Himanshu Thapliyal, M. B. Srinivas |
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. |
Asia-Pacific Computer Systems Architecture Conference |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim |
Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. |
ISMVL |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi |
Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Supratik Chakraborty, Rajeev Murgai |
Complexity Of Minimum-Delay Gate Resizing. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
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