Search results for "Glitches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
132	Ki-Seok Chung, Taewhan Kim, C. L. Liu 0001	G-vector: A New Model for Glitch Analysis in Logic Circuits.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	synthesis, power estimation, logic circuits, glitches
104	Wieland Fischer, Berndt M. Gammel	Masking at Gate Level in the Presence of Glitches.	CHES	2005	DBLP DOI BibTeX RDF	random masking, masked logic circuits, Cryptanalysis, side-channel attacks, DPA, power analysis, logic circuits, digital circuits, masking, glitches
80	Stefan Mangard, Kai Schramm	Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations.	CHES	2006	DBLP DOI BibTeX RDF	Zero-Offset DPA, Zero-Input DPA, Delay Chains, AES, DPA, Masking, Glitches
78	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register transfer level power optimization with emphasis on glitch analysis and reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
78	Svetla Nikova, Vincent Rijmen, Martin Schläffer	Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches.	ICISC	2008	DBLP DOI BibTeX RDF	non-linear functions, Noekeon, DPA, sharing, S-box, masking, glitches
76	Xun Liu, Marios C. Papaefthymiou	Incorporation of input glitches into power macromodeling.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
63	Quang Dinh, Deming Chen, Martin D. F. Wong	A routing approach to reduce glitches in low power FPGAs.	ISPD	2009	DBLP DOI BibTeX RDF	glitch reduction, path balancing, fpgas, routing, low power
50	Lei Cheng 0001, Deming Chen, Martin D. F. Wong	GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches.	DAC	2007	DBLP DOI BibTeX RDF
50	Svetla Nikova, Christian Rechberger, Vincent Rijmen	Threshold Implementations Against Side-Channel Attacks and Glitches.	ICICS	2006	DBLP DOI BibTeX RDF	side-channel attacks, secret sharing, Masking
41	Katherine Shu-Min Li, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen	IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	oscillation ring (OR) test scheme, open faults, crosstalk glitches, IEEE P1500, wrapper cell design, stuck-at faults, delay faults, SOC testing, interconnect test
39	Zhimin Chen 0002, Syed Haider, Patrick Schaumont	Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects.	ISA	2009	DBLP DOI BibTeX RDF
39	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton	GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
39	Tomasz S. Czajkowski, Stephen Dean Brown	Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits.	DAC	2007	DBLP DOI BibTeX RDF
39	Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara	Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes.	DFT	2005	DBLP DOI BibTeX RDF
39	Stefan Mangard, Thomas Popp, Berndt M. Gammel	Side-Channel Leakage of Masked CMOS Gates.	CT-RSA	2005	DBLP DOI BibTeX RDF
39	Michele Favalli	"Victim Gate" Crosstalk Fault Model.	DFT	2004	DBLP DOI BibTeX RDF
39	Anand Raghunathan, Sujit Dey, Niraj K. Jha	High-level macro-modeling and estimation techniques for switching activity and power consumption.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
39	Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi	Glitch power minimization by selective gate freezing.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
37	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
37	Benoit Catteau, Pieter Rombouts, Ludo Weyten	A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC's.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Ricardo Ferreira, Anne-Marie Trullemans, José C. Costa, José Monteiro 0001	Probabilistic Bottom-Up RTL Power Estimation.	ISQED	2000	DBLP DOI BibTeX RDF	Register Tranfers Level, Power Estimation, Glitches, ZBDD
26	Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia Di	Glitch-free design for multi-threshold CMOS NCL circuits.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	asynchronous circuit, mtcmos, glitch, threshold gate, null convention logic
26	Denis Réal, Cécile Canovas, Jessy Clédière, M'hamed Drissi, Frédéric Valette	Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis.	DATE	2008	DBLP DOI BibTeX RDF
26	Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal	Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
26	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton	GlitchLess: an active glitch minimization technique for FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	field-programmable gate arrays, power minimization
26	Hanif Fatemi, Shahin Nazarian, Massoud Pedram	A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms.	ASP-DAC	2007	DBLP DOI BibTeX RDF
26	Kathi Fisler	Two-Dimensional Regular Expressions for Compositional Bus Protocols.	FMCAD	2007	DBLP DOI BibTeX RDF
26	Natasa Miskov-Zivanov, Diana Marculescu	Circuit Reliability Analysis Using Symbolic Techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
26	Fei Hu, Vishwani D. Agrawal	Input-specific dynamic power optimization for VLSI circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	dynamic power optimization, glitch reduction, input specific
26	Zhimin Chen, Yujie Zhou	Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage.	CHES	2006	DBLP DOI BibTeX RDF	Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA
26	Natasa Miskov-Zivanov, Diana Marculescu	MARS-C: modeling and reduction of soft errors in combinational circuits.	DAC	2006	DBLP DOI BibTeX RDF	reliability symbolic techniques, SER
26	Fei Hu, Vishwani D. Agrawal	Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis.	ICCD	2005	DBLP DOI BibTeX RDF
26	Alex Gyure, Alireza Kasnavi, Sam C. Lo, Peivand F. Tehrani, William Shu, Mahmoud Shahram, Joddy W. Wang, Jindrich Zejda	Noise Library Characterization for Large Capacity Static Noise Analysis Tools.	ISQED	2005	DBLP DOI BibTeX RDF
26	Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald	Successfully Attacking Masked AES Hardware Implementations.	CHES	2005	DBLP DOI BibTeX RDF
26	Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis	A Static Low-Power, High-Performance 32-bit Carry Skip Adder.	DSD	2004	DBLP DOI BibTeX RDF
26	Katherine Shu-Min Li, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen	A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
26	Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis	A Low-Power Carry Skip Adder with Fast Saturation.	ASAP	2004	DBLP DOI BibTeX RDF
26	Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia 0001	Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.	PATMOS	2002	DBLP DOI BibTeX RDF
26	Henrik Eriksson, Per Larsson-Edefors	Impact of Voltage Scaling on Glitch Power Consumption.	PATMOS	2000	DBLP DOI BibTeX RDF
26	Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi	Glitch Power Minimization by Gate Freezing.	DATE	1999	DBLP DOI BibTeX RDF
26	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Robust Sequential Fault Testing of Iterative Logic Arrays.	VTS	1997	DBLP DOI BibTeX RDF	Sequential Faults, Linear-testability, Fault Modeling, Automatic Test Generation, C-testability, Iterative Logic Arrays
26	Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya	CMOS Stuck-open Fault Detection Using Single Test Patterns.	DAC	1989	DBLP DOI BibTeX RDF
24	Bingbin Liu, Jordan T. Ash, Surbhi Goel, Akshay Krishnamurthy, Cyril Zhang	Exposing Attention Glitches with Flip-Flop Language Modeling.	CoRR	2023	DBLP DOI BibTeX RDF
24	Elena Simona Apostol, Ciprian-Octavian Truica	Efficient Machine Learning Ensemble Methods for Detecting Gravitational Wave Glitches in LIGO Time Series.	CoRR	2023	DBLP DOI BibTeX RDF
24	Tiago S. Fernandes, Samuel J. Vieira, António Onofre, Juan Calderón Bustillo, Alejandro Torres-Forné, José A. Font	Convolutional Neural Networks for the classification of glitches in gravitational-wave data streams.	CoRR	2023	DBLP DOI BibTeX RDF
24	Mohammad Reza Taesiri, Tianjun Feng, Cor-Paul Bezemer, Anh Nguyen 0002	GlitchBench: Can large multimodal models detect video game glitches?	CoRR	2023	DBLP DOI BibTeX RDF
24	Ahmad Faza, John Leth, Arnfinn Aas Eielsen	Criterion for Sufficiently Large Dither Amplitude to Mitigate Non-linear Glitches.	CCTA	2023	DBLP DOI BibTeX RDF
24	Ahmad Faza, John Leth, Arnfinn Aas Eielsen	Mitigating Non-linear DAC Glitches Using Dither in Closed-loop Nano-positioning Applications.	ACC	2023	DBLP DOI BibTeX RDF
24	Stanislav Lyakhov, Vincent Immler	Analysis of Arbitrary Waveform Generation for Voltage Glitches.	FDTC	2023	DBLP DOI BibTeX RDF
24	Bingbin Liu, Jordan T. Ash, Surbhi Goel, Akshay Krishnamurthy, Cyril Zhang	Exposing Attention Glitches with Flip-Flop Language Modeling.	NeurIPS	2023	DBLP BibTeX RDF
24	Elena Simona Apostol, Ciprian-Octavian Truica	Efficient Machine Learning Ensemble Methods for Detecting Gravitational Wave Glitches in LIGO Time Series.	ICCP	2023	DBLP DOI BibTeX RDF
24	Sivaramakrishnan Sankarapandian, Brian Kulis	$β$-Annealed Variational Autoencoder for glitches.	CoRR	2021	DBLP BibTeX RDF
24	Oscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek	A digital switching scheme to reduce DAC glitches using code-dependent randomization.	NorCAS	2021	DBLP DOI BibTeX RDF
24	Yanbin Li, Ming Tang 0002, Yuguang Li, Huanguo Zhang	A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs.	Integr.	2020	DBLP DOI BibTeX RDF
24	Shlomo Engelberg, Osnat Keren	Constructive Bounds on the Capacity of Parallel Asynchronous Skew-Free Channels With Glitches.	IEEE Trans. Inf. Theory	2020	DBLP DOI BibTeX RDF
24	Arnfinn Aas Eielsen, John Leth, Andrew J. Fleming, Adrian G. Wills, Brett Ninness	Large-Amplitude Dithering Mitigates Glitches in Digital-to-Analogue Converters.	IEEE Trans. Signal Process.	2020	DBLP DOI BibTeX RDF
24	Vittorio Zaccaria	An F-algebra for analysing information leaks in the presence of glitches.	IACR Cryptol. ePrint Arch.	2020	DBLP BibTeX RDF
24	Corey Brian Jackson, Carsten S. Østerlund, Kevin Crowston, Mahboobeh Harandi, Sarah Allen, Sara Bahaadini, Scotty Coughlin, Vicky Kalogera, Aggelos K. Katsaggelos, Shane L. Larson, Neda Rohani, Joshua R. Smith 0003, Laura Trouille, Michael Zevin	Teaching citizen scientists to categorize glitches using machine learning guided training.	Comput. Hum. Behav.	2020	DBLP DOI BibTeX RDF
24	Tadahiro Nishiguchi	Transcriptional Characteristics of Quadrant Glitches on Machined Surface - Influence of Tool Diameter and Feed Rate -.	Int. J. Autom. Technol.	2020	DBLP DOI BibTeX RDF
24	Carlos García Ling, Konrad Tollmar, Linus Gisslén	Using Deep Convolutional Neural Networks to Detect Rendered Glitches in Video Games.	AIIDE	2020	DBLP BibTeX RDF
24	Stefano Gualeni	On the de-familiarizing and re-ontologizing effects of glitches and glitch-alikes.	DiGRA Conference	2019	DBLP BibTeX RDF
24	Raphael Kim, Roland van Dierendonck, Stefan Poslad	Moldy Ghosts and Yeasty Invasions: Glitches in Hybrid Bio-Digital Games.	CHI Extended Abstracts	2019	DBLP DOI BibTeX RDF
24	Antti Tenhiälä, Manus Johnny Rungtusanatham, Jason W. Miller	ERP System versus Stand-Alone Enterprise Applications in the Mitigation of Operational Glitches.	Decis. Sci.	2018	DBLP DOI BibTeX RDF
24	Rafael Nogueras, Carlos Cotta	Analyzing Resilience to Computational Glitches in Island-Based Evolutionary Algorithms.	PPSN (1)	2018	DBLP DOI BibTeX RDF
24	Roderick Bloem, Hannes Groß, Rinat Iusupov, Bettina Könighofer, Stefan Mangard, Johannes Winter	Formal Verification of Masked Hardware Implementations in the Presence of Glitches.	EUROCRYPT (2)	2018	DBLP DOI BibTeX RDF
24	Roderick Bloem, Hannes Groß, Rinat Iusupov, Bettina Könighofer, Stefan Mangard, Johannes Winter	Formal Verification of Masked Hardware Implementations in the Presence of Glitches.	IACR Cryptol. ePrint Arch.	2017	DBLP BibTeX RDF
24	Michael Meixner, Tobias G. Noll	Accurate Estimation of CMOS Power Consumption Considering Glitches by Using Waveform Lookup.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
24	Jungwoo Joh, Yezee Seo, Hoon-Kyu Kim, Taekyoung Kwon 0002	Glitch Recall: A Hardware Trojan Exploiting Natural Glitches in Logic Circuits.	WISA	2017	DBLP DOI BibTeX RDF
24	Shlomo Engelberg, Osnat Keren	Reliable Communication Across Parallel Asynchronous Channels with Glitches.	ICMCTA	2017	DBLP DOI BibTeX RDF
24	Ciro D'Urso	EXPERIENCE: Glitches in Databases, How to Ensure Data Quality by Outlier Detection Techniques.	ACM J. Data Inf. Qual.	2016	DBLP DOI BibTeX RDF
24	Herwig Wendt, Nicolas Dobigeon, Jean-Yves Tourneret, Mathieu Albinet, Christophe Goldstein, Nadia Karouche	Detection and Correction of Glitches in a Multiplexed Multichannel Data Stream - Application to the MADRAS Instrument.	IEEE Trans. Geosci. Remote. Sens.	2016	DBLP DOI BibTeX RDF
24	Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath	Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur.	IEICE Electron. Express	2016	DBLP DOI BibTeX RDF
24	Charlotte A. L. Haley	Mathematical physics: Glitches in time.	Nat.	2016	DBLP DOI BibTeX RDF
24	Yan Peng, Ian W. Jones, Mark R. Greenstreet	Finding Glitches Using Formal Methods.	ASYNC	2016	DBLP DOI BibTeX RDF
24	Laure Berti-Équille, Ji Meng Loh, Tamraparni Dasu	A masking index for quantifying hidden glitches.	Knowl. Inf. Syst.	2015	DBLP DOI BibTeX RDF
24	Honorio Martín, Thomas Korak, Enrique San Millán, Michael Hutter	Fault Attacks on STRNGs: Impact of Glitches, Temperature, and Underpowering on Randomness.	IEEE Trans. Inf. Forensics Secur.	2015	DBLP DOI BibTeX RDF
24	Stephen Longfield Jr., Brittany Nkounkou, Rajit Manohar, Ross Tate	Preventing glitches and short circuits in high-level self-timed chip specifications.	PLDI	2015	DBLP DOI BibTeX RDF
24	Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Bruno Robisson	Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter.	HOST	2014	DBLP DOI BibTeX RDF
24	Michael Meixner, Tobias G. Noll	Limits of gate-level power estimation considering real delay effects and glitches.	ISSoC	2014	DBLP DOI BibTeX RDF
24	Ji Meng Loh, Tamraparni Dasu	Auditing data streams for correlated glitches.	Int. J. Inf. Qual.	2013	DBLP DOI BibTeX RDF
24	Tamraparni Dasu	Data Glitches: Monsters in Your Data.	Handbook of Data Quality	2013	DBLP DOI BibTeX RDF
24	Laure Berti-Équille, Ji Meng Loh, Tamraparni Dasu	A Masking Index for Quantifying Hidden Glitches.	ICDM	2013	DBLP DOI BibTeX RDF
24	Koichi Shimizu, Daisuke Suzuki, Tomomi Kasuya	Glitch PUF: Extracting Information from Usually Unwanted Glitches.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
24	Ryuta Sato	Generation Mechanism of Quadrant Glitches and Compensation for it in Feed Drive Systems of NC Machine Tools.	Int. J. Autom. Technol.	2012	DBLP DOI BibTeX RDF
24	Svetla Nikova, Vincent Rijmen, Martin Schläffer	Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches.	J. Cryptol.	2011	DBLP DOI BibTeX RDF
24	Emmanuel Prouff, Thomas Roche	Higher-Order Glitches Free Implementation of the AES using Secure Multi-Party Computation.	IACR Cryptol. ePrint Arch.	2011	DBLP BibTeX RDF
24	Ji Meng Loh, Tamraparni Dasu	Auditing data streams for correlated glitches.	ICIQ	2011	DBLP BibTeX RDF
24	Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede	An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs.	FDTC	2011	DBLP DOI BibTeX RDF
24	Emmanuel Prouff, Thomas Roche	Higher-Order Glitches Free Implementation of the AES Using Secure Multi-party Computation Protocols.	CHES	2011	DBLP DOI BibTeX RDF
24	Da-Cheng Juan, Yu-Ting Chen, Ming-Chao Lee, Shih-Chieh Chang	An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
24	Quang Dinh, Deming Chen, Martin D. F. Wong	A Routing Approach to Reduce Glitches in Low Power FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
24	Xenophon Koufteros, Greg Rawski, Rupak Rauniar	Organizational Integration for Product Development: The Effects on Glitches, On-Time Execution of Engineering Change Orders, and Market Success.	Decis. Sci.	2010	DBLP DOI BibTeX RDF
24	Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier	Fault diagnosis of crosstalk induced glitches and delay faults.	DDECS	2010	DBLP DOI BibTeX RDF
24	Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier	Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults.	VLSI Design	2010	DBLP DOI BibTeX RDF	Switching Windows, Test Set Compaction, Automatic Test Pattern Generation, Crosstalk Faults
24	Monjur Alam, Santosh Ghosh, M. J. Mohan, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta 0001	Effect of glitches against masked AES S-box implementation and countermeasure.	IET Inf. Secur.	2009	DBLP DOI BibTeX RDF
24	Jins D. Alexander, Vishwani D. Agrawal	Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations.	ISVLSI	2009	DBLP DOI BibTeX RDF
24	Amir Moradi 0001, Mahmoud Salmasizadeh, Mohammad Taghi Manzuri Shalmani	On the Importance of the Number of Fanouts to Prevent the Glitches in DPA-Resistant Devices.	CSICC	2008	DBLP DOI BibTeX RDF
24	Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Cheng Chia Lo	Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware.	DATE	2007	DBLP DOI BibTeX RDF
24	Minjin Zhang, Xiaowei Li 0001	Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects.	ATS	2007	DBLP DOI BibTeX RDF
24	Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-Chieh Chang	An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon.	ICCAD	2007	DBLP DOI BibTeX RDF