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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3962 occurrences of 1873 keywords
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Results
Found 7741 publication records. Showing 7739 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
153 | Kwang-Ting Cheng |
Partial scan designs without using a separate scan clock. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock |
123 | Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen |
Peak-power reduction for multiple-scan circuits during test application. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing |
116 | Yu Huang 0005, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li |
Survey of Scan Chain Diagnosis. |
IEEE Des. Test Comput. |
2008 |
DBLP DOI BibTeX RDF |
|
106 | Abhijit Jas, Bahram Pouya, Nur A. Touba |
Virtual Scan Chains: A Means for Reducing Scan Length in Cores. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
Compression/Decompression, Virtual Scan, Built-In Self-Test, Mapping, Design-for-Testability, LFSR, System Integrator, Integrated Circuits, Integrated Circuits, Scan Chains, Embedded Cores, Digital Testing, Reseeding |
102 | Kuen-Jong Lee, Tsung-Chu Huang |
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. |
J. Electron. Test. |
2002 |
DBLP DOI BibTeX RDF |
multiple scan chains, interleaving scan, test power reduction, peak power reduction |
101 | Xijiang Lin, Yu Huang 0005 |
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells. |
J. Electron. Test. |
2008 |
DBLP DOI BibTeX RDF |
Scan shift, Low power test, Scan test, Signal probability |
101 | Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen |
Cost-free scan: a low-overhead scan path design methodology. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
Testing, DFT, Scan design |
96 | Dong Xiang, Mingjing Chen, Hideo Fujiwara |
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
Random testability, scan enable signal, weighted random testing, scan-based BIST |
96 | Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita |
Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
scan tree, logic testing, design for testability, sequential circuit |
92 | Robert B. Norwood, Edward J. McCluskey |
Synthesis-for-scan and scan chain ordering. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications |
90 | Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen |
Cost-free scan: a low-overhead scan path design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
87 | Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita |
Partial scan design and test sequence generation based on reduced scan shift method. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
partial scan circuit, short test sequence, reduced scan shift, scan design, test sequence generation |
86 | Subhrajit Bhattacharya, Sujit Dey |
H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology |
85 | Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam |
A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
85 | Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy |
Multiple Scan Tree Design with Test Vector Modification. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
85 | Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy |
On reducing test application time for scan circuits using limited scan operations and transfer sequences. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
85 | Dong Xiang, Kaiwei Li, Hideo Fujiwara |
Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
85 | Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita |
Reducing Scan Shifts Using Folding Scan Trees. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
84 | Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu |
A cost-effective scan architecture for scan testing with non-scan test power and test application cost. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
|
83 | Irith Pomeranz, Sudhakar M. Reddy |
Reducing test application time for full scan circuits by the addition of transfer sequences. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
transfer sequences, primary input vectors, scan-in operation, scan-out operation, static compaction procedure, compaction levels, fault diagnosis, logic testing, design for testability, fault detection, automatic testing, boundary scan testing, test set, test application time, full scan circuits |
80 | Dong Xiang, Mingjing Chen, Jia-Guang Sun |
Scan BIST with biased scan test signals. |
Sci. China Ser. F Inf. Sci. |
2008 |
DBLP DOI BibTeX RDF |
random testability, test signal, biased random testing, scan-based BIST |
80 | Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara |
Improving test effectiveness of scan-based BIST by scan chain partitioning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
80 | Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita |
On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure. |
DELTA |
2004 |
DBLP DOI BibTeX RDF |
|
80 | Irith Pomeranz, Sudhakar M. Reddy |
On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
78 | Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda |
Scan insertion criteria for low design impact. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan |
76 | Ozgur Sinanoglu |
Low Cost Scan Test by Test Correlation Utilization. |
J. Comput. Sci. Technol. |
2007 |
DBLP DOI BibTeX RDF |
test correlation, scan architecture design, test data compression, scan-based testing |
76 | Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee |
Functional Scan Chain Testing. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
functional scan chain, alternating sequence, scan chain testing, design for testability, test point insertion |
76 | Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara |
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
Scan forest, test application cost, test data volume, test power |
76 | Nur A. Touba, Edward J. McCluskey |
Applying two-pattern tests using scan-mapping. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
scan-mapping, combinational mapping logic, logic testing, built-in self test, built-in self-testing, fault coverage, delay faults, pseudo-random testing, deterministic testing, two-pattern tests |
75 | Geewhun Seok, Il-soo Lee, Tony Ambler, Baxter F. Womack |
An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
|
75 | Abhijit Jas, Bahram Pouya, Nur A. Touba |
Test data compression technique for embedded cores using virtual scan chains. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
75 | Irith Pomeranz |
Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
73 | Hao Zheng, Kewal K. Saluja, Rajiv Jain |
Test application time reduction for scan based sequential circuits. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
scan based sequential circuits, single clock configuration, nonscan flip-flops, test vector length, nonatomic two-clock scan method, test generation environment, logic testing, sequential circuits, flip-flops, clocks, partial scan, boundary scan testing, test application time |
73 | Sridhar Narayanan, Melvin A. Breuer |
Asynchronous multiple scan chain. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
asynchronous multiple scan chains, scan flip-flops, control complexity, I/O pin count, DFT method, logic IC, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, flip-flops, integrated logic circuits, scan designs, boundary scan testing, test application time |
72 | Seiken Yano |
Unified scan design with scannable memory arrays. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits |
71 | Ozgur Sinanoglu |
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations. |
J. Electron. Test. |
2008 |
DBLP DOI BibTeX RDF |
Test power reduction, Scan power reduction, Serial transformations, Scan chain modification, Design for testability, Core-based testing |
71 | Elizabeth M. Rudnick, Janak H. Patel |
A genetic approach to test application time reduction for full scan and partial scan circuits. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
partial scan circuits, design-for-testability techniques, compact test set generation, genetic algorithms, genetic algorithms, logic testing, design for testability, logic design, sequential circuits, combinational circuits, DFT, flip-flops, test application time reduction, full scan circuits |
71 | Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie 0001 |
Scan-chain design and optimization for three-dimensional integrated circuits. |
ACM J. Emerg. Technol. Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
scan-chain design, genetic algorithm, integer linear programming, randomized rounding, LP relaxation, 3D ICs |
71 | Min Gyung Kang, Juan Caballero, Dawn Xiaodong Song |
Distributed Evasive Scan Techniques and Countermeasures. |
DIMVA |
2007 |
DBLP DOI BibTeX RDF |
scan detection, distributed scanning, information-hiding, evasion |
70 | Zhen Chen, Dong Xiang, Boxue Yin |
A power-effective scan architecture using scan flip-flops clustering and post-generation filling. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
test, low power, design for test, scan design |
70 | Hideo Fujiwara, Akihiro Yamamoto |
Parity-scan design to reduce the cost of test application. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
70 | Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia |
VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
scan-based DFT, security, detection probability, low overhead, cryptographic hardware |
70 | Dong Xiang, Ming-Jing Chen, Kaiwei Li, Yu-Liang Wu |
Scan-Based BIST Using an Improved Scan Forest Architecture. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
70 | Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara |
Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
69 | Irith Pomeranz, Sudhakar M. Reddy |
Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
67 | Seongmoon Wang, Wenlong Wei |
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
peak current reduction, average power dissipation, clock tree construction, special scan cells, scan chain reordering, ATPG, scan designs |
67 | Kee Sup Kim, Charles R. Kime |
Partial scan flip-flop selection by use of empirical testability. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
scan flip-flop selection, serial scan, design for testability, testability, partial scan |
67 | Samantha Edirisooriya, Geetani Edirisooriya |
Diagnosis of scan path failures. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
scan path failures, scan based diagnostic schemes, faulty circuits, logic circuitry, scan chain fault diagnosis, fault diagnosis, logic testing, integrated circuit testing, design for testability, combinational circuits, integrated logic circuits |
66 | Yong-sheng Cheng, Zhiqiang You, Jishun Kuang |
Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
full scan testing, scan tree, routing complexity, test response data volume, design-for-testability |
66 | Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita |
Test sequence compaction by reduced scan shift and retiming. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
reduced scan shift, full scan designed circuits, computational complexity, logic testing, timing, transformation, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction |
66 | Prab Varma, Tushar Gheewala |
The economics of scan-path design for testability. |
J. Electron. Test. |
1994 |
DBLP DOI BibTeX RDF |
state retention problem, Design for testability, scan, partial scan, test economics, life-cycle costs |
66 | Sunghoon Chun, Taejin Kim, YongJoon Kim, Sungho Kang 0001 |
An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
Scan chain based test, Diagnosis, Symbolic Simulation |
65 | Dong Xiang, Ming-Jing Chen, Hideo Fujiwara |
Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
Test signal, random testability, weighted random testing, scan-based BIST |
65 | Wei Li 0023, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy |
Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
65 | Michael Cogswell, Shazia Mardhani, Kevin Melocco, Hina Arora |
A Structured Graphical Tool for Analyzing Boundary Scan Violations. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
65 | Soo Young Lee, Kewal K. Saluja |
Test application time reduction for sequential circuits with scan. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
65 | Irith Pomeranz, Sudhakar M. Reddy |
Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
65 | Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li 0036, Krishnendu Chakrabarty |
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
65 | Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
65 | Ozgur Sinanoglu, Alex Orailoglu |
Modeling Scan Chain Modifications For Scan-in Test Power Minimization. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
64 | Nicola Nicolici, Bashir M. Al-Hashimi |
Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
61 | Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li |
Layout-aware scan chain reorder for launch-off-shift transition test coverage. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
scan chain ordering, test generation, transition faults, Scan test |
61 | Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch |
Power-Driven Routing-Constrained Scan Chain Design. |
J. Electron. Test. |
2004 |
DBLP DOI BibTeX RDF |
scan chain design, DfT, low power testing, scan testing |
61 | Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier |
Enhanced Reduced Pin-Count Test for Full-Scan Design. |
J. Electron. Test. |
2002 |
DBLP DOI BibTeX RDF |
reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test |
61 | Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic |
Securing Designs against Scan-Based Side-Channel Attacks. |
IEEE Trans. Dependable Secur. Comput. |
2007 |
DBLP DOI BibTeX RDF |
Security and Privacy Protection, Scan-Based Design, Secure Design, Reliability and Testing |
61 | Lanjia Wang, Hai-Xin Duan, Xing Li 0001 |
Port Scan Behavior Diagnosis by Clustering. |
ICICS |
2005 |
DBLP DOI BibTeX RDF |
port scan detection, clustering, network security |
61 | Bo Yang 0010, Kaijie Wu 0001, Ramesh Karri |
Secure scan: a design-for-test architecture for crypto chips. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
crypto hardware, scan-based DFT, security, testability |
61 | Xiaodong Zhang 0010, Kaushik Roy 0001 |
Power Reduction in Test-Per-Scan BIST. |
IOLTW |
2000 |
DBLP DOI BibTeX RDF |
Test-per-scan, Low Power BIST, Testing, Low Power, BIST, Weighted Random Pattern |
61 | Jayabrata Ghosh-Dastidar, Nur A. Touba |
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
built-in self-test Scan Chains, Design-for-Diagnosis, Multi-Input Signature Register, Design-for-Testability, LFSR, Integrated Circuits, Integrated Circuits, Digital Testing, Design-for-Debug |
61 | Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik |
Integration of partial scan and built-in self-test. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
test points, built-in self-test, design for testability, partial scan |
60 | Yu-Ze Wu, Mango Chia-Tso Chao |
Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
signal transitions, correlation, reordering, scan-chain |
60 | Xiaoxia Wu, Paul Falkenstern, Yuan Xie 0001 |
Scan chain design for three-dimensional integrated circuits (3D ICs). |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
60 | Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi |
ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
60 | Nisar Ahmed, Mohammad Tehranipoor |
Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique. |
DFT |
2005 |
DBLP DOI BibTeX RDF |
|
60 | Irith Pomeranz, Sudhakar M. Reddy |
Autoscan: a scan design without external scan inputs or outputs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
60 | Shih Ping Lin 0001, Chung-Len Lee 0001, Jwu E. Chen |
A Scan Matrix Design for Low Power Scan-Based Test. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
60 | Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy 0001 |
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
60 | Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici |
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
60 | Seongmoon Wang, Xiao Liu, Srimat T. Chakradhar |
Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
60 | Irith Pomeranz |
Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
60 | Sandeep Bhatia, Niraj K. Jha |
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
56 | Roberto Bevacqua, Luca Guerrazzi, Franco Fummi |
SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation. |
EUROMICRO |
1996 |
DBLP DOI BibTeX RDF |
test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences |
56 | Hardy J. Pottinger, Chien-Yuh Lin |
Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education |
56 | Arun Balakrishnan, Srimat T. Chakradhar |
Partial scan design for technology mapped circuits. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
technology mapped circuits, scan flip-flops selection, multiple memory elements, library block, integer linear program formulation, production VLSI circuits, VLSI, graph theory, linear programming, design for testability, integer programming, logic design, logic CAD, VLSI design, flip-flops, integrated circuit design, circuit CAD, integrated logic circuits, functional specifications, partial scan design |
56 | Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos |
Efficient partial scan cell gating for low-power scan-based testing. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
partial gating, scan cell gating, Low-power testing, scan-based testing |
56 | Lifeng He, Yuyan Chao, Kenji Suzuki 0001, Hidenori Itoh |
A Run-Based One-Scan Labeling Algorithm. |
ICIAR |
2009 |
DBLP DOI BibTeX RDF |
label equivalence, raster scan, connected component, run-length encoding, Labeling algorithm |
56 | Hong-Sik Kim, Sungho Kang 0001, Michael S. Hsiao |
A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment. |
J. Electron. Test. |
2008 |
DBLP DOI BibTeX RDF |
Keyword System on a chip, Test compression, Low power testing, Scan testing |
56 | Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
Faults in scan cells, stuck-at and stuck-on faults |
56 | Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding |
Scan chain clustering for test power reduction. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
test, low power, design for test, scan design |
56 | Wei-Lun Wang, Kuen-Jong Lee |
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment. |
J. Electron. Test. |
2002 |
DBLP DOI BibTeX RDF |
mixed-mode pattern generation, built-in self-test, power consumption, test application time, scan chain |
56 | Sandeep Bhatia, Prab Varma |
Test Compaction in a Parallel Access Scan Environment. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
Test Vector Compaction, Design for Testability, Scan |
56 | Sándor P. Fekete, Joseph S. B. Mitchell, Christiane Schmidt 0001 |
Minimum Covering with Travel Cost. |
ISAAC |
2009 |
DBLP DOI BibTeX RDF |
|
56 | Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang |
Broadcasting test patterns to multiple circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
55 | Zhen Chen, Boxue Yin, Dong Xiang |
Conflict driven scan chain configuration for high transition fault coverage and low test power. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
55 | Fei Wang, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001 |
A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
55 | Xiaoding Chen, Michael S. Hsiao |
An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Li Zhang 0006, Wen Gao 0001, Qiang Wang 0011, Debin Zhao |
Macroblock-Level Adaptive Scan Scheme for Discrete Cosine Transform Coefficients. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Irith Pomeranz, Sudhakar M. Reddy |
Improved n-Detection Test Sequences Under Transparent Scan. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
55 | Yu Huang 0005, Keith Gallie |
Diagnosis of defects on scan enable and clock trees. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
55 | Minsik Cho, David Z. Pan |
PEAKASO: Peak-Temperature Aware Scan-Vector Optimization. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
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