Search results for "HDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
89	Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee	PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations.	CASES	2002	DBLP DOI BibTeX RDF	FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization
87	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	Functional vector generation for HDL models using linearprogramming and Boolean satisfiability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
87	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
67	Lin Yuan, Pushkin R. Pari, Gang Qu 0001	Soft IP Protection: Watermarking HDL Codes.	Information Hiding	2004	DBLP DOI BibTeX RDF
67	Gunther Lehmann, Bernhard Wunder, Klaus D. Müller-Glaser	Basic concepts for an HDL reverse engineering tool-set.	ICCAD	1996	DBLP DOI BibTeX RDF	VHDL Verilog Hardware Description Reuse Reverse Engineering Hypertext CASE Visualization Productivity Design Process Analysis Control Flow ADA Graphical Symbol, VHDL
62	Jian Li 0061, Rajesh K. Gupta 0001	Decomposition of timed decision tables and its use in presynthesis optimizations.	ICCAD	1997	DBLP DOI BibTeX RDF	TDT decomposition, behavioral HDL description, kernel extraction algorithm, optimized HDL description, presynthesis optimizations, system behavior model, timed decision table decomposition, benchmarks, decision tables, circuit synthesis
60	Chien-Nan Jimmy Liu, Jing-Yang Jou	An Efficient Functional Coverage Test for HDL Descriptions at RTL.	ICCD	1999	DBLP DOI BibTeX RDF	verification, coverage, FSM, HDL
58	Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu	A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs.	ASP-DAC	1999	DBLP DOI BibTeX RDF
50	Marco Ottavi, Luca Schiano, Fabrizio Lombardi, Douglas Tougaw	HDLQ: A HDL environment for QCA design.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	CAD, fault injection, QCA, HDL
49	Herbert Dawid, Klaus-Jürgen Koch, Johannes Stahl 0004	ADPCM codec: from system level description to versatile HDL model.	ASAP	1997	DBLP DOI BibTeX RDF	differential pulse code modulation, ADPCM codec, system level description, versatile HDL model, architectural design exploration, fast system simulation, adaptive differential pulse code modulation codec module, power analysis, design verification, behavioral synthesis, design reuse, system complexity, design constraints
48	Majid Ahmadi, Ashkan Hosseinzadeh Namin, Karl Leboeuf, Huapeng Wu	Artificial neural networks activation function HDL coder.	EIT	2009	DBLP DOI BibTeX RDF
48	Ronny Frevert, Steffen Rülke, Torsten Schäfer, Frank Dresig	Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement Analysis.	DSD	2002	DBLP DOI BibTeX RDF
48	Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum, Michael I. Ferguson	On Two New Trends in Evolvable Hardware: Employment of HDL-Based Structuring, and Design of Multi-Functional Circuits.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
48	Klaus Hofmann, Manfred Glesner, Nicu Sebe, Anca Manuela Manolescu, Santiago Marco, Josep Samitier, Jean-Michel Karam, Bernard Courtois	Generation of the HDL-A-model of a micromembrane from its finite-element-description.	ED&TC	1997	DBLP DOI BibTeX RDF
42	Makarand Joshi, Hideaki Kobayashi	Quantifying design productivity: an effort distribution analysis.	EURO-DAC	1995	DBLP DOI BibTeX RDF	design productivity, effort-distribution, graphical HDL, textual HDL, human interaction, ISO 9000, design resources, design quality
41	Jens Horstmannshoff, Thorsten Grötker, Heinrich Meyr	Mapping multirate dataflow to complex RT level hardware models.	ASAP	1997	DBLP DOI BibTeX RDF	multirate dataflow mapping, complex RT level hardware models, digital signal processing systems, algorithm development phase, data flow specification, RTL target architecture, HDL code generation, cycle based timing model, ASIC design complexity, multirate dataflow graphs, signal processing, hardware architecture
41	H. Fatih Ugurdag, Thomas E. Fuhrman	Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath.	ICCD	1996	DBLP DOI BibTeX RDF	Autocircuit, clock edge general behavioral synthesis system, physical datapaths, next-generation synthesis tool, behavioral HDL input descriptions, data-flow representations, use-trees, raw-states, word-oriented synthesis, unique parameterized netlist representation, high level synthesis, high-level design
40	Peter A. Jamieson, Kenneth B. Kent	Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, verilog hdl
39	Eoin Creedon, Michael Manzke	Scalable high performance computing on FPGA clusters using message passing.	FPL	2008	DBLP DOI BibTeX RDF
39	Alex K. Jones, Prithviraj Banerjee	An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
39	Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada	Comparative Study On Verilog-Based And C-Based Hardware Design Education.	MSE	2003	DBLP DOI BibTeX RDF
39	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	OCCOM-efficient computation of observability-based code coveragemetrics for functional verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
39	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification.	DAC	1998	DBLP DOI BibTeX RDF	high-level synthesis, telecommunication
38	Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti 0001, Vivekananda M. Vedula, K. S. Maneperambil	Automatic Constraint Based Test Generation for Behavioral HDL Models.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
38	Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Synthesizable HDL generation method for configurable VLIW processors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
38	Liang Zhang 0012, Michael S. Hsiao, Indradeep Ghosh	Automatic Design Validation Framework for HDL Descriptions via RTL ATPG.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
38	Rolf Drechsler, Nicole Drechsler	GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages.	EvoWorkshops	2003	DBLP DOI BibTeX RDF
38	Arash Saifhashemi, Hossein Pedram	Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction.	DAC	2003	DBLP DOI BibTeX RDF	CHP, PLI, CSP, asynchronous circuits, channel, verilog
38	Hen-Ming Lin, Jing-Yang Jou	On tri-state buffer inference in HDL synthesis.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
38	Wen-Jong Fang, Allen C.-H. Wu	Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
38	Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos	Automatic verification of implementations of large circuits against HDL specifications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
38	Rainer Leupers, Peter Marwedel	Retargetable generation of code selectors from HDL processor models.	ED&TC	1997	DBLP DOI BibTeX RDF
38	Timothy Kam, P. A. Subrahmanyam	Comparing layouts with HDL models: a formal verification technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
37	Saman Fröhlich, Rolf Drechsler	LiM-HDL: HDL-Based Synthesis for In-Memory Computing.	DATE	2022	DBLP DOI BibTeX RDF
37	R. Peschke, K. Nishimura, G. Varner	ARGG-HDL: A High Level Python Based Object-Oriented HDL Framework.	CoRR	2020	DBLP BibTeX RDF
32	Ali Husein El-Mousa, Nasser Anssari, Ashraf Al-Suyyagh, Hamzah Al-Zubi	The Design of a USART IP Core.	World Congress on Engineering (Selected Papers)	2008	DBLP DOI BibTeX RDF	addressable USART, multi-drop networks, FPGA, Embedded systems, HDL, IP core
32	Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller	Emulation verification of the Motorola 68060.	ICCD	1995	DBLP DOI BibTeX RDF	emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level
31	Choudhury A. Rahman, Wael M. Badawy	A quarter pel full search block motion estimation architecture for H.264/AVC.	ICME	2005	DBLP DOI BibTeX RDF	CIF frame sequence, quarter pel full search, block motion estimation architecture, H.264-AVC encoder, Xilinx Virtex2 FPGA, field programmable gate array, hardware description language, Verilog HDL
31	Sasha Novakovsky, Shy Shyman, Ziyad Hanna	High capacity and automatic functional extraction tool for industrial VLSI circuit designs.	ICCAD	2002	DBLP DOI BibTeX RDF	Formal Equivalence Verification (FEV), Hardware Description Languages (HDL), Switch Level Analysis, functional abstraction, satisfiability procedures, synthesis, Design For Testability (DFT), logic simulation, Binary Decision Diagrams (BDDs)
31	Marcel Jacomet, Roger Wälti, Lukas Winzenried, Jaime Perez, Martin Gysel	ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test bench, test machine, CAT-tool, ProTest, FPGA, VHDL, rapid prototyping, Verilog-HDL
29	Jacob N. Allen, Hoda S. Abdel-Aty-Zohdy, Robert L. Ewing	Agile hardware development with rapid hardware definition language.	EIT	2009	DBLP DOI BibTeX RDF
29	Indradeep Ghosh	High Level Test Generation for Custom Hardware: An Industrial Perspective.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
29	Masaharu Imai, Akira Kitajima	Verification Challenges in Configurable Processor Design with ASIP Meister.	CHARME	2005	DBLP DOI BibTeX RDF
29	Kausik Datta, Partha Pratim Das	Assertion Based Verification Using HDVL.	VLSI Design	2004	DBLP DOI BibTeX RDF
29	Lijun Li, Hai Huang, Carl Tropper	DVS: An Object-Oriented Framework for Distributed Verilog Simulation.	PADS	2003	DBLP DOI BibTeX RDF
29	Raik Brinkmann, Rolf Drechsler	RTL-Datapath Verification using Integer Linear Programming.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
29	Philippe Poure, Fabrice Aubépart, Francis Braun	A Design Methodology for Hardware Prototyping of Integrated AC Drive Control: Application to Direct Torque Control of an Induction Machine.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF
29	Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra	Hierarchical Simulation of a Multiprocessor Architecture.	ICCD	2000	DBLP DOI BibTeX RDF
29	Richard Goering, Clifford E. Cummings, Steven E. Schulz, Simon Davidman, John Sanguinetti, Joachim Kunkel, Oz Levia	The future of system design languages (panel session).	DAC	2000	DBLP DOI BibTeX RDF
29	B. Romanowicz, M. Laudon, P. Lerch, Philippe Renaud, Hans Peter Amann, A. Boegli, Vincent Moser, Fausto Pellandini	Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language.	ED&TC	1997	DBLP DOI BibTeX RDF
29	Stan Y. Liao, Steven W. K. Tjiang, Rajesh K. Gupta 0001	An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment.	DAC	1997	DBLP DOI BibTeX RDF	C++
29	Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly	CONLAN: a formal construction method for hardware description languages: basic principles.	AFIPS National Computer Conference	1980	DBLP DOI BibTeX RDF
28	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou	Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
28	Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang	A fast two-pass HDL simulation with on-demand dump.	ASP-DAC	2008	DBLP DOI BibTeX RDF
28	Encarnación Castillo, Uwe Meyer-Bäse, Antonio García 0001, Luis Parrilla 0001, Antonio Lloris-Ruíz	IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
28	Panagiotis D. Vouzis, Caroline Collange, Mark G. Arnold	Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction.	DSD	2007	DBLP DOI BibTeX RDF
28	Encarnación Castillo, Luis Parrilla 0001, Antonio García 0001, Uwe Meyer-Bäse, Antonio Lloris-Ruíz	Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting.	FPL	2007	DBLP DOI BibTeX RDF
28	Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev, Yana Yankova, Vlad Mihai Sima, Kamana Sigdel, Roel Meeuws, Stamatis Vassiliadis	HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation.	FPL	2007	DBLP DOI BibTeX RDF
28	Margrit R. Krug, Marcelo Lubaszewski, Marcelo de Souza Moraes	Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
28	Hessa Al-Junaid, Tom J. Kazmierski	HDL models of ferromagnetic core hysteresis using timeless discretisation of the magnetic slope.	DATE	2006	DBLP DOI BibTeX RDF
28	Robert M. Senger, Eric D. Marsman, Gordy A. Carichner, Sundus Kubba, Michael S. McCorquodale, Richard B. Brown	Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking.	ISCAS	2006	DBLP DOI BibTeX RDF
28	Mihai Udrescu, Lucian Prodan, Mircea Vladutiu	The Bubble Bit Technique as Improvement of HDL-Based Quantum Circuits Simulation.	Annual Simulation Symposium	2005	DBLP DOI BibTeX RDF
28	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou	Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
28	Elena Dubrova	Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
28	Raymond Hoare, Shen Chih Tung	Combining Mentor Graphics? HDL Designer FPGA Flow with a Reconfigurable System on a Programmable Chip, Educational Opportunity or Insanity?	MSE	2003	DBLP DOI BibTeX RDF
28	Farzan Fallah, Pranav Ashar, Srinivas Devadas	Functional vector generation for sequential HDL models under an observability-based code coverage metric.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
28	Jian Li 0061, Rajesh K. Gupta 0001	HDL presynthesis optimizations using a tabular model.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
28	Chien-Nan Jimmy Liu, Jing-Yang Jou	An Automatic Controller Extractor for HDL Descriptions at the RTL.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
28	Ivan Blunno, Luciano Lavagno	Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL.	ASYNC	2000	DBLP DOI BibTeX RDF
28	Marcelino B. Santos, João Paulo Teixeira 0001	Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL.	DATE	1999	DBLP DOI BibTeX RDF
28	Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin	Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy.	ISPD	1998	DBLP DOI BibTeX RDF
28	Rajesh K. Gupta 0001, Daniel Gajski, Randy Allen, Yatin Trivedi	Opportunities and pitfalls in HDL-based system design.	ICCD	1996	DBLP DOI BibTeX RDF	textual Hardware Description Languages, system designs, VHDL, modeling language, hardware description languages, Verilog, HDLs, hardware systems
28	Yaohan Chu, Donald L. Dietmeyer, James R. Duley, Fredrick J. Hill, Mario Barbacci, Charles W. Rose, Greg M. Ordy, Bill Johnson, Martin Roberts	Three Decades of HDLs: Part I, CDL Through TI-HDL.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
22	Brian Butka, Janusz Zalewski, Andrew J. Kornecki	Issues in Tool Qualification for Safety-Critical Hardware: What Formal Approaches Can and Cannot Do.	SAFECOMP	2009	DBLP DOI BibTeX RDF	Tool Qualification, Formal Methods, Safety-Critical Systems, Hardware Design, HDL, PLD
22	Christopher T. Johnston, Paul J. Lyons, Donald G. Bailey	User evaluation and overview of a visual language for real time image processing on FPGAs.	CHINZ	2009	DBLP DOI BibTeX RDF	FPGA, image processing, visual programming language, HDL
22	Alexander B. Smirnov, Alexander Taubin, Ming Su, Mark G. Karpovsky	An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library.	ACSD	2005	DBLP DOI BibTeX RDF	asynchronous EDA, QDI, synthesis, ASIC, HDL
22	Dave Protheroe, Francesco Pessolano	An Objective Measure of Digital System Design Quality.	ISQED	2000	DBLP DOI BibTeX RDF	Design, Specification, Metrics, Quality, VHDL, Digital, Circuit, HDL
22	Sy Wong, Gertrude Levine	Kernel Ada to Unify Hardware and Software Design.	SIGAda	1998	DBLP DOI BibTeX RDF	Ada, Ada, VHDL, EDA, hardware description language, HDL
21	Azam Beg, Faheem Ahmed, Piers Campbell	Hybrid OCR Techniques for Cursive Script Languages - A Review and Applications.	CICSyN	2010	DBLP DOI BibTeX RDF	hand-writing recognition, Arabic OCR, Farsi/Persian OCR, Urdu OCR, HDL models, optical character recognition, hardware implementation, Text recognition
21	Xiumin Wang, Yang Zhang, Qiang Ye, Shihua Yang	A New Algorithm for Designing Square Root Calculators Based on FPGA with Pipeline Technology.	HIS (1)	2009	DBLP DOI BibTeX RDF	FPGA, algorithm, pipeline, square root, Verilog HDL
21	Yang Zhang, Xiumin Wang, Yuduo Wang	A New Design of HDB3 Encoder and Decoder Based on FPGA.	HIS (1)	2009	DBLP DOI BibTeX RDF	HDB3, FPGA, encoder, decoder, Verilog HDL
21	K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti 0001, Vivekananda M. Vedula	Power Virus Generation Using Behavioral Models of Circuits.	VTS	2007	DBLP DOI BibTeX RDF	Dynamic power dissipation, Power virus, Integer Constraint Solvers, Hardware Description Languages (HDL), Behavioral Models
21	Salvador Mir, Libor Rufer, Bernard Courtois	On-chip testing of embedded transducers.	VLSI Design	2004	DBLP DOI BibTeX RDF	failure mechanisms, A-HDL, fault modeling, fault simulation, defects, MEMS, self-test
21	Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto	System-Level Design of IEEE1394 Bus Segment Bridge.	ISSS	2002	DBLP DOI BibTeX RDF	HW/SW co-simulation, IEEE1394, PLI, bus bridge, C/C++, verilog-HDL
20	Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao	Fortifying analog models with equivalence checking and coverage analysis.	DAC	2010	DBLP DOI BibTeX RDF	analog validation, model-first design, design methodology, fault coverage, equivalence checking, formal validation
20	Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran	Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	converter synthesis, protocol compatibility, System-on-chip, automatic design
20	Florian Eibensteiner, Rainer Findenig, Markus Pfaff	SynPSL: Behavioral Synthesis of PSL Assertions.	EUROCAST	2009	DBLP DOI BibTeX RDF	Synthesis, PSL, Assertion-based Verification
20	Michael T. Frederick, Arun K. Somani	Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	carry chain, depth optimal mapping, logic chain
20	Sankalita Saha, Jason Schlessman, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Wayne H. Wolf	An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications.	DATE	2008	DBLP DOI BibTeX RDF
20	Leran Wang, Tom J. Kazmierski, Bashir M. Al-Hashimi, Stephen P. Beeby, Russel N. Torah	Integrated approach to energy harvester mixed technology modelling and performance optimisation.	DATE	2008	DBLP DOI BibTeX RDF
20	Karl Meier, Alessandro Forin	Hardware Compilation from Machine Code with M2V.	FCCM	2008	DBLP DOI BibTeX RDF
20	Sangeetha Sudhakrishnan, Liying Su, Jose Renau	Processor Verification with hwBugHunt.	ISQED	2008	DBLP DOI BibTeX RDF
20	Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang	Simulation Acceleration with HW Re-Compilation Avoidance.	VLSI Design	2008	DBLP DOI BibTeX RDF
20	John R. Shell, Yonglian Wang, Nazeih M. Botros	Biological Mechanism on a Chip: Modeling and Realization of Growth Hormone Secretion Mechanism.	BIBE	2007	DBLP DOI BibTeX RDF
20	Yan Lin Aung, Douglas L. Maskell, Timothy F. Oliver, Bertil Schmidt, William Bong	C-Based Design Methodology for FPGA Implementation of ClustalW MSA.	PRIB	2007	DBLP DOI BibTeX RDF	ClustalW, FPGA, multiple sequence alignment, sequence analysis
20	Walid A. Najjar	Compiling code accelerators for FPGAs.	CASES	2007	DBLP DOI BibTeX RDF	FPGA code acceleration
20	Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham	Reducing verification overhead with RTL slicing.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	verification, test, CAD
20	Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand	Assessment of Message Missing Failures in FlexRay-Based Networks.	PRDC	2007	DBLP DOI BibTeX RDF
20	Hessa Al-Junaid, Tom J. Kazmierski, Peter R. Wilson, Jerzy Baranowski	Timeless Discretization of Magnetization Slope in the Modeling of Ferromagnetic Hysteresis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
20	Liang Zhang 0012, Indradeep Ghosh, Michael S. Hsiao	A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF