Search results for "HP-RISC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	Ciji Isen, Lizy K. John, Eugene John	A Tale of Two Processors: Revisiting the RISC-CISC Debate.	SPEC Benchmark Workshop	2009	DBLP DOI BibTeX RDF
76	Liwen Shih	Microprogramming heritage of RISC design.	MICRO	1990	DBLP BibTeX RDF
73	Krishna V. Palem, Barbara B. Simons	Scheduling Time-Critical Instructions on RISC Machines.	ACM Trans. Program. Lang. Syst.	1993	DBLP DOI BibTeX RDF	RISC machine scheduling, NP-complete, latency, compiler optimization, register allocation, greedy algorithm, instruction scheduling, deadline, RISC, pipeline processor
69	Michel J. Daydé, Iain S. Duff	The RISC BLAS: a blocked implementation of level 3 BLAS for RISC processors.	ACM Trans. Math. Softw.	1999	DBLP DOI BibTeX RDF	matrix-matrix kernels, blocking, loop-unrolling, level 3 BLAS, RISC processors
58	Marco Aurélio Cavalcanti Pacheco, Philip C. Treleaven	A Risc Architecture to Support Neural Net Simulation.	IWANN	1993	DBLP DOI BibTeX RDF
56	Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong-Sang Kim	An Accurate Worst Case Timing Analysis for RISC Processors.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	pipelined execution, real-time system, Cache memory, worst case execution time, RISC processor
54	Farooq Butt	Porting the mcc PowerPC C/C++ Compiler into an Interactive Development Environment.	ACM SIGPLAN Notices	1996	DBLP DOI BibTeX RDF	C++
54	Charles D. Norton	The International Workshop on Parallel C++ (IWPC++), Kanazawa, Ishikawa Prefecture, Japan.	ACM SIGPLAN Notices	1996	DBLP DOI BibTeX RDF	C++
49	Sofiène Tahar, Ramayya Kumar	Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL.	TPHOLs	1994	DBLP DOI BibTeX RDF
47	Ioannis Panagopoulos, Christos Pavlatos, George K. Papakonstantinou	A hardware extension of the RISC microprocessor for Attribute Grammar evaluation.	SAC	2004	DBLP DOI BibTeX RDF	RISC microprocessors, Attribute Grammars, declarative programs
47	Krishna V. Palem, Barbara B. Simons	Scheduling Time-Critical Instructions on RISC Machines.	POPL	1990	DBLP DOI BibTeX RDF	RISC
47	Margaret L. Simmons, Harvey J. Wasserman	Performance evaluation of the IBM RISC System/6000: comparison of an optimized scalar processor with two vector processors.	SC	1990	DBLP DOI BibTeX RDF	RISC
47	Christopher F. Clark	The JADE interpreter: a RISC interpreter for syntax directed editing.	PLDI	1987	DBLP DOI BibTeX RDF	RISC
47	Richard B. Kieburtz	A RISC Architecture for Symbolic Computation.	ASPLOS	1987	DBLP DOI BibTeX RDF	RISC
45	Nikolaos Kavvadias, Spiridon Nikolaidis 0001	Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Optimization, Microprocessors, Hardware description languages, Real-time and embedded systems, Pipeline processors, Control design
43	Rishiyur S. Nikhil	Can Dataflow Subsume von Neumann Computing?	ISCA	1989	DBLP DOI BibTeX RDF	RISC
42	Bob Wilkinson, Lawrence S. Mulholland	An Implementation of the BLAS on the i860: A RISC Approach to Software for RISC Devices.	CONPAR	1992	DBLP DOI BibTeX RDF	Fortran, linear algebra, RISC, BLAS, hierarchical memory
40	Xiaoyong Chen, Douglas L. Maskell	M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors.	ARCS	2006	DBLP DOI BibTeX RDF
40	Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek	Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration.	FPL	2004	DBLP DOI BibTeX RDF
40	Jiyang Kang, Jongbok Lee, Wonyong Sung	A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	code converter, compiler-friendly, performance evaluation, digital signal processor, architecture synthesis
40	Chris R. Jesshope, Bing Luo	Micro-Threading: A New Approach to Future RISC.	ACAC	2000	DBLP DOI BibTeX RDF
40	Edgar Holmann, Toyohiko Yoshida, Akira Yamada 0005, Shin-ichi Uramoto	Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
40	Olivier Maquelin, Herbert H. J. Hum, Guang R. Gao	Costs and Benefits of Multithreading with Off-the-Shelf RISC Processors.	Euro-Par	1995	DBLP DOI BibTeX RDF
40	Kai Hwang 0001, Michel Dubois 0001, Dhabaleswar K. Panda 0001, S. Rao, Shisheng Shang, Aydin Üresin, W. Mao, H. Nair, M. Lytwyn, F. Hsieh, J. Liu, Sharad Mehrotra, Chien-Ming Cheng	OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses.	ICS	1990	DBLP DOI BibTeX RDF
38	Erik Buchanan, Ryan Roemer, Hovav Shacham, Stefan Savage	When good instructions go bad: generalizing return-oriented programming to RISC.	CCS	2008	DBLP DOI BibTeX RDF	return-into-libc, return-oriented programming, RISC, SPARC
38	Salah Merniz, Mohamed Benmohammed	A Scalable Proof Methodology for RISC Processor Designs: A Functional Approach.	ITNG	2008	DBLP DOI BibTeX RDF	State functions, RISC designs, Formal Verification, Functional programming, Micro-architectures
38	Yunquan Zhang, Ying Chen, Yuan Tang	Block size selection of parallel LU and QR on PVP-based and RISC-based supercomputers.	China HPC	2007	DBLP DOI BibTeX RDF	LU, PVP, optimal parallel block size, RISC, ScaLAPACK, QR
38	Tsung-Han Tsai 0001, Ren-Jr Wu, Liang-Gee Chen	A Cost-Effective Design for MPEG-2 Audio Decoder with Embedded RISC Core.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	degrouping, synthesis filterbank, RISC, MPEG-2, multichannel
38	Marco Antonio Dal Poz, Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo	A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications.	ASAP	2000	DBLP DOI BibTeX RDF	FPGA, VHDL, Reconfigurable Computing, Microprocessor, MPEG, RISC, Co-Design, Instruction Set, HDTV, Set-Top-Box, iDCT, cable TV
38	Valentina Salapura, Michael Gschwind	Hardware/Software Co-Design of a Fuzzy RISC Processor.	DATE	1998	DBLP DOI BibTeX RDF	hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism
38	Zhen Guo, He Li, Shuling Guo, Dongsheng Wang	Design and Simulation of a RISC-Based 32-bit Embedded On-Board Computer.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF	Hardware/Software, Simulation, Design, Embedded System, EDA, RISC
38	Kanad Ghose, Pavel Vasek	A Fast Capability Extension to a RISC Architecture.	EUROMICRO	1996	DBLP DOI BibTeX RDF	fast capability extension, RISC architecture, capability-based addressing, capability-based machines, simulated executions, security, information sharing, reduced instruction set computing, performance penalty
38	Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa	A superscalar RISC processor with pseudo vector processing feature.	ICCD	1995	DBLP DOI BibTeX RDF	superscalar RISC processor, pseudo vector processing, architectural extension, floating-point registers, scoreboard-based dependency check, pipeline stage optimization, 267 MFLOPS, 1.2 Gbyte/s, performance evaluation, performance, computer architecture, memory access, reduced instruction set computing, vector processor systems
38	Thomas Scholz, Michael Schäfers 0003	An improved dynamic register array concept for high-performance RISC processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	dynamic register array concept, high-performance RISC processors, processor registers, Multi Windows, Threaded Windows, dynamic register array, dynamic register allocation, general purpose registers, fast context switches, short interrupt latency, exception routines, real time systems, data structures, data structures, interrupts, storage allocation, external memory, registers, reduced instruction set computing
38	Manuel L. Anido, David J. Allerton, Ed Zaluska	A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine.	ISCA	1989	DBLP DOI BibTeX RDF	Computer Image Generation, Computer Architecture, VLSI Design, Interprocessor Communication, RISC, Reduced Instruction Set Computers
38	William R. Bush, A. Dain Samples, David M. Ungar, Paul N. Hilfinger	Compiling Smalltalk-80 to a RISC.	ASPLOS	1987	DBLP DOI BibTeX RDF	RISC, Smalltalk-80
36	Chien-Kuo V. Tien, Kelvin Lewis, Hans J. Greub, Tom Tsen, John F. McDonald 0001	Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
34	Ioannis Panagopoulos, Christos Pavlatos, George K. Papakonstantinou	An Embedded Microprocessor for Intelligent Control.	J. Intell. Robotic Syst.	2005	DBLP DOI BibTeX RDF	embedded systems, logic programming, microprocessor, intelligent control, RISC, declarative programs
34	Gaetano Borriello, Andrew R. Cherenson, Peter B. Danzig, Michael N. Nelson	RISCs versus CISCs for Prolog: A Case Study.	ASPLOS	1987	DBLP DOI BibTeX RDF	Prolog, RISC, CISC
31	Cheol-Hong Moon, Woo-Chun Jang	Implementation of LED Array Color Temperature Controlled Lighting System Using RISC IP Core.	ICIC (1)	2009	DBLP DOI BibTeX RDF
31	Josef Börcsök, Ali Hayek, Muhammad Umar	Implementation of a 1oo2-RISC-architecture on FPGA for safety systems.	AICCSA	2008	DBLP DOI BibTeX RDF
31	Xuehai Qian, He Huang, Hao Zhang 0009, Guoping Long, Junchao Zhang, Dongrui Fan	Design and Implementation of Floating Point Stack on General RISC Architecture.	PDP	2007	DBLP DOI BibTeX RDF
31	Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf	Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications.	ICSAMOS	2006	DBLP DOI BibTeX RDF
31	Kiyofumi Tanaka	Casablanca II: Implementation of a Real-Time RISC.	ASAP	2005	DBLP DOI BibTeX RDF
31	Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen	A unified processor architecture for RISC & VLIW DSP.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	dual-core processor, register organization, variable-length instruction encoding, digital signal processor
31	Sascha Wennekers, Christian Siemers	Reconfigurable RISC - A New Approach for Space-Efficient Superscalar Microprocessor Architecture.	ARCS	2002	DBLP DOI BibTeX RDF
31	Johann Großschädl	Instruction Set Extension for Long Integer Modulo Arithmetic on RISC-Based Smart Cards.	SBAC-PAD	2002	DBLP DOI BibTeX RDF
31	Marc Campbell	Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications.	LCTES	1998	DBLP DOI BibTeX RDF
31	Ali Maamar, G. Russell	A 32-Bit Risc Processor with Concurrent Error Detection.	EUROMICRO	1998	DBLP DOI BibTeX RDF
31	V. J. Fazio, R. D. Pose	Distributed Route Initialization Algorithms for the Monash Secure RISC Multiprocessor.	HICSS (5)	1997	DBLP DOI BibTeX RDF
31	Luigi Carro, Altamiro Amadeu Susin	A Risc Architecture to Explore HW/SW Parallelism in HW/SW Co-Design.	ECBS	1996	DBLP DOI BibTeX RDF
31	Pedro Furtado 0001, Henrique Madeira	Fault Injection Evaluation of Assigned Signatures in a RISC Processor.	EDCC	1996	DBLP DOI BibTeX RDF
31	Rajiv Gupta 0001, Michael Epstein, Michael Whelan	The design of a RISC based multiprocessor chip.	SC	1990	DBLP DOI BibTeX RDF
31	M. Castan, Elliott I. Organick	µ3L: An HLL-RISC processor for parallel execution of FP-language programs.	ISCA	1982	DBLP BibTeX RDF	FP
31	David A. Patterson 0001, Richard S. Piepho	RISC assessment: A high-level language experiment.	ISCA	1982	DBLP BibTeX RDF
29	Hans Eberle	Architektur moderner RISC-Mikroprozessoren.	Inform. Spektrum	1997	DBLP DOI BibTeX RDF	Mikroprozessoren, Pipelineverarbeitung, Cachespeicher, RISC
29	Stephanie Dogimont, Martin Gumm, Friederich Mombers, Daniel Mlynek, Alessandro Torielli	Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture.	ASAP	1997	DBLP DOI BibTeX RDF	RISC CPU, parallel multimedia architecture, high performance control structure, parallel motion estimation architecture, MPEG2 coding, combined MIMD-SIMD approach, motion estimation, ASIP, subword parallelism, embedded controller
29	Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu	ARAS: asynchronous RISC architecture simulator.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous RISC architecture simulator, ARAS, pipeline instruction simulator, benchmark programs, pipeline configuration, asynchronous pipeline architectures, performance evaluation, parallel architectures, virtual machines, performance measurements, pipeline processing
29	John-David Wellman, Edward S. Davidson	The resource conflict methodology for early-stage design space exploration of superscalar RISC processors.	ICCD	1995	DBLP DOI BibTeX RDF	resource conflict methodology, early-stage design space exploration, superscalar RISC processors, execution trace driven simulation, hardware element model, analysis program, performance evaluation, virtual machines, computer architecture, reduced instruction set computing, design cycle
29	Ramayya Kumar, Sofiène Tahar	Formal verification of pipeline conflicts in RISC processors.	EURO-DAC	1994	DBLP DOI BibTeX RDF	RISC
29	Hidekazu Terai, Kazutoshi Gemma, Yohsuke Nagao, Yasuo Satoh, Yasuhiro Ohno	Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1.	DAC	1994	DBLP DOI BibTeX RDF	RISC
29	David H. Bailey	RISC microprocessors and scientific computing.	SC	1993	DBLP DOI BibTeX RDF	RISC, Intel i860
29	John Wood, Harold C. Grossman	Interprocedural register allocation for RISC machines.	ACM Southeast Regional Conference	1992	DBLP DOI BibTeX RDF	Interprocedural Register Allocation, RISC Computer, Webs, Graph Coloring
29	Kristy Andrews, Duane Sand	Migrating a CISC Computer Family onto RISC via Object Code Translation.	ASPLOS	1992	DBLP DOI BibTeX RDF	RISC, CISC
29	C. Brian Hall, Kevin O'Brien	Performance Characteristics of Architectural Features of the IBM RISC System/6000.	ASPLOS	1991	DBLP DOI BibTeX RDF	RISC, VAX
29	Dileep Bhandarkar, Douglas W. Clark	Performance From Architecture: Comparing a RISC and CISC with Similar Hardware Organization.	ASPLOS	1991	DBLP DOI BibTeX RDF	RISC, CISC
29	Walter A. Helbig, Veljko M. Milutinovic	A DCFL E/D-MESFET GaAs Experimental RISC Machine.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	RCA, DCFL E/D-MESFET, RISC machine, GaAs microprocessor, instruction execution sequence, III-V semiconductors, microprocessor chips, instruction set architecture, software environment, reduced instruction set computing, 32 bit, field effect integrated circuits, gallium arsenide
29	Yashwant K. Malaiya, Sheng Feng	Design of a testable RISC-to-CISC control architecture.	MICRO	1988	DBLP BibTeX RDF	RISC
29	Manuel Alfonseca 0001, David Selby	APL2 - A RISC Business.	APL	1988	DBLP DOI BibTeX RDF	IBM System/370, APL, RISC, IBM PC
29	Jack W. Davidson, Joseph V. Gresh	Cint: a RISC interpreter for the C programming language.	PLDI	1987	DBLP DOI BibTeX RDF	C, RISC
29	Yuval Tamir, Carlo H. Séquin	Strategies for Managing the Register File in RISC.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	VLSI processor, Cache fetch strategies, register file management, computer architecture, RISC, procedure calls
27	Wolfgang Windsteiger, Bruno Buchberger, Markus Rosenkranz	Theorema.	The Seventeen Provers of the World	2006	DBLP DOI BibTeX RDF
27	Fei Gao, Suleyman Sair	Exploiting Intra-function Correlation with the Global History Stack.	SAMOS	2005	DBLP DOI BibTeX RDF
27	Wayne Lyons	Meeting the Embedded Design Needs of Automotive Applications.	DATE	2005	DBLP DOI BibTeX RDF
27	V. Parthasarathy, S. Aram valartha Bharathi, V. Rhymend Uthariaraj	Performance Analysis of Embedded Media Applications in Newer ARM Architectures.	ICPP Workshops	2005	DBLP DOI BibTeX RDF	ARM v6, DSP Extensions, Instruction set architecture (ISA), Single Instruction Multiple Data (SIMD)
27	Shiliang Hu, James E. Smith 0001	Using Dynamic Binary Translation to Fuse Dependent Instructions.	CGO	2004	DBLP DOI BibTeX RDF
27	Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses	A Flexible H.263 Video Coder Prototype Based on FPGA.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
27	Rolf B. Hilgendorf, Wolfram Sauer	Instruction translation for an experimental S/390 processor.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF	IBM System/390
27	Naehyuck Chang, Kwanho Kim, Hyung Gyu Lee	Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI.	ISLPED	2000	DBLP DOI BibTeX RDF
27	Ryuichi Takahashi, Noriyoshi Yoshida	Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1.	MSE	1999	DBLP DOI BibTeX RDF
27	Giuliano Donzellini, Stefano Nervi, Domenico Ponta, Sergio Rossi, Stefano Rovetta	Object Oriented ARM7 Coprocessor.	HICSS (3)	1998	DBLP DOI BibTeX RDF
26	Yao-Ming Kuo, Mark F. Flanagan, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro	Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension.	IEEE Trans. Aerosp. Electron. Syst.	2023	DBLP DOI BibTeX RDF
26	Nick Brown 0001, Maurice Jamieson, Joseph K. L. Lee, Paul Wang	Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU.	CoRR	2023	DBLP DOI BibTeX RDF
26	Loïc Buckwell, Olivier Gilles, Daniel Gracia Pérez, Nikolai Kosmatov	Execution at RISC: Stealth JOP Attacks on RISC-V Applications.	CoRR	2023	DBLP DOI BibTeX RDF
26	Loïc Buckwell, Olivier Gilles, Daniel Gracia Pérez, Nikolai Kosmatov	Execution at RISC: Stealth JOP Attacks on RISC-V Applications.	ESORICS Workshops (2)	2023	DBLP DOI BibTeX RDF
26	Lukas Gerlach 0001, Daniel Weber 0007, Ruiyi Zhang, Michael Schwarz 0001	A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs.	SP	2023	DBLP DOI BibTeX RDF
26	Nick Brown 0002, Maurice Jamieson, Joseph K. L. Lee, Paul Wang	Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU.	SC Workshops	2023	DBLP DOI BibTeX RDF
26	Rieul Ducousso	Sécurisation des accès aux périphériques et depuis les périphériques dans une architecture multicœur RISC-V utilisée pour la virtualisation. (Securing access to and from devices in a RISC-V multicore architecture used for virtualization).		2023	RDF
26	Farhad Taheri, Siavash Bayat Sarmadi, Shahriar Hadayeghparast	RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference.	IEEE Internet Things J.	2022	DBLP DOI BibTeX RDF
26	Olivier Gilles, Franck Viguier, Nikolai Kosmatov, Daniel Gracia Pérez	Control-Flow Integrity at RISC: Attacking RISC-V by Jump-Oriented Programming.	CoRR	2022	DBLP DOI BibTeX RDF
26	Nils-Johan Wessman, Fabio Malatesta, Stefano Ribes, Jan Andersson, Antonio García-Vilanova, Miguel Masmano, Vicente Nicolau, Paco Gomez, Jimmy Le Rhun, Sergi Alcaide, Guillem Cabo, Francisco Bas, Pedro Benedicte, Fabio Mazzocchetti, Jaume Abella 0001	De-RISC: A Complete RISC-V Based Space-Grade Platform.	DATE	2022	DBLP DOI BibTeX RDF
26	Christopher Nitta, Aaron Kaloti, Shuotong Wang	RISC-V Console: A Containerized RISC-V Based Game Console Emulator for Education.	ITiCSE (1)	2022	DBLP DOI BibTeX RDF
26	Marc Reichenbach, Johannes Knödtel, Sebastian Rachuj, Dietmar Fey	RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems.	IEEE Access	2021	DBLP DOI BibTeX RDF
26	Taoran Xiang, Lunkai Zhang, Shuqian An, Xiaochun Ye, Mingzhe Zhang, Yanhuan Liu, Mingyu Yan, Da Wang, Hao Zhang 0009, Wenming Li, Ninghui Sun, Dongrui Fan	RISC-NN: Use RISC, NOT CISC as Neural Network Hardware Infrastructure.	CoRR	2021	DBLP BibTeX RDF
26	Yu Liu, Kejiang Ye, Cheng-Zhong Xu 0001	Performance Evaluation of Various RISC Processor Systems: A Case Study on ARM, MIPS and RISC-V.	CLOUD	2021	DBLP DOI BibTeX RDF
26	Qiang Jiao, Wei Hu 0001, Fang Liu 0031, Yong Dong	RISC-VTF: RISC-V Based Extended Instruction Set for Transformer.	SMC	2021	DBLP DOI BibTeX RDF
26	Karyofyllis Patsidis, Chrysostomos Nicopoulos, Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos	RISC-V2: A Scalable RISC-V Vector Processor.	ISCAS	2020	DBLP DOI BibTeX RDF
26	Mark Akoev, Olga Moskaleva, Vladimir Pislyakov	Confidence and RISC: How Russian papers indexed in the national citation database Russian Index of Science Citation (RISC) characterize universities and research institutes.	CoRR	2018	DBLP BibTeX RDF
26	Christoph Baumhof, Frank Müller, Otto Müller, Manfred Schlett	A novel 32 bit RISC architecture unifying RISC and DSP.	ICASSP	1997	DBLP DOI BibTeX RDF
26	Ulrich Golze	Der RISC-Prozessor TOOBSIE - Hintergrundband zum Buch "VLSI-Entwurf eines RISC-Prozessors" für den Entwurfsspezialisten.		1995	RDF