Search results for "IDDQ"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
157	Srdjan Dragic, Martin Margala	A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test.	ISVLSI	2002	DBLP DOI BibTeX RDF	Current Amplifier, On-Line Testing, Iddq, delta Iddq, Current Monitoring
143	Chih-Wen Lu, Chauchin Su, Chung-Len Lee 0001, Jwu E. Chen	Is IDDQ testing not applicable for deep submicron VLSI in year 2011?	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	deep submicron VLSI, IDDQ current estimation, random process deviations, IDDQ distributions, VLSI, statistical analysis, integrated circuit testing, CMOS integrated circuits, leakage currents, IDDQ testing, statistical approach, standard deviation, input vectors, circuit size
133	Arabi Keshk, Kozo Kinoshita, Yukiya Miura	IDDQ Current Dependency on Test Vectors and Bridging Resistance.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Bridging fault, IDDQ Testing
128	Jan Schat	Evaluation of the Iddq Signature in devices with Gauss-distributed background current.	DDECS	2008	DBLP DOI BibTeX RDF
128	Yukio Okuda	Eigen-Signatures for Regularity-based IDDQ Testing.	VTS	2002	DBLP DOI BibTeX RDF
126	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita	Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	IDDQ measurement vector, sequential circuit, bridging fault, IDDQ testing
116	Ashutosh Sharma, Anura P. Jayasumana, Yashwant K. Malaiya	X-IDDQ: A Novel Defect Detection Technique Using IDDQ Data.	VTS	2006	DBLP DOI BibTeX RDF	Defect Correlation, Principal Component Analysis, IDDQ, Binning, Test Optimization
114	Masaru Sanada	A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq.	VTS	1996	DBLP DOI BibTeX RDF	CAD-based failure diagnosis technology, CMOS LSI, abnormal Iddq phenomenon, physical damage detection, faulty blocks, failure point localization, Iddq test patterns, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, circuit CAD, large scale integration
109	Chih-Wen Lu, Chung-Len Lee 0001, Chauchin Su, Jwu-E Chen	Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	VLSI, IDDQ testing, deep sub-micron
102	Paul Lee, Alfred Chen, Dilip Mathew	A Speed-Dependent Approach for Delta IDDQ Implementation.	DFT	2001	DBLP DOI BibTeX RDF	Self-scaling IDDQ, Speed Performance Index, characterization, Delta IDDQ
102	Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita	A high-speed IDDQ sensor implementation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit feedback, high-speed IDDQ sensor implementation, submicron CMOS process, feedback scheme, floppy-disk controller IDDQ test, current sensor, built-in sensor, 0.35 micron, 50 MHz, integrated circuit testing, CMOS digital integrated circuits, BICS, electric current measurement, electric sensing devices
102	B. Straka, Hans A. R. Manhaeve, Jozef Vanneuville, M. Svajda	A Fully Digital Controlled Off-Chip IDDQ Measurement Unit.	DATE	1998	DBLP DOI BibTeX RDF	IDDQ monitors, test hardware, CMOS, testability, integrated circuits, IDDQ
98	Claude Thibeault	On the Comparison of IDDQ and IDDQ Testing.	VTS	1999	DBLP DOI BibTeX RDF
92	Chintan Patel, Abhishek Singh 0001, Jim Plusquellic	Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement.	ITC	2004	DBLP DOI BibTeX RDF
92	Yukio Okuda, Nobuyuki Furukawa	Hysteresis of Intrinsic IDDQ Currents.	ITC	2003	DBLP DOI BibTeX RDF
92	C. P. Ravikumar, Rahul Kumar	Divide-and-Conquer IDDQ Testing for Core-Based System Chips.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
92	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF
92	Jerry M. Soden, Charles F. Hawkins	IDDQ Testing: Issues Present and Future.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
90	Chintan Patel, Abhishek Singh 0001, Jim Plusquellic	Defect Detection Using Quiescent Signal Analysis.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	multiple current measurements, Quiescent Signal Analysis, IDDQ, current testing, defect-based testing, parametric testing
90	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ.	ITC	1998	DBLP DOI BibTeX RDF	IDDQ Tes t, Configurable Logic Blocks, FPGA, Testing, Bridging Fault, Programming Phase
86	Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita	IDDQ Sensing Technique for High Speed IDDQ Testing.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
85	Alan W. Righter, Charles F. Hawkins, Jerry M. Soden, Peter C. Maxwell	CMOS IC reliability indicators and burn-in economics.	ITC	1998	DBLP DOI BibTeX RDF
85	Toshiyuki Maeda, Kozo Kinoshita	Compaction of IDDQ Test Sequence Using Reassignment Method.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	reassignment method, weighted random vector, sequential circuit, IDDQ testing, test compaction
85	Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara	On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	IDDQ testing, test compaction
85	Rosa Rodríguez-Montañés, Joan Figueras	Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs.	DATE	1998	DBLP DOI BibTeX RDF	IDDQ testability, CMOS, deep-submicron
85	Peter C. Maxwell	The use of IDDQ testing in low stuck-at coverage situations.	VTS	1995	DBLP DOI BibTeX RDF	stuck-at coverage situations, quality goal, graded coverage, composite metric, fault diagnosis, logic testing, logic tests, integrated circuit testing, automatic testing, application specific integrated circuits, ASIC, CMOS logic circuits, IDDQ testing, IC testing
80	Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy 0001	Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement.	DAC	2007	DBLP DOI BibTeX RDF
80	Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal	New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.	VLSI Design	2003	DBLP DOI BibTeX RDF
80	Shengli Li, Kai Zhang, Jien-Chung Lo	The 2nd Order Analysis of IDDQ Test Data.	DFT	2000	DBLP DOI BibTeX RDF
80	R. D. (Shawn) Blanton	IDDQ-Testability of Tree Circuits.	VLSI Design	1999	DBLP DOI BibTeX RDF
77	Sagar S. Sabade, D. M. H. Walker	Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification.	VLSI Design	2003	DBLP DOI BibTeX RDF	spatial correlation, IDDQ testing, delta IDDQ
77	Hisashi Kondo, Kwang-Ting Cheng	Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG.	ICCAD	1996	DBLP DOI BibTeX RDF	Selective IDDQ, Pseudo Stuck-at Fault, Sequential ATPG, Vector compaction, Test, Fault model, IDDQ, Leakage Fault
67	B. Straka, Hans A. R. Manhaeve, J. Brenkus, Stefaan Kerckenaere	Theoretical and Practical Aspects of IDDQ Settling-Impact on Measurement Timing and Quality.	DATE	2008	DBLP DOI BibTeX RDF
67	Chuen-Song Chen, Jien-Chung Lo, Tian Xia	Equivalent IDDQ Tests for Systems with Regulated Power Supply.	DFT	2006	DBLP DOI BibTeX RDF
67	Abhijit Prasad, D. M. H. Walker	Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors.	DFT	2003	DBLP DOI BibTeX RDF
67	Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota	Test Vector Generation Based on Correlation Model for Ratio-Iddq.	ITC	2003	DBLP DOI BibTeX RDF
67	Swarup Bhunia, Hai Li, Kaushik Roy 0001	A High Performance IDDQ Testable Cache for Scaled CMOS Technologies.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
67	Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni	Extending the Viability of IDDQ Testing in the Deep Submicron Era.	ISQED	2002	DBLP DOI BibTeX RDF
67	Sagar S. Sabade, D. M. H. Walker	Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction.	VTS	2002	DBLP DOI BibTeX RDF
67	Bram Kruseman, Stefan van den Oetelaar, Josep Rius 0001	Comparison of IDDQ Testing and Very-Low Voltage Testing.	ITC	2002	DBLP DOI BibTeX RDF
67	Zhanping Chen, Liqiong Wei, Kaushik Roy 0001	On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
67	Chintan Patel, Jim Plusquellic	A Process and Technology-Tolerant IDDQ Method for IC Diagnosis.	VTS	2001	DBLP DOI BibTeX RDF
67	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda	Testability Analysis of IDDQ Testing with Large Threshold Value.	DFT	2000	DBLP DOI BibTeX RDF
67	Zhanping Chen, Liqiong Wei, Kaushik Roy 0001	On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.	ISQED	2000	DBLP DOI BibTeX RDF
65	Hisashi Kondo, Kwang-Ting Cheng	An Efficient Compact Test Generator for IDDQ Testing.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	Selective IDDQ, Pattern Compaction, Pseudo Stuck-at Fault, Essential Fault, Test, ATPG, Fault Model, Testability, IDDQ, Leakage Fault
60	Jim Plusquellic, Dhruva Acharyya, Abhishek Singh 0001, Mohammad Tehranipoor, Chintan Patel	Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	Quiescent Signal Analysis, defect detection, IDDQ
60	Chuen-Song Chen, Jien-Chung Lo, Tian Xia	An indirect current sensing technique for IDDQ and IDDT tests.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	IDDT, IDDQ, current testing, BICS
60	Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni	An Embedded IDDQ Testing Architecture and Technique.	ISQED	2003	DBLP DOI BibTeX RDF	IEEE 1149.1, Design for Testability (DFT), Boundary Scan, IDDQ Testing
60	Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos	A Compact Built-In Current Sensor for IDDQ Testing.	IOLTW	2000	DBLP DOI BibTeX RDF	Bridging and Stuck-on fault testability, Design for testability, DFT, IDDQ testing, Built in current sensors, BICS, Current monitoring
60	Hugo Cheung, Sandeep K. Gupta 0001	A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study.	VTS	2000	DBLP DOI BibTeX RDF	critical severity, test escape, fault modeling, IDDQ, yield loss
60	Theo J. Powell, James R. Pair, Melissa St. John, Doug Counce	Delta Iddq for Testing Reliability.	VTS	2000	DBLP DOI BibTeX RDF	reliability, Iddq
60	Víctor H. Champac, José Castillejos, Joan Figueras	IDDQ Testing of Opens in CMOS SRAMs.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	data retention faults, memory testing, opens, IDDQ
60	Yinghua Min, Zhongcheng Li	IDDT Testing versus IDDQ Testing.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	IDDT test, IDDQ test, stuck-open fault, Boolean process
55	Bin Xue, D. M. H. Walker	Is IDDQ Test of Microprocessors Feasible?	MTV	2005	DBLP DOI BibTeX RDF
55	Sagar S. Sabade, D. M. H. Walker	Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests.	VLSI Design	2004	DBLP DOI BibTeX RDF
55	Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita	A BIST Circuit for IDDQ Tests.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
55	Chris Schuermyer, Brady Benware, Kevin Cota, Robert Madge, W. Robert Daasch, L. Ning	Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ.	ITC	2003	DBLP DOI BibTeX RDF
55	Sagar S. Sabade, D. M. H. Walker	IDDQ Test: Will It Survive the DSM Challenge?	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
55	Sagar S. Sabade, D. M. H. Walker	Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis.	DFT	2002	DBLP DOI BibTeX RDF
55	Claude Thibeault	Speeding-Up IDDQ Measurements.	VTS	2002	DBLP DOI BibTeX RDF
55	W. Robert Daasch, Kevin Cota, James McNames, Robert Madge	Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data.	ITC	2002	DBLP DOI BibTeX RDF
55	David I. Bergman, Hans Engler	Improved IDDQ Testing with Empirical Linear Prediction.	ITC	2002	DBLP DOI BibTeX RDF
55	Sagar S. Sabade, D. M. H. Walker	Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
55	Juan M. Díez, Juan Carlos López 0001	Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion.	DATE	2000	DBLP DOI BibTeX RDF
55	Sri Jandhyala, Hari Balachandran, Manidip Sengupta, Anura P. Jayasumana	Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs.	VTS	2000	DBLP DOI BibTeX RDF
55	Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita	Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
55	Manoj Sachdev	Deep sub-micron IDDQ testing: issues and solutions.	ED&TC	1997	DBLP DOI BibTeX RDF
49	Robert Madge, Manu Rehani, Kevin Cota, W. Robert Daasch	Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies.	VTS	2002	DBLP DOI BibTeX RDF
48	Sagar S. Sabade, D. M. H. Walker	Use of Multiple IDDQ Test Metrics for Outlier Identification.	VTS	2003	DBLP DOI BibTeX RDF	Current ratio, neighbor current ratio, outlier identification, spatial correlation, IDDQ testing
48	Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda	High speed IDDQ test and its testability for process variation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	high speed IDDQ test, charge current, gate load capacitances, test input vector application, CMOS IC production, logic testing, integrated circuit testing, process variation, testability, CMOS logic circuits, production testing
48	Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi	Cyclic greedy generation method for limited number of IDDQ tests.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	cyclic greedy generation method, undetected faults, ISCAS85Y circuits, short circuit faults, fault diagnosis, integrated circuit testing, iterative methods, iterative method, CMOS integrated circuits, IDDQ tests, test patterns, CMOS IC, electric current measurement, cyclic, random patterns
48	Claude Thibeault	Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm.	VTS	2000	DBLP DOI BibTeX RDF	probabilistic signatures, double faults, Diagnosis, Viterbi algorithm, Delta Iddq
48	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita	Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	sequential circuit, fault simulation, bridging fault, IDDQ testing
48	Tsuyoshi Shinogi, Terumine Hayashi	A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	compact test generation, parallel processing, ATPG, IDDQ testing
48	Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken	An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing.	VTS	1997	DBLP DOI BibTeX RDF	semiconductor testing, stuck-fault testing, ASIC device, application specific integrated circuits, functional testing, IDDQ testing, delay-fault testing, scan testing
48	Hari Balachandran, D. M. H. Walker	Improvement of SRAM-based failure analysis using calibrated Iddq testing.	VTS	1996	DBLP DOI BibTeX RDF	defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield
48	Jason P. Hurst, Adit D. Singh	A differential built-in current sensor design for high speed IDDQ testing.	VLSI Design	1995	DBLP DOI BibTeX RDF	built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices
43	Junichi Hirase, Yoshiyuki Goi, Yoshiyuki Tanaka	IDDQ Testing Method using a Scan Pattern for Production Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
43	Thomas J. Vogels	Effectiveness of I-V Testing in Comparison to IDDq Tests.	VTS	2003	DBLP DOI BibTeX RDF
43	Nobuhiro Sato, Yoshihiro Hashimoto	A High Precision IDDQ Measurement System With Improved Dynamic Load Regulation.	ITC	2003	DBLP DOI BibTeX RDF
43	Sreejit Chakravarty, Sujit T. Zachariah	STBM: a fast algorithm to simulate IDDQ tests forleakage faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
43	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	Bridging Fault Detection in FPGA Interconnects Using IDDQ.	FPGA	1998	DBLP DOI BibTeX RDF
43	M. Svajda, B. Straka, Hans A. R. Manhaeve	IOCIMU - An Integrated Off-Chip IDDQ Measurement Unit.	DATE	1998	DBLP DOI BibTeX RDF
43	Md. Altaf-Ul-Amin, Zahari Mohamed Darus	An Off-Chip Current Sensor for IDDQ Testing of CMOS ICs.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
43	B. Laquai, H. Richter, H. Werkmann	A production-oriented measurement method for fast and exhaustive Iddq tests.	ED&TC	1997	DBLP DOI BibTeX RDF
43	Don Douglas Josephson, Mark Storey, Daniel D. Dixon	Microprocessor IDDQ Testing: A Case Study.	IEEE Des. Test Comput.	1995	DBLP DOI BibTeX RDF
43	S. Wayne Bollinger, Scott F. Midkiff	Test generation for IDDQ testing of bridging faults in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
41	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001	Low-Power and testable circuit synthesis using Shannon decomposition.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
41	Anton Chichkov, Dirk Merlier, Peter Cox	Current Testing Procedure for Deep Submicron Devices.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	ASIC testing, IDDQ, deep submicron
41	Antonio Zenteno, Víctor H. Champac, Joan Figueras	Detectability Conditions of Full Opens in the Interconnections.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	logic testing, IDDQ testing, opens, defect modeling
41	Yukiya Miura, Hiroshi Yamazaki	A Low-Loss Built-In Current Sensor.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	low-voltage LSIs, multiple power supplies, IDDQ testing, Built-in current sensor
41	Claude Thibeault	Increasing Current Testing Resolution.	DFT	1998	DBLP DOI BibTeX RDF	current signatures, test, Integrated circuits, Iddq testing
41	Yinghua Min, Zhuxing Zhao, Zhongcheng Li	IDDT Testing.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	IDDT test, IDDQ test, stuck-open fault, Boolean process
38	Alexei Kaltchenko, Oleg Semenov	Temperature dependence of IDDQ distribution: application for thermal delta IDDQ testing.	IET Circuits Devices Syst.	2007	DBLP DOI BibTeX RDF
38	Carlo Dallavalle	Adaptive IDDQ: How to Set an IDDQ Limit for any Device Under Test.	IOLTW	2002	DBLP DOI BibTeX RDF
36	Ritesh P. Turakhia, Brady Benware, Robert Madge, Thaddeus T. Shannon, W. Robert Daasch	Defect Screening Using Independent Component Analysis on I_DDQ.	VTS	2005	DBLP DOI BibTeX RDF
36	Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins	Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
36	Wanli Jiang, Bapiraju Vinnakota	IC test using the energy consumption ratio.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
36	Josep Rius 0001, Luis Elvira Villagra, Maurice Meijer	A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits.	ETS	2009	DBLP DOI BibTeX RDF	IDDQ testing
36	Toshiyuki Maeda, Kozo Kinoshita	Memory reduction of IDDQ test compaction for internal and external bridging faults.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction