Search results for "Infrastructure-IP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26		Panel Summaries.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	IEEE European Test Symposium, IEEE Infrastructure IP Workshop, silicon debug, microelectronics, infrastructure IP
20	Yu Huang 0005, Wu-Tung Cheng	Using embedded infrastructure IP for SOC post-silicon verification.	DAC	2003	DBLP DOI BibTeX RDF	FPGA core, infrastructure IP (I-IP), post-silicon verification, transaction-based verification
16	Yervant Zorian	Leveraging Infrastructure IP for SoC Yield.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
16	Yervant Zorian	Embedded Memory Test and Repair: Infrastructure IP for SOC Yield.	ITC	2002	DBLP DOI BibTeX RDF
16	Yervant Zorian	Embedding infrastructure IP for SOC yield improvement.	DAC	2002	DBLP DOI BibTeX RDF	embedded test & repair, semiconductor IP, yield optimization, test resource partitioning
13	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	A System-layer Infrastructure for SoC Diagnosis.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	SoC diagnosis, Processor and UDL logic self-testing, Memory, Infrastructure-IP
13	Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas 0001, Massimo Violante	A New Hybrid Fault Detection Technique for Systems-on-a-Chip.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	SoC dependability, transient fault detection, infrastructure IP
13	Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green	Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	systematic yield loss, test structure, BEOL, DFM, process monitoring, silicon debug, infrastructure IP
13	Nikhil Bansal 0003, Kanishka Lahiri, Anand Raghunathan	Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis.	VLSI Design	2007	DBLP DOI BibTeX RDF
13	C. J. Clark, Mike Ricchetti	Infrastructure IP for Configuration and Test of Boards and Systems.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
13	Yervant Zorian, Samvel K. Shoukourian	Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
13	L. Forli, Jean-Michel Portal, Didier Née, Bertrand Borot	Infrastructure IP for Back-End Yield Improvement.	ITC	2003	DBLP DOI BibTeX RDF
12	C. J. Clark	Tutorial IND2B: Structured Embedded Configuration and Test.	VLSI Design	2007	DBLP DOI BibTeX RDF
10	Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante	Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Instruction hardening, SET, SEU, Infrastructure IP
10	Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh	Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP
10	André Ivanov, Giovanni De Micheli	Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	micronetworks, networks on chips, multiprocessor SoCs, on-chip interconnection network, on-chip communication, infrastructure IP
10	Praveen Bhojwani, Rabi N. Mahapatra	An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs.	ISQED	2007	DBLP DOI BibTeX RDF
10	Jui-Jer Huang, Jiun-Lang Huang	An Infrastructure IP for On-Chip Clock Jitter Measurement.	ICCD	2004	DBLP DOI BibTeX RDF
9	Jason D. Lee, Nikhil Gupta 0004, Praveen Bhojwani, Rabi N. Mahapatra	An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems.	ISQED	2008	DBLP DOI BibTeX RDF	test triggering, network on chip, on-line test
7	Xinmu Wang, Yu Zheng 0011, Abhishek Basak, Swarup Bhunia	IIPS: Infrastructure IP for Secure SoC Design.	IEEE Trans. Computers	2015	DBLP DOI BibTeX RDF
7	Chao-Da Huang, Jin-Fu Li 0001, Tsu-Wei Tseng	ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
7	R. Chandramouli	Infrastructure IP design for repair in nanometer technologies.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF
7	Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas 0001, Massimo Violante	On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core.	DSN	2005	DBLP DOI BibTeX RDF
7	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs.	ETS	2005	DBLP DOI BibTeX RDF
7	Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas 0001, Massimo Violante	Hybrid Soft Error Detection by Means of Infrastructure IP Cores.	IOLTS	2004	DBLP DOI BibTeX RDF
7	Yervant Zorian	Guest Editor's Introduction: Advances in Infrastructure IP.	IEEE Des. Test Comput.	2003	DBLP BibTeX RDF
7		Guest Editor's Introduction: What is Infrastructure IP?	IEEE Des. Test Comput.	2002	DBLP BibTeX RDF
6	Yervant Zorian, Juan Antonio Carballo	T1: Design for Manufacturability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
6	R. Chandramouli	Managing Test and Repair of Embedded Memory Subsystem in SoC.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
6	N. Derhacobian, Valery A. Vardanian, Yervant Zorian	Embedded Memory Reliability: The SER Challenge.	MTDT	2004	DBLP DOI BibTeX RDF
6	Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an I-IP for In-Field SOC Test.	DFT	2004	DBLP DOI BibTeX RDF
6	Eric Dupont, Michael Nicolaidis	Robustness IPs for Reliability and Security of SoCs.	ITC	2002	DBLP DOI BibTeX RDF
3	Jason D. Lee, Rabi N. Mahapatra	In-field NoC-based SoC testing with distributed test vector storage.	ICCD	2008	DBLP DOI BibTeX RDF
3	Ernesto Sánchez 0001, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda	Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor.	DATE	2007	DBLP DOI BibTeX RDF
3	Letícia Maria Veiras Bolzani, Paolo Bernardi, Matteo Sonza Reorda	An optimized hybrid approach to provide fault detection and correction in SoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	fault correction, SoCs, fault detection, hybrid approach
3	Paolo Bernardi, Ernesto Sánchez 0001, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda	An effective technique for minimizing the cost of processor software-based diagnosis in SoCs.	DATE	2006	DBLP DOI BibTeX RDF
3	Paolo Bernardi, Ernesto Sánchez 0001, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets.	MTV	2005	DBLP DOI BibTeX RDF
3	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores.	MTV	2005	DBLP DOI BibTeX RDF
3	Miron Abramovici, Charles E. Stroud, John Marty Emmert	Using embedded FPGAs for SoC yield improvement.	DAC	2002	DBLP DOI BibTeX RDF